CN113284802A - High electron mobility transistor and preparation method thereof - Google Patents
High electron mobility transistor and preparation method thereof Download PDFInfo
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- CN113284802A CN113284802A CN202110719930.2A CN202110719930A CN113284802A CN 113284802 A CN113284802 A CN 113284802A CN 202110719930 A CN202110719930 A CN 202110719930A CN 113284802 A CN113284802 A CN 113284802A
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 131
- 230000004888 barrier function Effects 0.000 claims abstract description 57
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 47
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims abstract description 45
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims abstract description 38
- 230000005641 tunneling Effects 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000000903 blocking effect Effects 0.000 claims description 46
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- KDYFGRWQOYBRFD-UHFFFAOYSA-N succinic acid Chemical compound OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000001384 succinic acid Substances 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- KDYFGRWQOYBRFD-NUQCWPJISA-N butanedioic acid Chemical compound O[14C](=O)CC[14C](O)=O KDYFGRWQOYBRFD-NUQCWPJISA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention provides a high electron mobility transistor and a preparation method thereof, relating to the technical field of semiconductors. And forming a first groove on the second N + type doping layer. And forming a second groove on the indium gallium arsenide etching barrier layer and the first N-type doped layer. And forming a third groove on the aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are communicated to be used as a grid groove. And depositing metal in the grid groove to form a grid electrode in contact with the low-energy gap tunneling layer. Because the low-energy-gap tunneling layer is inserted between the grid electrode and the barrier layer, and the indium gallium arsenide etching barrier layer is arranged between the first N-type doping layer and the second N + type doping layer, the ohmic contact resistance of the source electrode and the drain electrode can be effectively reduced, the on-resistance of the device is further reduced, and the performance of the device is convenient to improve.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-electron-mobility transistor and a preparation method thereof.
Background
A High Electron Mobility Transistor (HEMT), also known as a modulation doped field effect transistor, uses two materials with different energy gaps to form a heterojunction, which provides a channel for carriers. High electron mobility transistors can operate at very high frequencies and are therefore widely used in mobile phones, satellite television and radar.
When the existing high electron mobility transistor is used as a power device, a double-groove structure is usually adopted, namely, after a first etching barrier layer, an N-doping layer, a second etching barrier layer and an N + doping layer are sequentially formed on a barrier layer, two communicated grooves are formed on the first etching barrier layer, the N-doping layer, the second etching barrier layer and the N + doping layer, and a source electrode and a drain electrode which are in ohmic contact are also arranged on the N + doping layer.
Disclosure of Invention
The present invention is directed to a high electron mobility transistor and a method for fabricating the same, which can reduce the on-resistance of the device.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in one aspect of the embodiments of the present invention, a method for manufacturing a high electron mobility transistor is provided, where the method includes: forming a channel layer, a first isolating layer, a first doping layer, a barrier layer, a low-energy gap tunneling layer, an aluminum arsenide etching blocking layer, a first N-type doping layer, an indium gallium arsenide etching blocking layer and a second N + type doping layer on a substrate in sequence; depositing metal on the second N + type doping layer to form a source electrode and a drain electrode respectively; etching the second N + type doped layer in the region between the source electrode and the drain electrode and stopping at the indium gallium arsenide etching barrier layer to form a first groove; sequentially etching the indium gallium arsenide etching barrier layer and the first N-type doped layer in the first groove and stopping at the aluminum arsenide etching barrier layer to form a second groove; etching the aluminum arsenide etching barrier layer in the second groove and stopping at the low-energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to be used as grid grooves; and depositing metal in the grid groove to form a grid electrode in contact with the low-energy gap tunneling layer.
Optionally, a buffer layer is further formed between the substrate and the channel layer.
Optionally, a second doping layer and a second isolation layer on the buffer layer are sequentially formed between the buffer layer and the channel layer.
Optionally, the low-bandgap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.
Optionally, etching the second N + -type doped layer in the region between the source and the drain and terminating at the ingaas etching stop layer to form the first recess includes: and etching the second N + type doped layer in the region between the source electrode and the drain electrode by using citric acid and stopping at the indium gallium arsenide etching barrier layer to form a first groove.
Optionally, the sequentially etching the indium gallium arsenide etching blocking layer and the first N-type doped layer in the first groove and terminating at the aluminum arsenide etching blocking layer to form the second groove includes: and sequentially etching the indium gallium arsenide etching barrier layer and the first N-type doped layer in the first groove by using succinic acid and stopping at the aluminum arsenide etching barrier layer to form a second groove.
Optionally, the thicknesses of the aluminum arsenide etching blocking layer and the indium gallium arsenide etching blocking layer are both 1nm to 5 nm.
Optionally, the thickness of the channel layer is 5nm to 15 nm; the thickness of the first isolation layer is 3nm to 8 nm; the thickness of the barrier layer is 12nm to 20 nm; the thickness of the low-energy-gap tunneling layer is 1nm to 5 nm; the thickness of the first N-type doped layer is 10nm to 40 nm; the thickness of the second N + type doping layer is 30nm to 80 nm;
optionally, the first doped layer and the second doped layer are both planar doped layers.
In another aspect of the embodiments of the present invention, a high electron mobility transistor is provided, which includes a substrate, and a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low bandgap tunneling layer, an aluminum arsenide etching blocking layer, a first N-type doping layer, an indium gallium arsenide etching blocking layer, and a second N + -type doping layer sequentially disposed on the substrate; a grid groove is formed on the surface of the first N-type doping layer, the grid groove sequentially penetrates through the second N + type doping layer, the indium gallium arsenide etching barrier layer, the first N-type doping layer and the aluminum arsenide etching barrier layer to expose the low-energy-gap tunneling layer, a source electrode and a drain electrode which are in contact with the second N + type doping layer are arranged on two sides of the grid groove, and a grid electrode which is in contact with the low-energy-gap tunneling layer is arranged in the grid groove.
The beneficial effects of the invention include:
the invention provides a high electron mobility transistor and a preparation method thereof, which comprises the steps of sequentially forming a channel layer, a first isolating layer, a first doping layer, a barrier layer, a low-energy gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N + type doping layer on a substrate. And depositing metal on the second N + type doped layer to form a source electrode and a drain electrode respectively. And forming a first groove on the second N + type doping layer. And forming a second groove on the indium gallium arsenide etching barrier layer and the first N-type doped layer. And forming a third groove on the aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are communicated to be used as a grid groove. And depositing metal in the grid groove to form a grid electrode in contact with the low-energy gap tunneling layer. Thereby forming a schottky contact with the barrier layer below the low bandgap tunneling layer. Since the low-bandgap tunneling layer is interposed between the gate and the barrier layer, the on-resistance between the source and the drain can be reduced. On the basis, the level between the first N-type doping layer and the second N + type doping layer is set to be the indium gallium arsenide etching barrier layer, so that the indium gallium arsenide etching barrier layer can play a role in blocking when the second N + type doping layer is etched, and meanwhile, after a device structure is formed, the indium gallium arsenide etching barrier layer is made of a low-energy gap material, so that the ohmic contact resistance of a source electrode and a drain electrode can be effectively reduced, the on-resistance of the device is further reduced, and the performance of the device is convenient to improve.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a diagram illustrating a state of a high electron mobility transistor according to an embodiment of the present invention;
fig. 3 is a second schematic diagram illustrating a state of a high electron mobility transistor according to an embodiment of the present invention;
fig. 4 is a third state diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 5 is a fourth state diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 6 is a fifth state diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 7 is a sixth state diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.
Icon: 100-a substrate; 210-a buffer layer; 220-a second doped layer; 230-a second isolation layer; 240-channel layer; 250-a first isolation layer; 260-a first doped layer; 270-barrier layer; 280-low-bandgap tunneling layer; 290-an aluminum arsenide etching barrier layer; 310-a first N-type doped layer; 320-indium gallium arsenide etching barrier layer; 330-a second N + type doped layer; 340-source; 350-a drain electrode; 360-grid electrode groove; 361-a first groove; 362-a second groove; 370-a gate; 410-a first patterned photoresist layer; 420-a second patterned photoresist layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, in the case of no conflict, various features in the embodiments of the present invention may be combined with each other, and the combined embodiments are still within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "first", "second", "third", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to have better device performance, the existing high electron mobility transistor generally adopts two etching barrier layers to realize a double-groove structure, but because the two etching barrier layers are high-energy band gap layers, the formed ohmic contact resistance is also larger, and the device performance is influenced. Therefore, in an aspect of the embodiments of the present application, a method for manufacturing a High Electron Mobility Transistor (HEMT) is provided to reduce an on-resistance of a device and improve performance of the device. As shown in fig. 1, the steps of the preparation method are schematically shown, including:
s010: a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy gap tunneling layer, an aluminum arsenide etching blocking layer, a first N-type doping layer, an indium gallium arsenide etching blocking layer and a second N + type doping layer are sequentially formed on a substrate.
As shown in fig. 2, a substrate 100 is provided, and the substrate 100 may be a base material for carrying semiconductor integrated circuit devices, such as gallium arsenide, silicon carbide, and the like. In order to form an epitaxial layer of a pseudo-modulation doped heterojunction field effect transistor (pHEMT), a channel layer 240, a first isolation layer 250, a first doped layer 260, a barrier layer 270, a low-energy gap tunneling layer 280, an aluminum arsenide etching blocking layer 290, a first N-type doped layer 310, an indium gallium arsenide etching blocking layer 320, and a second N + -type doped layer 330 may be sequentially formed on the substrate 100. The formation formula of each layer in the epitaxial layer can be carried out by processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), and the processes are not limited in the application and can be reasonably selected according to actual requirements.
S020: and depositing metal on the second N + type doped layer to form a source electrode and a drain electrode respectively.
In forming the epitaxial layer of the pHEMT device in S010, as shown in fig. 2, metal may be sequentially deposited on the uppermost layer of the epitaxial layer, i.e., the second N + -doped layer 330, to form the source electrode 340 and the drain electrode 350, respectively, so that ohmic contacts of the device are formed by the contact of the source electrode 340 with the second N + -doped layer 330 and the contact of the drain electrode 350 with the second N + -doped layer 330, and the source electrode 340 and the drain electrode 350 may be spaced apart from each other in order to ensure the performance of the device.
S030: and etching the second N + type doped layer in the region between the source electrode and the drain electrode and stopping at the indium gallium arsenide etching barrier layer to form a first groove.
As shown in fig. 3, the etching may be performed by coating a photoresist layer on the second N + -type doped layer 330 and the upper surfaces of the source 340 and the drain 350, exposing, developing, and hard-baking to form a patterned photoresist layer having a window region, where the window region is located in a region between the source 340 and the drain 350, and removing the second N + -type doped layer 330 exposed in the window region by using an etching solution or a physical etching method until the window region is terminated at the ingaas etching stop layer 320, where a relatively high etching solution may be selected for etching according to the second N + -type doped layer 330 and the ingaas etching stop layer 320, so as to control an etching depth of the second N + -type doped layer 330, thereby forming a first groove 361 structure on the second N + -type doped layer 330. After the first grooves 361 are formed, the patterned photoresist layer may be stripped and removed, resulting in the structure shown in fig. 3.
S040: and sequentially etching the indium gallium arsenide etching barrier layer and the first N-type doped layer in the first groove and stopping at the aluminum arsenide etching barrier layer to form a second groove.
As shown in fig. 4, a photoresist layer is continuously coated on the structure formed in S030, and then a first patterned photoresist layer 410 is formed through processes of exposure, development and the like, and a window region of the first patterned photoresist is located in the first groove 361, so that the indium gallium arsenide etching blocking layer 320 is exposed in the window region. The indium gallium arsenide etching stopper layer 320 exposed in the window region in the first groove 361 is removed by means of an etching solution or the like, the underlying first N-type doped layer 310 is then exposed and then etching of the exposed first N-type doped layer 310 continues until the aluminum arsenide etch stop layer 290 is terminated, as shown in figure 6, a second recess 362 is formed on the ingaas etch stop layer 320 and the first N-doped layer 310, wherein, when the InGaAs etching stopper layer 320 and the first N-type doping layer 310 are sequentially etched, can be etched by the same etching solution or by two etching solutions, however, when etching the first N-type doped layer 310, the first N-type doped layer 310 should be etched by selecting an etching solution having a relatively high etching selectivity according to the first N-type doped layer 310 and the aluminum arsenide etch stop layer 290, so that the etch depth of the first N-type doped layer 310 can be controlled by the aluminum arsenide etch stop layer 290.
S050: and etching the aluminum arsenide etching barrier layer in the second groove and stopping at the low-energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to be used as a grid groove.
After the structure shown in fig. 6 is formed in S040, the aluminum arsenide barrier layer is continuously removed in the second groove 362 by etching until the low-energy-gap tunneling layer 280 under the aluminum arsenide barrier layer is exposed, so as to form the structure shown in fig. 7, where the etching manner may refer to the manner of forming the first groove 361 and the second groove 362 by etching, and details are not repeated here. In this way, a third recess can be formed in the aluminum arsenide barrier layer, and since the second recess 362 is formed in the first recess 361 and the third recess is formed in the second recess 362, the three are sequentially connected in the order of formation, and the whole connected recess can be used as the gate recess 360. Thus, by sequentially etching the second N + type doping layer 330, the indium gallium arsenide etching blocking layer 320, the first N type doping layer 310 and the aluminum arsenide etching blocking layer 290, a double-groove device structure can be formed, so that breakdown voltage is improved, and the device has better performance. It should be noted that, when etching the first N-type doped layer 310 and the aluminum arsenide etching blocking layer 290, two etching steps should be performed, so that the aluminum arsenide etching blocking layer 290 can play a blocking role when etching the first N-type doped layer 310, and similarly, when etching the second N + -type doped layer 330 and the indium gallium arsenide etching blocking layer 320, two etching steps should be performed.
S060: and depositing metal in the grid groove to form a grid electrode in contact with the low-energy gap tunneling layer.
After forming gate recess 360 in S050, a metal may be deposited within gate recess 360 to form gate 370 of the pHEMT device, and gate 370 may make contact with low-gap tunneling layer 280 to form a schottky contact with barrier layer 270 under low-gap tunneling layer 280. Since the low-bandgap tunneling layer 280 is interposed between the gate 370 and the barrier layer 270, the on-resistance between the source electrode 340 and the drain electrode 350 may be reduced. On this basis, the level between the first N-type doped layer 310 and the second N + -type doped layer 330 is set as the indium gallium arsenide etching blocking layer 320, so that the indium gallium arsenide etching blocking layer 320 can not only play a blocking role when the second N + -type doped layer 330 is etched, but also can effectively reduce the ohmic contact resistance of the source electrode 340 and the drain electrode 350 because the indium gallium arsenide etching blocking layer 320 is a low-energy gap material after the device structure is formed, thereby further reducing the on-resistance of the device and facilitating the improvement of the device performance.
In the embodiment of the present application, the low-gap tunneling layer 280 may be a gallium arsenide layer or an indium gallium arsenide layer, so that the resistance of the ohmic contact formed between the source electrode 340 and the drain electrode 350 is reduced. The aluminum arsenide etch stop 290 is a high-bandgap material that can effectively increase the breakdown voltage of the device. The first N-doped layer 310 may be an N-doped layer.
As shown in fig. 5, in order to form the T-shaped gate 370 in the gate groove 360, the second patterned photoresist layer 420 may be further formed on the first patterned photoresist layer 410, and thus, the second patterned photoresist layer 420 may be trimmed to form a concave shape, so that the T-shaped region in fig. 5 is formed, and after the gate groove 360 shown in fig. 7 is formed, the second patterned photoresist layer 420 and the first patterned photoresist layer are stripped through gate metal evaporation, so that the T-shaped gate 370 is formed, thereby further improving the performance of the device.
Optionally, as shown in fig. 2, in order to improve the performance of the pHEMT device, a buffer layer 210 may be further formed between the substrate 100 and the channel layer 240, so that the subsequent second doped layer 220 or second isolation layer 230 can be better formed on the substrate 100.
Optionally, a second doping layer 220 and a second isolation layer 230 located on the buffer layer 210 are sequentially formed between the buffer layer 210 and the channel layer 240, the channel layer 240 and the first doping layer 260 may be isolated by the first isolation layer 250, and similarly, the second doping layer 220 and the channel layer 240 may be isolated by the second isolation layer 230, so as to ensure performance of the device. The first 250 and second 230 isolation layers are undoped levels.
Optionally, since citric acid may etch the second N + -type doped layer 330 and the ingaas etch stop layer 320 has good etch stop property for citric acid, when the second N + -type doped layer 330 is etched in the region between the source 340 and the drain 350 and stopped at the ingaas etch stop layer 320 to form the first groove 361: first recess 361 may be formed on second N + -doped layer 330 by etching second N + -doped layer 330 with citric acid and terminating at ingaas etch stop layer 320.
Optionally, similarly, since the succinic acid may etch the ingaas etching blocking layer 320, and also etch the first N-type doping layer 310, and the aluminum arsenide layer may have a good etching termination property for the succinic acid, when the ingaas etching blocking layer 320 and the first N-type doping layer 310 are sequentially etched in the first groove 361 and terminated at the aluminum arsenide etching blocking layer 290 to form the second groove 362, the ingaas etching blocking layer 320 and the first N-type doping layer 310 are sequentially etched by the succinic acid and terminated at the aluminum arsenide etching blocking layer 290 to form the second groove 362. Therefore, the indium gallium arsenide etching blocking layer 320 and the first N-type doping layer 310 can be etched in one step through the succinic acid, and etching steps are saved.
By using citric acid and succinic acid at different stages, the gate recess 360 can be effectively formed when the etching stop layer between the first N-type doped layer 310 and the second N + -type doped layer 330 is the indium gallium arsenide etching stop layer 320.
Optionally, the thickness of the aluminum arsenide etching blocking layer 290 is set to be 1nm to 5nm, for example, 2, 3, 4nm, and the like, and the thickness of the indium gallium arsenide etching blocking layer 320 is set to be 1nm to 5nm, for example, 2, 3, 4nm, and the like, so that the performance of the device can be effectively improved.
Alternatively, the thickness of the channel layer 240 of the pHEMT device may also be set to 5nm to 15nm, such as 8, 11, 13nm, etc.; the thickness of the first isolation layer 250 is 3nm to 8nm, such as 5nm, 7nm, etc.; the barrier layer 270 has a thickness of 12nm to 20nm, for example, 15, 18nm, etc.; the thickness of low-bandgap tunneling layer 280 is 1nm to 5nm, e.g., 2, 3, 4nm, etc.; the thickness of the first N-type doped layer 310 is 10nm to 40 nm; the thickness of the second N + -doped layer 330 is 30nm to 80nm, so that the performance of the device can be effectively improved, and the pHEMT device can have a lower on-resistance.
Optionally, the first doped layer 260 and the second doped layer 220 are both planar doped layers, which can effectively weaken the trap effect, and at the same time, facilitate the control of pinch-off voltage, improve the breakdown voltage of the gate 370, and increase the carrier concentration in the channel layer 240.
In another aspect of the present invention, a high electron mobility transistor is provided, as shown in fig. 8, including a substrate 100, and a channel layer 240, a first isolation layer 250, a first doped layer 260, a barrier layer 270, a low-bandgap tunneling layer 280, an aluminum arsenide etching blocking layer 290, a first N-type doped layer 310, an indium gallium arsenide etching blocking layer 320, and a second N + -type doped layer 330 sequentially disposed on the substrate 100; a gate recess 360 is formed on the surface of the first N type doped layer 310, the gate recess 360 sequentially penetrates through the second N + type doped layer 330, the ingaas etching stopper 320, the first N type doped layer 310 and the al arsenide etching stopper 290 to expose the low bandgap tunneling layer 280, a source 340 and a drain 350 are disposed on both sides of the gate recess 360 to contact the second N + type doped layer 330, and a gate 370 is disposed in the gate recess 360 to contact the low bandgap tunneling layer 280. Since the low-bandgap tunneling layer 280 is interposed between the gate 370 and the barrier layer 270, the on-resistance between the source electrode 340 and the drain electrode 350 may be reduced. On this basis, the level between the first N-type doped layer 310 and the second N + -type doped layer 330 is set as the indium gallium arsenide etching blocking layer 320, so that the indium gallium arsenide etching blocking layer 320 can not only play a blocking role when the second N + -type doped layer 330 is etched, but also can effectively reduce the ohmic contact resistance of the source electrode 340 and the drain electrode 350 because the indium gallium arsenide etching blocking layer 320 is a low-energy gap material after the device structure is formed, thereby further reducing the on-resistance of the device and facilitating the improvement of the device performance.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for preparing a high electron mobility transistor, the method comprising:
forming a channel layer, a first isolating layer, a first doping layer, a barrier layer, a low-energy gap tunneling layer, an aluminum arsenide etching blocking layer, a first N-type doping layer, an indium gallium arsenide etching blocking layer and a second N + type doping layer on a substrate in sequence;
depositing metal on the second N + type doping layer to form a source electrode and a drain electrode respectively;
etching the second N + type doping layer in the region between the source electrode and the drain electrode and stopping at the indium gallium arsenide etching barrier layer to form a first groove;
sequentially etching the indium gallium arsenide etching blocking layer and the first N-type doping layer in the first groove and stopping at the aluminum arsenide etching blocking layer to form a second groove;
etching the aluminum arsenide etching barrier layer in the second groove and stopping at the low-energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to be used as a grid groove;
and depositing metal in the gate groove to form a gate in contact with the low-energy-gap tunneling layer.
2. The method of manufacturing a high electron mobility transistor according to claim 1, wherein a buffer layer is further formed between the substrate and the channel layer.
3. The method of manufacturing a high electron mobility transistor according to claim 2, wherein a second doping layer and a second isolation layer on the buffer layer are sequentially formed between the buffer layer and the channel layer.
4. The method of fabricating a high electron mobility transistor according to any of claims 1 to 3, wherein the low bandgap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.
5. The method of fabricating the hemt of any one of claims 1 to 3, wherein said etching said second N + doped layer in the region between said source and said drain and terminating at said ingaas etch stop layer to form a first recess comprises:
and etching the second N + type doping layer in the region between the source electrode and the drain electrode through citric acid and stopping at the indium gallium arsenide etching barrier layer to form a first groove.
6. The method of fabricating the hemt of any one of claims 1 to 3, wherein said sequentially etching said ingan etch stop layer and said first N-type doped layer in said first recess and terminating at said al-arsenide etch stop layer to form a second recess comprises:
and sequentially etching the indium gallium arsenide etching blocking layer and the first N-type doped layer in the first groove by using succinic acid and stopping at the aluminum arsenide etching blocking layer to form a second groove.
7. The method of manufacturing a high electron mobility transistor according to any one of claims 1 to 3, wherein the thickness of each of the aluminum arsenide etching stopper layer and the indium gallium arsenide etching stopper layer is 1nm to 5 nm.
8. The method for manufacturing a high electron mobility transistor according to claim 7, wherein the channel layer has a thickness of 5nm to 15 nm; the thickness of the first isolation layer is 3nm to 8 nm; the barrier layer has a thickness of 12nm to 20 nm; the thickness of the low-energy-gap tunneling layer is 1nm to 5 nm; the thickness of the first N-type doped layer is 10nm to 40 nm; the thickness of the second N + type doping layer is 30nm to 80 nm.
9. The method according to claim 3, wherein the first doped layer and the second doped layer are planar doped layers.
10. A high electron mobility transistor is characterized by comprising a substrate, and a channel layer, a first isolating layer, a first doping layer, a barrier layer, a low-energy gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N + type doping layer which are sequentially arranged on the substrate; a gate groove is formed on the surface of the first N-type doped layer, the gate groove sequentially penetrates through the second N + -type doped layer, the indium gallium arsenide etching blocking layer, the first N-type doped layer and the aluminum arsenide etching blocking layer to expose the low-energy-gap tunneling layer, a source electrode and a drain electrode which are in contact with the second N + -type doped layer are arranged on two sides of the gate groove, and a gate electrode which is in contact with the low-energy-gap tunneling layer is arranged in the gate groove.
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