CN112310208A

CN112310208A - Enhanced gallium nitride-based transistor, preparation method thereof and electronic device

Info

Publication number: CN112310208A
Application number: CN201910689945.1A
Authority: CN
Inventors: 曲爽; 庄建治; 王晓亮; 李巍
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2021-02-02

Abstract

The embodiment of the application provides an enhanced gallium nitride-based transistor, a preparation method thereof and an electronic device. The enhancement type gallium nitride-based transistor comprises a substrate, a functional layer and a transistor layer which are arranged in a stacked mode. The transistor layer comprises a doping cap layer, a grid electrode, a source electrode and a drain electrode. The doping cap layer, the source electrode and the drain electrode are in contact with the surface of the functional layer and are isolated from each other, and the doping cap layer is located between the source electrode and the drain electrode. The grid electrode is arranged on the surface of the doping cap layer far away from the functional layer. The doping cap layer is provided with at least one doping area, and the upper surface of the doping area is at least one part of the surface of the doping cap layer facing the grid electrode. The upper surface of the doped region is in contact with the lower surface of the gate. The lower surface of the grid electrode is the surface of the grid electrode facing the doping cap layer. The embodiment of the application provides an enhanced gallium nitride-based transistor, a preparation method thereof and an electronic device, which can reduce the grid leakage of a device and improve the grid voltage swing.

Description

Enhanced gallium nitride-based transistor, preparation method thereof and electronic device

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to an enhanced gallium nitride-based transistor, a preparation method thereof and an electronic device.

Background

Gallium Nitride (GaN) -based materials are used as semiconductor materials, have the characteristics of large forbidden bandwidth, high critical breakdown electric field, high electron saturation and drift velocity, stable chemical properties and the like, and are widely applied to the fields of microelectronics and photoelectrons. High Electron Mobility Transistor (HEMT) based on gallium nitride-based materials has the characteristics of High breakdown voltage, low on-resistance, High operating frequency, small device size and the like, and has become a common material of High-power switching devices. The power switch device is generally an Enhancement-Mode (E-Mode) device, which avoids the negative gate voltage power supply required for turning off the depletion Mode device, thereby realizing safer switching operation.

At present, the method for manufacturing the enhancement device mainly comprises etching a concave gate structure, F ion implantation treatment under a gate or forming a P-type cap layer under the gate. And forming a P-type cap layer under the gate comprises forming a P-type InGaN cap layer under the gate or forming a P-type AlGaN cap layer under the gate. The P-type cap layer formed under the gate has the advantage of high threshold voltage, wherein the enhancement type characteristic of the high threshold voltage is more stable and easier to control, so that the P-type cap layer is widely applied to the manufacture of enhancement type devices.

However, when the P-type cap layer enhanced device is turned on, the schottky junction is in a reverse bias state under forward gate voltage bias, gate leakage current is generated, and the gate voltage swing of the device is reduced.

Disclosure of Invention

The embodiment of the application provides an enhanced gallium nitride-based transistor, which can reduce the grid leakage of a device and improve the grid voltage swing. In addition, the application also provides an electronic device using the enhanced gallium nitride-based transistor and a preparation method of the enhanced gallium nitride-based transistor.

In a first aspect, an embodiment of the present application provides an enhanced gallium nitride-based transistor, which includes a substrate, a functional layer, and a transistor layer, which are stacked. The substrate is located on one side of the functional layer, and the transistor layer is located on one side of the functional layer, which faces away from the substrate. The transistor layer comprises a doping cap layer, a grid electrode, a source electrode and a drain electrode, wherein the doping cap layer, the source electrode and the drain electrode are in contact with the surface of the functional layer and are isolated from each other, and the doping cap layer is located between the source electrode and the drain electrode. The grid electrode is arranged on the surface of the doping cap layer far away from the functional layer.

The doped cap layer is provided with at least one doped region, the upper surface of the doped region is at least one part of the surface of the doped cap layer facing the grid electrode, the upper surface of the doped region is in contact with the lower surface of the grid electrode, and the lower surface of the grid electrode is the surface of the grid electrode facing the doped cap layer. Because the lower surface of the grid electrode is contacted with the upper surface of the doped region, when voltage is applied to the grid electrode, the doped region contacted with the grid electrode generates carrier diffusion to the doped cap layer under the action of an electric field, a depletion region is formed in the doped cap layer until the doped region is combined with the doped cap layer, and the combined doped cap layer and the doped region clamp off a current channel on the surface of the grid electrode, so that the electric leakage of the grid electrode is reduced, the grid voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor is improved.

In one possible implementation manner of the first aspect, the doped region is an N-type high-concentration doped region, and the doped cap layer is a P-type cap layer. When voltage is applied to the grid electrode, the N-type high-concentration doping area and the P-type cap layer form a PN junction, and when the enhanced gallium nitride-based transistor is conducted in the forward direction, the N-type high-concentration doping area and the P-type cap layer form the PN junction and can clamp off a current channel on the surface of the grid electrode, so that the electric leakage of the grid electrode is reduced, the grid voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor is improved.

In a possible implementation of the first aspect, an upper surface of the doped region is in contact with a portion of a lower surface of the gate, or an edge of the upper surface of the doped region coincides with an edge of the lower surface of the gate.

The upper surface of the doped region formed in the doped cap layer can be diffused into the doped cap layer as long as the upper surface of the doped region is in contact with a part of the lower surface of the gate, or at least a part of the edge of the upper surface of the doped region is overlapped with at least a part of the edge of the lower surface of the gate. Therefore, the shape and the position of the formed doped region do not need to be accurately controlled when the doped region is formed by injection doping or diffusion doping, and the time for forming the doped region is saved.

In one possible embodiment of the first aspect, the number of the doped regions is at least two, and the at least two doped regions are spaced apart. Thus, by increasing the number of the doped regions, it is ensured that the upper surface of the doped region has a portion which is in contact with the lower surface of the gate electrode.

In one possible implementation manner of the first aspect, the doping depth of the doped region is less than or equal to the thickness of the doping cap layer, and the doping width of the doped region is less than or equal to half of the width of the gate. Therefore, the doping depth of the doping region is controlled to be smaller than or equal to the thickness of the doping cap layer, the doping region is prevented from extending into the functional layer in contact with the doping cap layer, the doping width of the doping region is controlled to be smaller than or equal to half of the width of the grid electrode, and the best pressure-resistant effect is obtained while the upper surface of the doping region is ensured to be in contact with at least part of the lower surface of the grid electrode.

In one possible embodiment of the first aspect, the doped cap layer has a thickness greater than or equal to 1nm and less than or equal to 500 nm. The thickness of the doped cap layer is selected according to the specific performance of the enhanced gallium nitride-based transistor.

In one possible implementation of the first aspect, the doped cap layer is in ohmic contact or schottky contact with the gate. When the doped cap layer is in Schottky contact with the gate, the height of an electron transition barrier formed by the contact surface of the doped cap layer and the gate is higher, and the thickness is thicker.

In one possible implementation of the first aspect, the doped cap layer is doped with acceptor impurities. The acceptor impurity makes the doped cap layer easily attract one free electron from the outside to enter the doped cap layer, so that the doped cap layer is in a saturated state.

In one possible embodiment of the first aspect, the acceptor impurity is one of magnesium, calcium, zinc, beryllium, iron, or carbon, and doping of the acceptor impurityConcentration of 1X 10 or more¹⁶cm^-3And is less than or equal to 1 × 10²¹cm^-3。

In one possible embodiment of the first aspect, the doped region has donor impurities therein. The donor impurity causes the contents of the doped region to volatilize an electron into a free electron, which allows the free electron to enter the doped cap layer.

In one possible embodiment of the first aspect, the donor impurity is silicon or oxygen, and the doping concentration of the donor impurity is greater than or equal to 1 × 10¹⁵cm^-3And is less than or equal to 1 × 10²⁰cm^-3. By selectively doping the donor impurity in the doped region, the doped region can improve the fringe electric field of the gate, reducing the reliability risk of the edge breakdown of the gate.

In one possible embodiment of the first aspect, the functional layer includes a nucleation layer, a high resistance layer, a high mobility layer, and a barrier layer sequentially stacked,

the nucleation layer is positioned between the substrate and the high-resistance layer, and the barrier layer is positioned between the doped cap layer and the high-mobility layer. The substrate serves to support the functional layer overlying the substrate. The high resistance layer performs a buffer function for a high mobility layer grown or formed on the high resistance layer. The barrier layer is used for matching with the high mobility layer and generating two-dimensional electron gas in a connection area of the high mobility layer and the barrier layer through polarization, so that current is conducted. The source and drain electrodes are used to make the two-dimensional electron gas flow in the high mobility layer under the effect of the electric field. The grid is used for allowing or blocking the two-dimensional electron gas to pass through.

In one possible implementation of the first aspect, the barrier layer is one or more of aluminum gallium nitride, indium gallium nitride, or aluminum indium nitride.

In one possible implementation manner of the first aspect, the barrier layer has a multi-layer structure, and the material of two adjacent barrier layers is different.

In a second aspect, an electronic device is provided in an embodiment of the present application, and includes the above-mentioned enhanced gallium nitride-based transistor and a controller, where the controller is connected to the enhanced gallium nitride-based transistor.

The electronic device is provided with the enhanced gallium nitride-based transistor, the lower surface of the grid electrode in the enhanced gallium nitride-based transistor is in contact with the upper surface of the doped region, when voltage is applied to the grid electrode, the doped region in contact with the grid electrode generates carrier diffusion to the doped cap layer under the action of an electric field, a depletion region is formed in the doped cap layer until the doped region is combined with the doped cap layer, and the combined doped cap layer and the doped region clamp off a current channel on the surface of the grid electrode, so that grid electrode electric leakage is reduced, grid voltage swing is improved, and reliability of the enhanced gallium nitride-based transistor is improved.

In a third aspect, an embodiment of the present application provides a method for manufacturing an enhanced gallium nitride-based transistor, including:

forming a functional layer on a substrate;

forming a source electrode, a doping cap layer and a drain electrode on the surface of the functional layer, which is far away from the substrate, wherein the doping cap layer is positioned between the source electrode and the drain electrode, and the source electrode, the drain electrode and the doping cap layer are spaced;

forming at least one doped region within the doped cap layer;

and forming a grid electrode on the surface of the doping cap layer, which is far away from the functional layer, wherein the upper surface of the doping region is at least one part of the surface of the doping cap layer, which faces the grid electrode, the upper surface of the doping region is in contact with the lower surface of the grid electrode, and the lower surface of the grid electrode is the surface of the grid electrode, which faces the doping cap layer.

According to the enhanced gallium nitride-based transistor prepared by the method, the lower surface of the grid electrode in the enhanced gallium nitride-based transistor is contacted with the upper surface of the doped region, when voltage is applied to the grid electrode, the doped region contacted with the grid electrode is diffused to the doped cap layer under the action of an electric field, a depletion region is formed in the doped cap layer until the doped region is combined with the doped cap layer, and the combined doped cap layer and the doped region clamp off a current channel on the surface of the grid electrode, so that the electric leakage of the grid electrode is reduced, the amplitude of grid voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor is improved.

In one possible implementation of the third aspect, the forming of the doped cap layer on the surface of the functional layer facing away from the substrate comprises:

and forming a P-type cap layer on the surface of the functional layer, which is far away from the substrate.

In one possible implementation manner of the third aspect, after forming the P-type cap layer on the surface of the functional layer facing away from the substrate, the method further includes:

and doping acceptor impurities in the P-type cap layer.

In one possible embodiment of the third aspect, the doped cap layer is formed at a temperature greater than or equal to 900 ℃ and less than or equal to 1100 ℃, and has a thickness greater than or equal to 60nm and less than or equal to 80 nm.

In one possible implementation of the third aspect, forming at least one doped region within the doped cap layer includes:

forming at least one preset area on the surface of the doped cap layer, which is far away from the functional layer, and doping donor impurities on the surface of the P-type cap layer exposed in the preset area to form an N-type high-concentration doped area;

the doping depth of the N-type high-concentration doping region is smaller than or equal to the thickness of the doping cap layer, and the doping width of the N-type high-concentration doping region is smaller than or equal to half of the width of the grid electrode.

In one possible implementation of the third aspect, forming the functional layer on the substrate includes;

sequentially stacking a nucleating layer, a high-resistance layer, a high-mobility layer and a barrier layer on a substrate;

the nucleation layer is positioned between the substrate and the high-resistance layer, and the barrier layer is positioned between the doping cap layer and the high mobility layer.

The substrate serves to support the functional layer overlying the substrate. The high resistance layer performs a buffer function for a high mobility layer grown or formed on the high resistance layer. The barrier layer is used for matching with the high mobility layer and generating two-dimensional electron gas in a connection area of the high mobility layer and the barrier layer through polarization, so that current is conducted. The source and drain electrodes are used to make the two-dimensional electron gas flow in the high mobility layer under the effect of the electric field. The grid is used for allowing or blocking the two-dimensional electron gas to pass through.

The enhanced gallium nitride-based transistor comprises a substrate, a functional layer and a transistor layer, wherein the transistor layer comprises a doped cap layer, a grid electrode, a source electrode and a drain electrode, at least one doped region is arranged in the doped cap layer, the lower surface of the grid electrode is in contact with the upper surface of the doped region, when voltage is applied to the grid electrode, the doped region in contact with the grid electrode generates carrier diffusion to the doped cap layer under the action of an electric field, a depletion region is formed in the doped cap layer until the doped region is combined with the doped cap layer, and the combined doped cap layer and the doped region clamp off a current channel on the surface of the grid electrode, so that grid electrode leakage is reduced, grid voltage swing is improved, and reliability of the enhanced gallium nitride-based transistor is improved.

Drawings

Fig. 1 is a schematic structural diagram of an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 2 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 3 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 4 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 5 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 6 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 7 is a schematic position diagram of a doped region and a doped cap layer in an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a doped region in an enhanced gan-based transistor according to an embodiment of the present disclosure;

FIG. 9 is a schematic view of the structure of FIG. 8 in another orientation;

fig. 10 is a schematic structural diagram of a doped region in an enhanced gan-based transistor according to an embodiment of the present disclosure;

FIG. 11 is a schematic view of the structure of FIG. 10 in another orientation;

fig. 12 is a schematic structural diagram of a doped region in an enhancement mode gan-based transistor according to an embodiment of the present disclosure;

FIG. 13 is a schematic view of the structure of FIG. 12 in another orientation;

fig. 14 is a schematic structural diagram of a doped region in an enhancement mode gan-based transistor according to an embodiment of the present disclosure;

FIG. 15 is a schematic view of the structure of FIG. 14 in another orientation;

fig. 16 is a schematic structural diagram of a doped region in an enhancement mode gan-based transistor according to an embodiment of the present disclosure;

FIG. 17 is a schematic view of the structure of FIG. 16 in another orientation;

fig. 18 is a schematic structural diagram of a doped region in an enhancement mode gan-based transistor according to an embodiment of the present disclosure;

FIG. 19 is a schematic view of the structure of FIG. 18 in another orientation;

fig. 20 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 21 is a circuit diagram of an electronic device according to an embodiment of the present application;

fig. 22 is a flowchart illustrating a method for fabricating an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 23 is a flowchart illustrating a method for fabricating an enhanced gan-based transistor according to an embodiment of the present disclosure;

fig. 24a to 24j are schematic structural diagrams of respective manufacturing extremes in a manufacturing method of an enhancement mode gan-based transistor according to an embodiment of the present disclosure;

FIG. 25 is a graph comparing the gate characteristics of an enhanced GaN-based transistor fabricated according to the present application with those of a conventional enhanced GaN-based transistor;

FIG. 26 is a graph comparing the output characteristics of an enhanced GaN-based transistor fabricated according to the present invention with those of a conventional enhanced GaN-based transistor;

fig. 27 is a graph comparing transfer characteristics of an enhancement type gallium nitride based transistor manufactured by the present application and a conventional enhancement type gallium nitride based transistor.

Description of the reference numerals

100-enhancement mode gallium nitride based transistors; 10-a substrate; 20-a functional layer; 21-a nucleation layer; 22-high resistance layer; 23-a high mobility layer; 24-barrier layer; 30-a transistor layer; 31-doped cap layer; 311-doped region; 312-mask; 32-a gate; 33-source; 34-a drain electrode; 401 — a first passivation layer; 402-a second passivation layer; 200-an electronic device; 300-controller.

Detailed Description

In order to make the technical solution and the clarity of the embodiments of the present application clearer, the following explains terms referred to in the embodiments of the present application.

High Electron Mobility Transistors (HEMTs), also known as Heterojunction Field Effect Transistors (HFETs), are used. High electron mobility transistors are field effect transistors that utilize two-dimensional electron gas high mobility characteristics in a heterojunction or modulated doped structure. The electron mobility of the high electron mobility transistor at low temperature or low electric field is 1000 times higher than that of a general high-quality bulk semiconductor field effect transistor under the same condition, and the high electron mobility transistor can realize high-speed low-noise operation.

Gallium Nitride (GaN), a Gallium Nitride material, has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high electron saturation, high drift velocity, low heat generation rate and high breakdown electric field, and is an important material for developing high-temperature high-power electronic devices and high-frequency microwave devices.

Forbidden band: and an energy interval in which the energy state density between the valence band and the conduction band of the semiconductor is zero.

Grid voltage swing: the difference between the driving voltage and the highest operating voltage that satisfies reliability.

Two-dimensional electron gas is a system which uses physical methods such as quantum confinement to limit the movement of electron group in one direction to a small range, and can move freely in the other two directions, and is called two-dimensional electron system. If the electron density in the system is low, it is called two-dimensional electron gas. If the movement of electrons in a three-dimensional solid is blocked (restricted) in one direction (e.g., z direction), the electrons can move freely only in the other Two directions (x, y directions), and the free electrons with Two degrees of freedom are called Two-dimensional electron gas (2-DEG).

Donor impurities and acceptor impurities in a semiconductor refer to atoms inside the semiconductor other than the atoms of the semiconductor itself. The acceptor means that the number of electrons in the outermost layer of nuclear electron of the impurity atom in the semiconductor is less than 4. For example, if there are less than 4, such as 3, outermost electrons of an impurity atom in the semiconductor, the positron in its core can easily attract one electron from the outside into the outermost electron layer to form a saturated state, and this impurity atom is called an acceptor because of the electron obtained. The donor means that the number of electrons in the outermost layer of the nuclear electron of the impurity atom in the semiconductor is more than 4. For example, if the number of outermost electrons of an impurity atom in the semiconductor is more than 4, for example, 5, the impurity atom is liable to lose one electron to become a free electron, and this impurity atom is called a donor. Because the number of electrons at the outermost layer of the atomic nucleus is most stable when being 4, if the number of electrons at the outermost layer is less than 4, the electrons at the outermost layer can easily attract a free electron to enter the outermost layer to rotate around the nucleus to form a saturated state; on the contrary, if the number of outermost electrons is more than 4, the electrons are more easily lost.

The power switch device generally adopts a normally-off device, namely an Enhancement-Mode (E-Mode) device, and the Enhancement device does not need negative voltage in the application of the circuit, thereby reducing the complexity and the manufacturing cost of the circuit and improving the safety of the functional switch circuit.

At present, the method for manufacturing the enhancement device mainly comprises etching a concave gate structure, F ion implantation treatment under a gate or forming a P-type cap layer under the gate. And forming a P-type cap layer under the gate comprises forming a P-type InGaN cap layer under the gate or forming a P-type AlGaN cap layer under the gate. The P-type cap layer formed under the gate has the advantage of high threshold voltage, wherein the enhancement type characteristic of the high threshold voltage is more stable and is easier to control, so that the P-type cap layer is widely applied to the manufacture of enhancement type devices. Although the threshold voltage of the P-type cap layer under the gate is high, the forward withstand voltage of the gate is insufficient, specifically: when the enhancement type device with the P-type cap layer is conducted, the Schottky junction is in a reverse bias state under forward gate voltage bias, gate leakage current can be generated, the gate voltage swing of the enhancement type device is reduced, the safe operation range and the reliability of the enhancement type device are limited, and the reliability risk exists after long-term work.

In order to solve the above problems, the present application provides an enhancement mode gallium nitride based transistor having a gate electrode in contact with a doped region in a doped cap layer. When the enhanced gallium nitride-based transistor is conducted in the forward direction, the doped cap layer and the doped regions in the doped cap layer clamp off the current channel, so that grid leakage of the enhanced gallium nitride-based transistor is reduced, grid voltage swing is improved, and reliability of the enhanced gallium nitride-based transistor is improved.

The following describes in detail an implementation of the enhanced gallium nitride-based transistor provided in the present application with reference to an embodiment.

Fig. 1 is a schematic structural diagram of an enhanced gallium nitride-based transistor according to an embodiment of the present disclosure. It should be noted that fig. 1 is merely an exemplary illustration, and the enhancement mode gallium nitride based transistor 100 of the present application is not limited to this manner. Referring to fig. 1, an enhancement mode gallium nitride based transistor 100 includes: a substrate 10, a functional layer 20 and a transistor layer 30. As can be easily seen from fig. 1, the upper surface of the substrate 10 contacts the lower surface of the functional layer 20, and the upper surface of the functional layer 20 contacts the lower surface of the transistor layer 30.

The transistor layer 30 includes a source electrode 33, a drain electrode 34, and a dielectric layer between the source electrode 33 and the drain electrode 34. The dielectric layer is isolated from the source electrode 33 by the first passivation layer 1 and the dielectric layer is isolated from the drain electrode 34 by the second passivation layer 2. The first passivation layer 1 is located on one side of the dielectric layer, and the side wall of the first passivation layer 1 facing the dielectric layer is attached to the first side wall of the dielectric layer. The first passivation layer 1 also covers the source electrode 33, or the source electrode 33 is located in a cavity formed between the functional layer 20 and a part of the surface of the first passivation layer 1 facing the functional layer 20. It is readily apparent that the part of the surface of the first passivation layer 1 facing the functional layer 20 is in contact with the surface of the source electrode 33 facing away from the functional layer 20, and the other part of the surface of the first passivation layer 1 facing the functional layer 20 is in contact with the surface of the functional layer 20. It is noted that the first passivation layer 1 further has a sidewall facing the source electrode 33, and the sidewall of the first passivation layer 1 facing the source electrode 33 and the sidewall of the source electrode 33 face each other and contact each other. As can be easily seen in fig. 1, the first passivation layer 1 has an inverted "L" shape. The first passivation layer 1 insulates the source electrode 33 from the dielectric layer.

The first passivation layer 1 may be divided into two adjacent portions, a first portion of the first passivation layer 1 is located between the source electrode 33 and the dielectric layer, a first sidewall of the first portion of the first passivation layer 1 is attached to a first sidewall of the dielectric layer, and a second sidewall of the first portion of the first passivation layer 1 is attached to the first sidewall of the source electrode 33. The second portion of the first passivation layer 1 is stacked on the surface of the source electrode 33 facing away from the dielectric layer 20, and a first sidewall of the second portion of the first passivation layer 1 is attached to a second sidewall of another portion of the first passivation layer 1. Wherein, the first portion of the first passivation layer 1 and the second portion of the first passivation layer 1 may be integrally formed, and the first portion of the first passivation layer 1 and the second portion of the first passivation layer 1 are located on the same plane away from the surface of the dielectric layer 20.

The second passivation layer 2 is located on the other side of the dielectric layer, i.e. the dielectric layer is located between the first passivation layer 1 and the second passivation layer 2. The side wall of the second passivation layer 2 facing the dielectric layer is attached to the second side wall of the dielectric layer. The second passivation layer 2 also covers the drain electrode 34, or the drain electrode 34 is located in a cavity formed between the functional layer 20 and a part of the surface of the second passivation layer 2 facing the functional layer 20. It is readily apparent that the part of the surface of the second passivation layer 2 facing the functional layer 20 is in contact with the surface of the drain electrode 34 facing away from the functional layer 20, and the other part of the surface of the second passivation layer 2 facing the functional layer 20 is in contact with the surface of the functional layer 20. It is noted that the second passivation layer 2 further has a sidewall facing the drain electrode 34, and the sidewall of the second passivation layer 2 facing the drain electrode 34 and the sidewall of the drain electrode 34 face each other and contact each other. As can be readily seen in connection with fig. 1, the second passivation layer 2 has an inverted "L" shape. The second passivation layer 2 insulates the drain electrode 34 from the dielectric layer.

The second passivation layer 2 may be divided into two adjacent portions, a first portion of the second passivation layer 2 is located between the drain electrode 34 and the dielectric layer, a first sidewall of the first portion of the second passivation layer 2 is attached to a second sidewall of the dielectric layer, and a portion of the second sidewall of the first portion of the second passivation layer 2 is attached to the first sidewall of the drain electrode 34. A second portion of the second passivation layer 2 is stacked on the surface of the drain electrode 34 facing away from the dielectric layer 20, and a first sidewall of the second portion of the second passivation layer 2 is attached to a second sidewall of another portion of the first portion of the second passivation layer 2. Wherein the first portion of the second passivation layer 2 and the second portion of the second passivation layer 2 may be integrally formed, and the first portion of the second passivation layer 2 and the second portion of the second passivation layer 2 are located on the same plane away from the surface of the dielectric layer 20.

It is noted that the dielectric layer includes a doping cap layer 31 and a gate electrode 32, and the doping cap layer 31 is located between the gate electrode 32 and the functional layer 20. The upper surface of the doping cap layer 31 is in contact with the lower surface of the gate 32, the doping cap layer 31 has at least one doping region 311, the upper surface of the doping region 311 is at least a part of the upper surface of the doping cap layer 31, and the upper surface of the doping region 311 is in contact with the lower surface of the gate 32. When voltage is applied to the gate 32, because the lower surface of the gate 32 is in contact with the upper surface of the doped region 311, under the action of an electric field, carrier diffusion occurs to the doped cap layer 31 from the doped region 311 in contact with the gate 32, a depletion region is formed in the doped cap layer 31 until the doped region 311 is merged with the doped cap layer 31, and the merged doped cap layer 31 and doped region 311 pinch off a current channel on the surface of the gate 32, so that the leakage of the gate 32 is reduced, the gate voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor 100 is improved.

In an embodiment, the doped region 311 is an N-type high-concentration doped region, and the doped cap layer 31 is a P-type cap layer. The N-type high concentration doped region is also referred to as an N + doped region. The N-type high concentration doped region is located in the P-type cap layer, and the lower surface of the gate 32 is in contact with the upper surface of the doped region 311 while the upper surface of the doped region 311 is in contact with the lower surface of the gate 32. When a voltage is applied to the gate 32, the N-type high-concentration doped region and the P-type cap layer form a PN junction, where electrons in the N-type high-concentration doped region diffuse into a region of the P-type cap layer where the N-type high-concentration doped region is not located, and holes in a region of the P-type cap layer where the N-type high-concentration doped region is not located also diffuse into the N-type high-concentration doped region, which is also referred to as carrier diffusion. At the contact position of the N-type high-concentration doping region and a region without the N-type high-concentration doping region in the P-type cap layer, positive charges are left in the N-type high-concentration doping region, negative charges are left in the P-type cap layer, a self-built electric field is formed by the positive charges and the negative charges, the self-built electric field enables the carriers to drift, the direction of the carrier drift is opposite to the direction of the carrier diffusion, the carrier drift and the carrier diffusion are balanced, and at the moment, the self-built electric field region has no carriers, so that a PN junction is formed. When the enhanced gallium nitride-based transistor 100 is conducted in the forward direction, the N-type high-concentration doping region and the P-type cap layer form a PN junction which can pinch off a current channel on the surface of the gate 32, so that the electric leakage of the gate 32 is reduced, the gate voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor is improved.

Under the action of the electric field, the doped region 311 diffuses towards the doped cap layer 31 regardless of the contact area between the doped region 311 and the gate 32, and can diffuse towards the doped cap layer 31 as long as the doped region 311 contacts with the gate 32. Therefore, in the embodiment, the upper surface of the doped region 311 is in contact with a portion of the lower surface of the gate electrode 32, or the edge of the upper surface of the doped region 311 coincides with the edge of the lower surface of the gate electrode 32. That is, the upper surface of the doped region 311 formed in the doped cap layer 31 may be in contact with a part of the lower surface of the gate electrode 32, or at least a part of the edge of the upper surface of the doped region 311 may overlap with at least a part of the edge of the lower surface of the gate electrode 32, so that the doped region 311 in contact with the gate electrode 32 may diffuse carriers to the doped cap layer 31. Thus, there is no need to perform implantation doping or diffusion doping to form the doped region 311, and the shape and position of the doped region 311 are precisely controlled, thereby saving the time for forming the doped region 311.

The doping cap layer 31 is doped by implantation doping or diffusion doping to form a doped region 311. In order to ensure that the upper surface of the doped cap layer 31 has a contact portion with the lower surface of the gate electrode 32, in this embodiment, the number of the doped regions 311 may be two or more, so that the upper surface of the doped region 311 is ensured to have a contact portion with the lower surface of the gate electrode 32 by increasing the number of the doped regions 311.

When the number of the doped regions 311 is multiple, the doped regions 311 are disposed at intervals, the spacing distance between the doped regions 311 may be equal, and the spacing distance between the doped regions 311 may also be unequal. The upper surface of each doped region 311 contacts with different positions of the lower surface of the gate 32, and the portions of each doped region 311 located in the doped cap layer 31 may be connected to each other.

The position and number of the doped regions 311 in the doped cap layer 31 can have various forms, and the position and number of the doped regions 311 in the doped cap layer 31 will be described in detail below with reference to specific embodiments.

Fig. 2 is a schematic position diagram of a doped region 311 and a doped cap layer 31 in an enhancement-mode gan-based transistor according to an embodiment of the present disclosure. Referring to fig. 2, in one possible embodiment, the number of the doped regions 311 is one, a first sidewall of the doped region 311 is flush with a first sidewall of the doped cap layer 31, and a second sidewall of the doped region 311 is located in the doped cap layer 31.

Fig. 3 is a schematic position diagram of a doped region 311 and a doped cap layer 31 in an enhancement-mode gan-based transistor according to an embodiment of the present disclosure. Referring to fig. 3, in another possible embodiment, the number of the doped regions 311 is one, the second sidewall of the doped region 311 is flush with the second sidewall of the doped cap layer 31, and the first sidewall of the doped region 311 is located in the doped cap layer 31.

Fig. 4 is a schematic position diagram of a doped region 311 and a doped cap layer 31 in an enhancement-mode gan-based transistor according to an embodiment of the present disclosure. Referring to fig. 4, in another possible embodiment, the number of the doped regions 311 is one, a first sidewall of the doped region 311 is flush with a first sidewall of the doped cap layer 31, and a second sidewall of the doped region 311 is flush with the first sidewall of the doped cap layer 31.

Fig. 5 is a fourth schematic view illustrating a position between the doped region 311 and the doped cap layer 31 in the enhanced gan-based transistor according to an embodiment of the present disclosure. Referring to fig. 5, in another possible embodiment, the number of the doped regions 311 is two, the two doped regions 311 are disposed at intervals, the two doped regions 311 are respectively located at two sides of the doping cap layer 31, a first sidewall of the first doped region 311 is flush with a first sidewall of the doping cap layer 31, a second sidewall of the second doped region 311 is flush with a second sidewall of the doping cap layer 31, and both the second sidewall of the first doped region 311 and the first sidewall of the second doped region 311 are located in the doping cap layer 31 and are spaced by the doping cap layer 31.

Fig. 6 is a schematic position diagram five of the enhanced gan-based transistor according to an embodiment of the present disclosure, which is between the doped region 311 and the doped cap layer 31. Referring to fig. 6, in another possible embodiment, the number of the doped regions 311 is two, two doped regions 311 are disposed at intervals, the first sidewall and the second sidewall of each of the two doped regions 311 are located in the doping cap layer 31, and the two doped regions 311 are spaced by the doping cap layer 31.

Fig. 7 is a sixth schematic view illustrating a position between the doped region 311 and the doped cap layer 31 in the enhanced gan-based transistor according to an embodiment of the present disclosure. Referring to fig. 7, in another possible implementation, the number of the doped regions 311 is three, and on the basis of the embodiment in fig. 5, one doped region 311 is added, the added doped region 311 is located between two doped regions 311 provided in the embodiment in fig. 5, and the three doped regions 311 are spaced apart and separated by the doping cap layer 31.

It should be noted that, in the above embodiments of fig. 2 to 7, the first side wall and the second side wall refer to the left side and the right side in the corresponding figures. The shape of the doped region 311 in the embodiments of fig. 2 to 7 is described as a rectangle, but the doped region 311 may have other shapes, and the doped region 311 will be described in detail in the following embodiments.

The position of the doped region 311 in the doped cap layer 31 is not limited to the above embodiment, and the above embodiment is only partially illustrated.

In the above-mentioned embodiment of fig. 2 to 7, by selecting different regions in the doping cap layer 31, ion implantation doping or diffusion doping or other doping methods are performed in the selected regions to form the N-type high-concentration doping region 311 in the embodiment of fig. 2 to 7. In the embodiments of fig. 2 to 5, ion implantation doping or diffusion doping is more facilitated in the region of the doped cap layer 31, as compared to the embodiments of fig. 6 and 7.

In this embodiment, the shape of the doped region 311 may be one or more of a rectangle, a ring, or a circle. In order to facilitate understanding of the shape of the doped region 311 and the positional relationship between the doped region 311 and the doped cap layer 31, the shape of the doped region 311 is described in detail below with reference to the doped cap layer 31 and specific embodiments.

Fig. 8 and fig. 9 are schematic structural diagrams of the doped region 311 in the enhanced gan-based transistor according to an embodiment of the present disclosure. Fig. 8 is a cross-sectional view, and fig. 9 is a plan view. Referring to fig. 8 and 9, in the present embodiment, the number of the doped regions 311 is one, and the shape of the doped regions 311 is rectangular.

Fig. 10 and fig. 11 are schematic structural diagrams of a doped region in an enhancement mode gallium nitride based transistor according to an embodiment of the present disclosure. Fig. 10 is a cross-sectional view, and fig. 11 is a plan view. Referring to fig. 10 and 11, in the present embodiment, the number of the doped regions 311 is one, and the shape of the doped regions 311 is a ring shape.

Fig. 12 and fig. 13 are schematic structural diagrams of a doped region in an enhancement mode gallium nitride based transistor according to an embodiment of the present application. Fig. 12 is a sectional view, and fig. 13 is a plan view. Referring to fig. 12 and 13, in the present embodiment, the number of the doped regions 311 is one, and the shape of the doped regions 311 is a circle.

Fig. 14 and fig. 15 are schematic structural diagrams of a doped region in an enhancement mode gallium nitride-based transistor according to an embodiment of the present application. Fig. 14 is a sectional view, and fig. 15 is a plan view. Referring to fig. 14 and 15, in the present embodiment, the number of the doped regions 311 is two, and the shapes of the doped regions 311 are rectangular and circular, respectively.

Fig. 16 and 17 are schematic structural diagrams of a doped region in an enhancement mode gallium nitride-based transistor according to an embodiment of the present application. Fig. 16 is a sectional view, and fig. 17 is a plan view. Referring to fig. 16 and 17, in the present embodiment, the number of the doped regions 311 is two, and the shapes of the doped regions 311 are ring-shaped and circular, respectively.

Fig. 18 and fig. 19 are schematic structural diagrams of a doped region in an enhancement mode gallium nitride-based transistor according to an embodiment of the present application. Fig. 18 is a sectional view, and fig. 19 is a plan view. Referring to fig. 18 and 19, in the present embodiment, the number of the doped regions 311 is two, and the shapes of the doped regions 311 are a ring shape and a rectangular shape, respectively.

The shape of the doped region 311 is not limited to the above embodiment, and the above embodiment is only partially illustrated.

In the above embodiments, the shape, number, and position of the doped regions 311 are explained. The doping depth and doping width of the doping region 311 will be described below by taking two doping regions 311 on the doping cap layer 31 as an example, as shown in fig. 1, D_DIs the doping depth of the doped region 311, W_DIs the doping length of the doped region 311, L_DIs the length of the gate 32. In an embodiment, the doping depth of the doped region 311 is less than or equal to the thickness of the doping cap layer 31, and the doping width of the doped region 311 is less than or equal to half of the width of the gate 32. By controlling the doping depth of the doped region 311, the doping depth of the doped region 311 is made to be less than or equal to the thickness of the doping cap layer 31, so as to prevent the doped region 311 from extending into the functional layer 20 in contact with the doping cap layer 31, and by controlling the doping width of the doped region 311, the doping width of the doped region 311 is made to be less than or equal to half of the width of the gate 32, so that at least the upper surface of the doped region 311 and the gate 32 are ensured to be in contact with each otherThe best pressure-resistant effect is obtained when parts of the lower surfaces are in contact.

Wherein, the thickness of the doping cap layer 31 is more than or equal to 1nm and less than or equal to 500 nm. That is, the doping depth of the doped region 311 is less than or equal to 500 nm. The thickness of the doping cap layer 31 is selected according to the specific performance of the enhancement-mode gan-based transistor 100, and the embodiment is not limited herein.

In the present embodiment, the distance between the doping cap layer 31 and the source electrode 33 is less than or equal to the distance between the doping cap layer 31 and the drain electrode 34, L in fig. 1_GSIs the distance between the doped cap layer 31 and the source electrode 33, L_GDIs the distance between the doping cap layer 31 and the drain 34. The distance between the doping cap layer 31 and the source electrode 33 can also be larger than the distance between the doping cap layer 31 and the drain electrode 34.

The doping cap layer 31 is doped with acceptor impurities. The acceptor impurity makes the doped cap layer 31 easily attract a free electron from the outside into the doped cap layer, so that the doped cap layer is in a saturated state. Wherein the acceptor impurity is one of magnesium, calcium, zinc, beryllium, iron or carbon, and the doping concentration of the acceptor impurity is more than or equal to 1 × 10¹⁶cm^-3And is less than or equal to 1 × 10²¹cm^-3。

The doped region 311 has donor impurities therein. The donor impurity causes the contents of the doped region 311 to volatilize an electron as a free electron, such that the free electron enters the doped cap layer 31. Wherein the donor impurity is silicon or oxygen, and the doping concentration of the donor impurity is 1 × 10 or more¹⁵cm^-3And is less than or equal to 1 × 10²⁰cm^-3. By selectively doping the donor impurity in the doped region 311, the doped region 311 can improve the fringe electric field of the gate electrode 32, reducing the reliability risk of the edge breakdown of the gate electrode 32.

The greater the concentration of the acceptor impurity doped in the doping cap layer 31 is, and the greater the concentration of the donor impurity doped in the doping region 311 is, the stronger the self-established electric field of the PN junction formed by the doping cap layer 31 and the doping region 311 is, and the thinner the PN junction is.

The doping cap layer 31 makes ohmic contact or schottky contact with the gate electrode 32. When the doping cap layer 31 is in schottky contact with the gate electrode 32, the electron transition barrier formed at the contact surface between the doping cap layer 31 and the gate electrode 32 has a high height and a large thickness.

Referring to fig. 1, in the present embodiment, the functional layer 20 includes a nucleation layer 21, a high resistance layer 22, a high mobility layer 23, and a barrier layer 24, which are sequentially stacked. Wherein the nucleation layer 21 is located between the substrate 10 and the high resistance layer 22, and the high mobility layer 23 is located between the high resistance layer 22 and the barrier layer 24. That is, the nucleation layer 21, the high resistance layer 22, the high mobility layer 23 and the barrier layer 24 are sequentially formed or grown on the substrate 10, the source electrode 33, the drain electrode 34 and the doping cap layer 31 between the source electrode 33 and the drain electrode 34 are formed or grown on the barrier layer 24, and the gate electrode 32 is formed or grown on the doping cap layer 31.

In the present application, the nucleation layer 21, the high resistance layer 22, the high mobility layer 23 and the barrier layer 24 may be sequentially grown or formed on the substrate 10 using Metal-organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) as a growth tool.

Wherein the substrate 10 functions to support the functional layer 20 overlying the substrate 10. The substrate 10 may be made of silicon (Si), silicon carbide (SiC), sapphire (Al2O3), or gallium nitride (GaN). The SiC is adopted as the substrate material, so that the chemical stability is good, the electric conductivity is good, the heat conductivity is good, and visible light is not absorbed; the sapphire is adopted as the substrate material, so that the chemical stability is good, the visible light is not absorbed, the price is moderate, and the manufacturing technology is mature. The GaN substrate is adopted as the material, so that the service life of the device can be prolonged, and the working current density of the device can be improved.

The nucleation layer 21 may be made of one or more of gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).

Both the high resistance layer 22 and the high mobility layer 23 may be made of gallium nitride or aluminum nitride. The high-resistance layer 22 is made of doped gallium nitride or doped aluminum nitride. The high mobility layer 23 uses undoped gallium nitride or undoped aluminum nitride. The high resistance layer 22 performs a buffer function for the high mobility layer 23 grown or formed on the high resistance layer 22. The high mobility layer 23 is a running channel of two-dimensional electron gas.

The barrier layer 24 may be made of one or more of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or indium aluminum nitride (InAlN), and the barrier layer 24 is used to cooperate with the high mobility layer 23 and generate two-dimensional electron gas by polarization in a region where the high mobility layer 23 and the barrier layer 24 are connected, so as to conduct current. Indium gallium nitride (InGaN) or indium aluminum nitride (InAlN) can help to increase the two-dimensional electron gas concentration.

The barrier layer 24 may have a multilayer structure, and the material of two adjacent layers of the barrier layer 24 is different. For example, the barrier layer 24 has a two-layer structure, the first barrier layer 24 is made of aluminum gallium nitride, the second barrier layer 24 covers the first barrier layer 24, and the second barrier layer 24 is made of indium gallium nitride. Alternatively, the barrier layer 24 has a three-layer structure, the first barrier layer 24 is made of aluminum gallium nitride, the second barrier layer 24 covers the first barrier layer 24, the second barrier layer 24 is made of indium gallium nitride, the third barrier layer 24 covers the first barrier layer 24, and the third barrier layer 24 is made of indium gallium nitride. Or the barrier layer 24 has a three-layer structure, the first layer 24 is made of aluminum gallium nitride, the second layer 24 covers the first layer 24, the second layer 24 is made of indium gallium nitride, the third layer 24 covers the first layer 24, and the third layer 24 is made of indium aluminum nitride. By providing the barrier layer 24 as a multilayer structure, the material difference between adjacent two layers in the barrier layer 24 helps to improve the two-dimensional electron gas concentration.

The source electrode 33 and the drain electrode 34 serve to flow a two-dimensional electron gas within the high mobility layer 23 under the effect of an electric field, and conduction between the source electrode 33 and the drain electrode 34 occurs at the two-dimensional electron gas in the high mobility layer 23. The gate electrode 32 is positioned between the source electrode 33 and the drain electrode 34, and the gate electrode 32 is used to allow or block the two-dimensional electron gas to pass through. In this case, the P-type cap layer 31 contains a large amount of holes, and diffuses into the channel of the high mobility layer 23 to neutralize electrons and form a depletion region, which hinders the passage of two-dimensional electron gas. When the gate 32 is applied with positive voltage, holes in the P-type cap layer 31 are consumed, the formed depletion region disappears, and the channel of the high mobility layer 23 is turned on, allowing two-dimensional electron gas to pass through.

The gate 32, the source 33 and the drain 34 may be made of any suitable metal or other material.

Referring to fig. 1, in the present embodiment, a passivation layer may be further disposed on the surface of the enhancement mode gan-based transistor 100. The passivation layers include a first passivation layer 1, a second passivation layer 2, and a third passivation layer (not shown in the figure), wherein the structures and positions of the first passivation layer 1 and the second passivation layer 2 are described in detail in the above embodiments, and are not described herein again. The gate 32 covered by the third passivation layer is far away from the surface of the P-type cap layer 31, and the surfaces of the first passivation layer 1, the second passivation layer 2 and the third passivation layer far away from the functional layer 20 may be located in the same plane.

The passivation layer is used for surface passivation of the enhanced gallium nitride-based transistor 100, so that the surface electron trap density of the enhanced gallium nitride-based transistor 100 is reduced, and current collapse is inhibited. The passivation layer is made of silicon nitride (SiNX), and it is understood that the passivation layer may be made of a suitable material that can reduce the surface electron trap density of the enhancement gan-based transistor 100 and suppress the current collapse of the hemt.

Fig. 20 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Referring to fig. 20, an electronic device 200 according to an embodiment of the present disclosure includes the enhancement mode gallium nitride based transistor 100 provided in the foregoing embodiment and a controller 300, where the controller 300 is connected to the enhancement mode gallium nitride based transistor 100.

The structure and the operation principle of the enhancement-mode gan-based transistor 100 are described in detail in the above embodiments, which are not repeated herein.

The electronic device 200 may be an energy switch, such as a BP-based power amplifier base station, a high-voltage inverter, an adapter of a terminal device, and the like, which is not limited herein.

Fig. 21 is a circuit diagram of an electronic device according to an embodiment of the present application. Referring to fig. 21, fig. 21 is a circuit diagram of an internal power supply module of an adapter of a terminal device, a portion within a dotted line in fig. 21 is a controller 300, and the controller 300 may be a 2.2V-16V, voltage mode synchronous buck controller with a tracking function. The high-channel driver (HG) of the controller 300 determines the on-off state of the enhancement-mode gan-based transistor 100, and when a current needs to flow between the input voltage (Vin) and the output voltage (Vo), HG provides a positive voltage to change the energy band of a depletion region of a channel, and carriers are injected to turn on the channel. In the normal state, HG is at 0 potential and the channel is in the off state.

In the electronic device 200 provided in this embodiment, by providing the enhancement mode gan-based transistor 100, the upper surface of the doped cap layer 31 in the enhancement mode gan-based transistor 100 is in contact with the lower surface of the gate 32, the doped cap layer 31 has at least one doped region 311, the upper surface of the doped region 311 is at least a portion of the upper surface of the doped cap layer 31, and the upper surface of the doped region 311 is in contact with the lower surface of the gate 32. When voltage is applied to the gate 32, because the lower surface of the gate 32 is in contact with the upper surface of the doped region 311, under the action of an electric field, carrier diffusion occurs to the doped cap layer 31 from the doped region 311 in contact with the gate 32, a depletion region is formed in the doped cap layer 31 until the doped region 311 is merged with the doped cap layer 31, and the merged doped cap layer 31 and doped region 311 pinch off a current channel on the surface of the gate 32, so that the leakage of the gate 32 is reduced, the gate voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor 100 is improved.

The following are embodiments of the methods of the present application that may be used to perform the embodiments of the methods of the present application. For details which are not disclosed in the method embodiments of the present application, reference is made to the embodiments of the apparatus of the present application.

Fig. 22 is a flowchart of a method for manufacturing an enhanced gallium nitride-based transistor according to an embodiment of the present disclosure. Referring to fig. 22, an embodiment of the present application provides a method for manufacturing an enhanced gallium nitride-based transistor, including:

s101, the functional layer 20 is formed on the substrate 10.

And S102, forming a source electrode 33, a doping cap layer 31 and a drain electrode 34 on the surface of the functional layer 20, which faces away from the substrate 10, wherein the doping cap layer 31 is positioned between the source electrode 33 and the drain electrode 34, and the source electrode 33, the drain electrode 34 and the doping cap layer 31 are spaced.

S103, forming at least one forming doped region 311 in the doping cap layer 31.

And S104, forming a gate 32 on the surface of the doping cap layer 31 departing from the functional layer 20, wherein the upper surface of the doping region 311 is at least one part of the surface of the doping cap layer 31 facing the gate 32, the upper surface of the doping region 311 is in contact with the lower surface of the gate 32, and the lower surface of the gate 32 is the surface of the gate 32 facing the doping cap layer 31.

In the enhanced gallium nitride-based transistor 100 prepared by the preparation method of the enhanced gallium nitride-based transistor, the upper surface of the doped cap layer 31 is in contact with the lower surface of the gate 32, the doped cap layer 31 has at least one doped region 311, the upper surface of the doped region 311 is at least a part of the upper surface of the doped cap layer 31, and the upper surface of the doped region 311 is in contact with the lower surface of the gate 32. When voltage is applied to the gate 32, because the lower surface of the gate 32 is in contact with the upper surface of the doped region 311, under the action of an electric field, carrier diffusion occurs to the doped cap layer 31 from the doped region 311 in contact with the gate 32, a depletion region is formed in the doped cap layer 31 until the doped region 311 is merged with the doped cap layer 31, and the merged doped cap layer 31 and doped region 311 pinch off a current channel on the surface of the gate 32, so that the leakage of the gate 32 is reduced, the gate voltage swing is improved, and the reliability of the enhanced gallium nitride-based transistor 100 is improved.

Fig. 23 is a flowchart illustrating a method for fabricating an enhanced gan-based transistor according to an embodiment of the present disclosure; fig. 24a to 24j are schematic structural diagrams of respective manufacturing extremes in a manufacturing method of an enhancement mode gallium nitride based transistor according to an embodiment of the present application. Referring to fig. 23 and fig. 24a to 24j, an embodiment of the present application provides a method for manufacturing an enhanced gallium nitride-based transistor, including:

and S201, growing and forming a nucleation layer 21 on the substrate 10.

As the material of the substrate 10, silicon (Si), silicon carbide (SiC), or sapphire (Al2O3) can be used. The nucleation layer 21 may be made of one or more of gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN). The formation temperature of the nucleation layer 21 is greater than or equal to 1000 ℃ and less than or equal to 1200 ℃, and the thickness of the nucleation layer 21 is greater than or equal to 45nm and less than or equal to 55 nm.

And S202, growing and forming the high-resistance layer 22 on the nucleation layer 21.

The material of the high resistance layer 22 may be doped gallium nitride or doped aluminum nitride, the forming temperature of the high resistance layer 22 is greater than or equal to 900 ℃ and less than or equal to 1100 ℃, and the thickness of the nucleation layer 22 is greater than or equal to 1nm and less than or equal to 3 nm.

And S203, growing and forming a high mobility layer 23 on the high resistance layer 22.

The material of the high mobility layer 23 may be undoped gan or undoped aln. The high mobility layer 23 is formed at a temperature of 900 ℃ or more and 1100 ℃ or less, and the high mobility layer 23 has a thickness of 150nm or more and 250nm or less.

And S204, growing and forming a barrier layer 24 on the high mobility layer 23.

The barrier layer 24 may be made of one or more of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or indium aluminum nitride (InAlN), the barrier layer 24 may have a multi-layer structure, and the adjacent two layers of the barrier layer 24 are made of different materials. The formation temperature of the barrier layer 14 is 900 ℃ or higher and 1100 ℃ or lower, and the thickness of the barrier layer 14 is 20nm or higher and 30nm or lower.

And S205, growing a P-type cap layer on the barrier layer 24.

The forming temperature of the P-type cap layer is greater than or equal to 900 ℃ and less than or equal to 1100 ℃, and the thickness of the P-type cap layer is greater than or equal to 60nm and less than or equal to 80 nm.

An acceptor impurity is doped in the P-type cap layer, wherein the acceptor impurity is one of magnesium, calcium, zinc, beryllium, iron or carbon, and the doping concentration of the acceptor impurity is greater than or equal to 1 × 10¹⁶cm^-3And is less than or equal to 1 × 10²¹cm^-3。

S206, forming at least one doped region 311 in the P-type cap layer.

Wherein the forming of the at least one doped region 311 in the P-type cap layer comprises: at least one preset region is formed on the surface of the P-type cap layer away from the functional layer 20, donor impurities are doped on the surface of the P-type cap layer exposed in the preset region, and an N-type high-concentration doped region is formed. The doping depth of the N-type high-concentration doping region is less than or equal to the thickness of the doping cap layer 31, and the doping width of the N-type high-concentration doping region is less than or equal to half of the width of the gate 32.

Doping donor impurity in the preset region, wherein the donor impurity is silicon or oxygen, and the doping concentration of the donor impurity is greater than or equal to 1 × 10¹⁵cm^-3And is less than or equal to 1 × 10²⁰cm^-3。

The shape of the preset region is the same as the shape of the top view of the doped region 311 in the above embodiment of the enhancement-mode gan-based transistor 100, and the shape and the position of the top view of the doped region 311 are described in detail in the above embodiment, which is not described herein again.

S207, etching the P-type cap layer, and forming a step surface with the P-type cap layer on the barrier layer 24.

And S208, manufacturing a source electrode 33 and a drain electrode 34 on the barrier layer 24.

Specifically, the source electrode 33 is an ohmic contact source electrode, and the drain electrode 34 is an ohmic contact drain electrode.

S209, manufacturing a grid electrode 32 on the P-type cap layer.

A specific P-type cap layer makes ohmic or schottky contact with the gate 32.

The following describes a method for manufacturing an enhanced gallium nitride-based transistor according to an embodiment of the present application with reference to specific embodiments.

The embodiment of the application provides a preparation method of an enhanced gallium nitride-based transistor, which comprises the following steps:

and S301, growing and forming a nucleation layer 21 on the substrate 10.

The substrate 10 is an 8-inch P-type silicon substrate. The nucleation layer 21 is made of aluminum nitride. The growth temperature of the nucleation layer 21 is 1100 deg.c, and the growth thickness of the nucleation layer 21 is 50 nm.

And S302, growing and forming the high-resistance layer 22 on the nucleation layer 21.

The material of the high-resistance layer 22 is doped gallium nitride, gallium nitride doped carbon element, carbon elementThe doping concentration is 5X 10¹⁶cm^-3The growth temperature of the high-resistance layer 22 is 1000 ℃, and the growth thickness of the nucleation layer is 2 nm.

And S303, growing and forming a high mobility layer 23 on the high resistance layer 22.

The high mobility layer 23 is made of undoped gallium nitride. The growth temperature of the high mobility layer 23 was 1000 deg.c, and the growth thickness of the high mobility layer 23 was 200 nm.

And S304, growing and forming a barrier layer 24 on the high mobility layer 23.

The barrier layer 24 is made of gallium aluminum nitride, the aluminum content in the gallium aluminum nitride is 25%, the growth temperature of the barrier layer 14 is 1000 ℃, and the growth thickness of the barrier layer 14 is 25 nm.

S305, growing a P-type cap layer in a first state on the barrier layer 24.

Wherein, the P-type cap layer is made of gallium nitride doped with magnesium element with the doping concentration of 1 × 10¹⁷cm^-3The growth temperature of the P-type cap layer is 1000 ℃, and the growth thickness of the P-type cap layer is 70 nm. Note that the first sidewall of the P-type cap layer in the first state is flush with the first sidewall of the barrier layer 24, and the second sidewall of the P-type cap layer is flush with the second sidewall of the barrier layer 24.

S306, forming two doped regions 311 in the P-type cap layer in the first state.

Forming or growing a mask 312 on the P-type cap layer in the first state, etching a predetermined region on the mask 312 according to the position and number of the doped regions 311, and implanting silicon ions into the predetermined region, wherein the concentration of the implanted silicon ions is 1 × 10¹⁸cm^-3The depth of implanted silicon ions is W_DIs 400 nm.

S307, the P-type cap layer in the first state is etched, and a step surface with the P-type cap layer in the second state is formed on the barrier layer 24.

Wherein, the first side wall and the second side wall of the P-type cap layer in the first state are etched to expose the surface of the barrier layer 24 and leave positions for manufacturing the source electrode 33 and the drain electrode 34 on the barrier layer 24, or the P-type cap layer in the first state is etched to form a platform on the barrier layer 24A step surface to prepare for the subsequent fabrication of the source electrode 33 and the drain electrode 34 on the step surface. Simultaneously ensuring the width D of the two doped regions 311 implanted with silicon ions_DAre all 80nm to form a P-type cap layer in a second state, i.e., a P-type cap layer in a final state.

S308, the source electrode 33 and the drain electrode 34 are formed on the barrier layer 24.

Wherein, titanium aluminum alloy (TiAl) metal is sputtered on the step surface or the exposed surface of the barrier layer 24 to form a source electrode 33 and a drain electrode 34, a P-type cap layer is positioned between the source electrode 33 and the drain electrode 34, a first side wall of the source electrode 33 is flush with a first side wall of the barrier layer 24, and a second side wall of the drain electrode 34 is flush with a second side wall of the barrier layer 24.

S309, manufacturing a grid electrode 32 on the P-type cap layer.

Wherein, titanium-nitrogen alloy (TiN) metal is sputtered on the surface of the P-type cap layer away from the barrier layer 24 to form a gate 32, so as to form the enhanced gallium nitride-based transistor 100.

And S310, passivating the enhancement mode gallium nitride based transistor 100.

Specifically, a passivation layer is formed on the enhancement mode gallium nitride based transistor 100. The structure and position of the passivation layer are described in detail in the above embodiment of the enhancement-mode gan-based transistor 100, and the details of this embodiment are not repeated herein.

Simulation software is adopted to test the enhanced gallium nitride-based transistor 100 prepared in the above embodiments S301 to S310. Wherein, the simulation software is Silvaco.

Fig. 25 is a graph comparing the gate characteristics of the enhancement mode gan-based transistor fabricated according to the present invention with those of the conventional enhancement mode gan-based transistor. Referring to fig. 25, the curve of the box in fig. 25 is the gate characteristics of the enhancement mode GaN-based transistor fabricated by the present application, and the curve of the circle in fig. 25 is the gate characteristics of the conventional P-GaN cap layer hemt device without N-type heavily doped region. Wherein, the grid drain voltage is 0V in the application. As can be seen from fig. 25, the enhanced gan-based transistor fabricated by the present application has smaller gate leakage.

Fig. 26 is a graph comparing the output characteristics of the enhancement type gallium nitride based transistor manufactured according to the present invention with those of the conventional enhancement type gallium nitride based transistor. Referring to fig. 26, the curve of the square in fig. 26 is the output characteristic of the enhancement mode GaN-based transistor fabricated by the present application, and the curve of the circle in fig. 26 is the output characteristic of the conventional p-GaN cap layer hemt device without the N-type heavily doped region. Wherein, the grid voltage is 5V in the application. As can be seen from fig. 26, the enhancement mode gallium nitride based transistor prepared by the present application has a higher saturation output current density.

Fig. 27 is a graph comparing transfer characteristics of an enhancement type gallium nitride based transistor manufactured by the present application and a conventional enhancement type gallium nitride based transistor. Referring to fig. 27, the curve of the square in fig. 27 is the transfer characteristic of the enhancement mode GaN-based transistor fabricated by the present application, and the curve of the circle in fig. 27 is the transfer characteristic of the p-GaN cap layer hemt device without the N-type heavily doped region. Wherein, the grid voltage is 15V in the application. As can be seen from fig. 27, the enhancement type gallium nitride based transistor prepared by the present application has a small variation in threshold voltage.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An enhancement mode gallium nitride-based transistor is characterized by comprising a substrate, a functional layer and a transistor layer which are arranged in a stacking mode, wherein the substrate is located on one side of the functional layer, the transistor layer is located on one side, away from the substrate, of the functional layer, the transistor layer comprises a doping cap layer, a grid electrode, a source electrode and a drain electrode, the doping cap layer, the source electrode and the drain electrode are in contact with the surface of the functional layer and are isolated from each other, the doping cap layer is located between the source electrode and the drain electrode, and the grid electrode is arranged on the surface, away from the functional layer, of the doping cap layer;

the doped cap layer is provided with at least one doped region, the upper surface of the doped region is at least one part of the surface of the doped cap layer facing the grid electrode, the upper surface of the doped region is in contact with the lower surface of the grid electrode, and the lower surface of the grid electrode is the surface of the grid electrode facing the doped cap layer.

2. The enhancement mode GaN-based transistor according to claim 1, wherein the doped region is an N-type heavily doped region and the doped cap layer is a P-type cap layer.

3. The enhancement mode gallium nitride based transistor according to claim 1, wherein the upper surface of the doped region is in contact with a portion of the lower surface of the gate, or wherein an edge of the upper surface of the doped region coincides with an edge of the lower surface of the gate.

4. The enhancement mode GaN-based transistor according to claim 3, wherein the number of the doped regions is at least two, and at least two of the doped regions are spaced apart.

5. The enhancement mode GaN-based transistor according to any of claims 1 to 4, wherein the doping depth of the doped region is less than or equal to the thickness of the doped cap layer, and the doping width of the doped region is less than or equal to half of the width of the gate.

6. An enhanced gallium nitride based transistor according to claim 1 or 2, wherein said doped cap layer is doped with acceptor impurities.

7. An enhancement mode gallium nitride based transistor according to claim 1 or claim 2 wherein the doped region has donor impurities therein.

8. An electronic device comprising the enhanced gallium nitride-based transistor according to any one of claims 1 to 7 and a controller, wherein the controller is connected to the enhanced gallium nitride-based transistor.

9. A preparation method of an enhanced gallium nitride-based transistor is characterized by comprising the following steps:

forming a functional layer on a substrate;

forming a source electrode, a doping cap layer and a drain electrode on the surface of the functional layer, which is far away from the substrate, wherein the doping cap layer is positioned between the source electrode and the drain electrode, and the source electrode, the drain electrode and the doping cap layer are provided with intervals;

forming at least one doped region within the doped cap layer;

10. The method of fabricating an enhanced gallium nitride-based transistor according to claim 9, wherein forming a doped cap layer on a surface of the functional layer facing away from the substrate comprises:

11. The method according to claim 10, further comprising, after forming a P-type cap layer on a surface of the functional layer facing away from the substrate:

and doping acceptor impurities in the P-type cap layer.

12. The method for manufacturing an enhancement mode gallium nitride-based transistor according to any one of claims 9 to 11, wherein the temperature for forming the doped cap layer is greater than or equal to 900 ℃ and less than or equal to 1100 ℃, and the thickness of the doped cap layer is greater than or equal to 60nm and less than or equal to 80 nm.

13. The method of claim 9 wherein forming at least one doped region within the doped cap layer comprises:

forming at least one preset region on the surface of the doped cap layer, which is far away from the functional layer, and doping donor impurities on the surface of the P-type cap layer exposed in the preset region to form an N-type high-concentration doped region;