CN208028062U - A kind of enhanced and depletion type GaN HEMT integrated morphologies - Google Patents
A kind of enhanced and depletion type GaN HEMT integrated morphologies Download PDFInfo
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- CN208028062U CN208028062U CN201820559173.0U CN201820559173U CN208028062U CN 208028062 U CN208028062 U CN 208028062U CN 201820559173 U CN201820559173 U CN 201820559173U CN 208028062 U CN208028062 U CN 208028062U
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Abstract
The utility model discloses a kind of enhanced and depletion type GaN HEMT integrated morphologies, including：Substrate；Buffer layer is formed on the substrate；The HEMT integrated morphologies further include the enhanced HEMT device being formed on the buffer layer and depletion type HEMT device；The enhanced HEMT device includes the first GaN channel layers for being formed in the buffer layer, the first barrier layer being formed on the first GaN channel layers；The depletion type HEMT device includes the 2nd GaN channel layers for being formed in the buffer layer, the first barrier layer being formed on the 2nd GaN channel layers；The HEMT integrated morphologies further include separation layer, and the separation layer is between the first GaN channel layers and the 2nd GaN channel layers and between first barrier layer and second barrier layer the enhanced HEMT device and the depletion type HEMT device to be isolated.Enhanced and depletion type GaN HEMT devices single-chip integration is realized, is the enhanced and depletion type GaN HEMT integrated morphologies of complete plane.
Description
Technical field
The utility model belongs to field of semiconductor devices, and in particular to a kind of integrated knots of enhanced and depletion type GaN HEMT
Structure.
Background technology
The research of GaN material and device and forward position and hot spot that application is current global semiconductor research.GaN material with
SiC and diamond are known as third generation semi-conducting material together.GaN material wide, critical breakdown electric field with energy gap
The advantages that height, electron saturation velocities are high, thermal conductivity is high, heterojunction boundary two-dimensional electron gas is high, is next-generation power device
Ideal substitute.
The operating mode of traditional GaN device is mostly depletion device, needs positive and negative voltage biasing on and off,
There is a problem of power consumption height and designs complexity.And the introducing of enhancement device, it is only necessary to positive voltage, to simplify circuit and
Reduce cost.In addition, for GaN logical devices, in direct-coupling field-effect transistor logic, enhancement device may be used as driving
Dynamic device, depletion device may be used as loading.
Realize the high density during enhanced and depletion type GaN HEMT devices are integrated and high consistency, the enhancing of complete plane
Type and depletion type GaN HEMT integrated morphologies have important researching value and wide application prospect.
Utility model content
The purpose of this utility model be solve the problems, such as above-mentioned the deficiencies in the prior art and, it is proposed that it is a kind of enhanced
With depletion type GaN HEMT integrated morphologies.
In order to achieve the above objectives, the technical solution adopted in the utility model is as follows：
A kind of enhanced and depletion type GaN HEMT integrated morphologies, including：
Substrate；
Buffer layer is formed on the substrate；
The HEMT integrated morphologies further include the enhanced HEMT device being formed on the buffer layer and depletion type HEMT
Device；
The enhanced HEMT device includes the first GaN channel layers being formed on the buffer layer, is formed in described
The first barrier layer on one GaN channel layers；
The depletion type HEMT device includes the 2nd GaN channel layers being formed on the buffer layer, is formed in described
The second barrier layer on two GaN channel layers；
The HEMT integrated morphologies further include separation layer, and the separation layer is located at the first GaN channel layers and described
With by the enhanced HEMT device and institute between two GaN channel layers and between first barrier layer and second barrier layer
Depletion type HEMT device is stated to be isolated.
In one embodiment, the first GaN channel layers and the 2nd GaN channel layers are integrally formed at the buffer layer
Upper constituting channel layer, first barrier layer and second barrier layer, which are integrally formed on the channel layer, constitutes barrier layer,
The separation layer is formed by carrying out ion implanting into the channel layer and the barrier layer.
In one embodiment, the separation layer is the laminated construction formed by ion implanting, the injection of the laminated construction
Element is H, He, N, F, Mg, Ar, Zn, Si or O.
In one embodiment, the lower end of the separation layer extends in the buffer layer top.
In one embodiment, it is 0-200nm that the separation layer, which stretches into the thickness in the buffer layer,.
In one embodiment, the thickness of the buffer layer is 1-3 μm.
In one embodiment, the enhanced HEMT device further includes the first p-type being formed on first barrier layer
Cap layers and the first Source and drain metal level, the first barrier metal layer being formed in the first p-type cap layers and first medium layer and formation
One or more N-type injection regions in the first p-type cap layers；
The depletion type HEMT device further includes the second p-type cap layers being formed on second barrier layer and second gate gold
Belong to layer and the second Source and drain metal level, the second dielectric layer being formed in the second p-type cap layers and is formed in the second p-type cap
One or more N-type injection regions in layer.
In one embodiment, the first p-type cap layers, the second p-type cap layers are the p-type doping that thickness is 30-200nm
AlGaN, AlInN, AlScN, AlN, GaN, AlInGaN, AlInScN or AlGaScN layers, doping concentration is 1 × 1018 -1×
1020 cm-3Between, doped chemical is the codope of Mg or C or Mg and C；
And/or the dielectric layer is the single layer structure or laminated construction that thickness is 1-200nm, the single layer structure or institute
State laminated construction every layer is silicon nitride, silica, alumina nitrogen or aln layer；
And/or first barrier metal layer, second barrier metal layer are the single layer structure or folded that thickness is 10nm-1 μm
Every layer of layer structure, the single layer structure or the laminated construction is tantalum nitride, titanium nitride, titanium, nickel, platinum, gold, tungsten or aluminium layer；
And/or first Source and drain metal level, second Source and drain metal level are the single layer structure that thickness is 10nm-1 μm
Or laminated construction, every layer of the single layer structure or the laminated construction be nickel, germanium, gold, palladium, titanium, copper, platinum, tungsten, aluminium
Layer；
And/or between first barrier metal layer and first Source and drain metal level between be separated with multiple N-types injections
Area, between second barrier metal layer and second Source and drain metal level between be separated with multiple N-type injection regions, the N-type note
The width for entering area is 20nm-10 μm, 200nm-20 μm is divided between adjacent N-type injection region, the number of the N-type injection region is 1-
25；The upper and lower surface of the N-type injection region respectively with the first p-type cap layers or the upper and lower surface of the second p-type cap layers
Flush and vertically penetrate the first p-type cap layers or the second p-type cap layers；The N-type injection region is n-type doping
AlGaN, AlInN, AlScN, AlN, GaN, AlInGaN, AlInScN or AlGaScN layers, doped chemical Si, doping concentration is 1
×1018 -1×1020 cm-3Between；
And/or the level interval between the first medium layer and first Source and drain metal level is 10nm-3 μm；It is described
Level interval between second dielectric layer and second Source and drain metal level is 10nm-3 μm.
In one embodiment, the substrate is one kind in silicon, sapphire, single-crystal silicon carbide substrate；
And/or the buffer layer is AlN, AlGaN or GaN layer.
In one embodiment, the first GaN channel layers, the 2nd GaN channel layers are the GaN that thickness is 1-500nm
Single crystalline layer；
And/or first barrier layer, second barrier layer be thickness be 5-200nm AlGaN, AlInN,
AlScN, AlN, GaN, AlInGaN, AlInScN or AlGaScN layers.
The utility model uses above scheme, has the following advantages that compared with prior art：
By be arranged between the first GaN channel layers, the 2nd GaN channel layers and the first barrier layer, the second barrier layer it
Between separation layer enhanced HEMT device and depletion type HEMT device are isolated, realize enhanced and depletion type GaN HEMT devices
The single-chip integration of part, described enhanced and depletion type GaN HEMT integrated morphologies have high density and high consistency, are completely flat
The enhanced and depletion type GaN HEMT integrated morphologies in face have important researching value and wide application prospect.
Description of the drawings
It, below will be to needed in embodiment description in order to illustrate more clearly of the technical solution of the utility model
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the utility model, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of enhanced and depletion type GaN HEMT integrated morphologies the diagrammatic cross-section according to the utility model；
Fig. 2 is the stream of a kind of enhanced and depletion type GaN HEMT integrated morphologies manufacturing method according to the present utility model
Cheng Tu.
Wherein, 1, substrate；2, buffer layer；3a, the first GaN channel layers；3b, the 2nd GaN channel layers；4a, the first barrier layer；
4b, the second barrier layer；5a, the first p-type cap layers；5b, the second p-type cap layers；6a, first medium layer；6b, second dielectric layer；7, N-type
Injection region；8a, the first Source and drain metal level；8b, the second Source and drain metal level；9a, the first barrier metal layer；9b, the second barrier metal layer；
10, separation layer.
Specific implementation mode
The preferred embodiment of the utility model is described in detail below in conjunction with the accompanying drawings, so that the advantages of the utility model
It can be easier to be understood by the person skilled in the art with feature.The utility model is according to those skilled in the art to the definition in orientation
It usual observation visual angle and is defined to describe convenient, does not limit specific direction.
Fig. 1 shows a kind of enhanced and depletion type GaN HEMT integrated morphologies of the present embodiment.It, should shown in referring to Fig.1
The buffer layer 2 and be formed in described that enhanced and depletion type GaN HEMT integrated morphologies include substrate 1, are formed on substrate 1
Enhanced HEMT device on buffer layer 2 and depletion type HEMT device.
The enhanced HEMT device includes the first GaN channel layers 3a for being formed in the buffer layer 2, is formed in described
The first barrier layer 4a on one GaN channel layers 3a, the first p-type cap layers 5a being formed on the first barrier layer 4a and the first source
It leaks metal layer 8a, the first barrier metal layer 9a being formed on the first p-type cap layers 5a and first medium layer 6a and is formed in institute
State one or more N-type injection regions 7 in the first p-type cap layers 5a.Wherein, the marginal portion of the first barrier metal layer 9a is covered in first
On dielectric layer 6a, and between the first Source and drain metal level 8a.
The depletion type HEMT device includes the 2nd GaN channel layers 3b for being formed in the buffer layer 2, is formed in described
The second barrier layer 4b on two GaN channel layers 3b, the second p-type cap layers 5b and second gate being formed on the second barrier layer 4b
Metal layer 9b and the second Source and drain metal level 8b, the second dielectric layer 6b being formed on the second p-type cap layers 5b and it is formed in institute
State one or more N-type injection regions 7 in the second p-type cap layers 5b.Wherein, the second p-type cap layers 5b and second dielectric layer 6b are second
The marginal portion of the both sides barrier metal layer 9b, the second barrier metal layer 9b is covered on second dielectric layer 6b, and positioned at the second source and drain gold
Between category layer 8b.
Wherein, the first GaN channel layers 3a and the 2nd GaN channel layers 3b are integrally formed on the buffer layer 2
Constituting channel layer, the first barrier layer 4a and the second barrier layer 4b are integrally formed on the channel layer and constitute potential barrier
Layer.The HEMT integrated morphologies further include the separation layer 10 being at least set in channel layer and barrier layer, and separation layer 10 is by described
Ion implanting is carried out in channel layer and the barrier layer to be formed, specially by H, He, N, F, Mg, Ar, Zn, Si of ion implanting or
The single layer structure or laminated construction that O is formed.Therefore, separation layer 10 is located at the first GaN channel layers 3a and the 2nd GaN ditches
With by the enhanced HEMT device and institute between channel layer 3b and between the first barrier layer 4a and the second barrier layer 4b
Depletion type HEMT device is stated to be isolated.
It should also be noted that, the lower end of separation layer 10 also may extend to 2 top of buffer layer, i.e. separation layer 10 stretches into institute
It is 0-200nm to state the thickness in buffer layer 2.In the present embodiment, the upper surface of the separation layer 10 is flushed with barrier layer, and edge
Vertical direction penetrates barrier layer and channel layer and its lower surface is located in the buffer layer 2, and the separation layer 10 gos deep into buffer layer 2
In thickness be 30 nanometers, the separation layer 10 be ion implanting 10 lower surface horizontal direction of the separation layer more than potential barrier
The element of the material layer laminate of layer, channel layer, the buffer layer 2, ion implanting is He.
Substrate 1 is silicon substrate.Buffer layer 2 is GaN layer, and thickness is 1.5 μm.First GaN channel layers 3a, the 2nd GaN raceway grooves
Layer 3b is the GaN single crystal layer of unintentional doping, thickness 50nm.First barrier layer 4a and the second barrier layer 4b is unintentional mixes
Miscellaneous AlGaN single crystalline layers, thickness are 20 nanometers.First p-type cap layers 5a and the second p-type cap layers 5b is the GaN layer of p-type doping,
Doping concentration is 1 × 1019 cm-3, doped chemical Mg, thickness is 70 nanometers.First medium layer 6a and second dielectric layer 6b
It is silicon nitride, thickness is 50 nanometers.
Multiple N-type injection regions 7 are separated between the first barrier metal layer 9a and the first Source and drain metal level 8a,
Multiple N-type injection regions 7 are separated between the second barrier metal layer 9b and the second Source and drain metal level 8b.The N-type
The width of injection region 7 is 300nm, and 600nm is divided between adjacent N-type injection region 7.The number of the N-type injection region 7 is 1-25
A, specific in the present embodiment, the N-type injection region 7 between the first barrier metal layer 9a and the first Source and drain metal level 8a is 8, and
It it is 5 close to drain electrode side；N-type injection region 7 between second barrier metal layer 9b and the second Source and drain metal level 8b is 8, and is leaned on
Nearly drain electrode side is 5.The upper and lower surface of the N-type injection region 7 respectively with second p-types of the first p-type cap layers 5a or described
The upper and lower surface of cap layers 5b flushes and vertically penetrates the first p-type cap layers 5a or described second p-type cap layers 5b.It is described
The material of N-type injection region 7 and the GaN layer of n-type doping, doped chemical Si, doping concentration is 1 × 1019 cm-3。
Level interval between the first medium layer 6a and the first Source and drain metal level 8a is 500nm；
Level interval between the second dielectric layer 6b and the first Source and drain metal level 8b is 500nm；
The first Source and drain metal level 8a, the second Source and drain metal level 8b are respectively Ti/Al/Ni/Au laminations, thickness 200
Nanometer
The first barrier metal layer 9a and the second barrier metal layer 9b is Ni/Au laminations, the first barrier metal layer 9a
Thickness with the second barrier metal layer 9b is 200 nanometers.
Aforementioned enhanced and depletion type GaN HEMT integrated morphologies preparation method, described method includes following steps：
Step 1：Material layer, material layer, the potential barrier of institute's channel layer of buffer layer 2 described in extension successively on the substrate 1
Material layer, the material layer of p-type cap layers of layer；
Step 2：The material layer of metallization medium layer forms institute using photoresist into line mask by the way of ion implanting
State N-type injection region 7；
Step 3：Fall the material of the material layer and part p-type cap layers of certain media layer by mask hole etching technology selective etch
The bed of material forms the Source and drain metal level on barrier layer.
Step 4：The material layer for falling certain media layer by mask hole etching technology selective etch forms the first grid gold
Belong to layer 9a and the second barrier metal layer 9b
Step 5：The separation layer 10 is formed by the way of ion implanting；
It is to use MOCVD in the step 1（Metal Organic Chemical Vapor Deposition）Mode extension described in buffer
Material layer, the material layer of the material layer of the GaN channel layers, the material layer of the barrier layer and the p-type cap layers of layer 2.
In the step 2, using plasma reinforced chemical vapour deposition（PECVD）Mode deposit the material of the dielectric layer
The bed of material carries out Si ion implantings after spin coating, photoetching, development using photoresist into line mask to the material layer of the p-type cap layers,
Photoresist is removed, rapid thermal annealing is carried out, eliminates implant damage and activator impurity, annealing temperature is 1100 DEG C, the time 100
Second, form the N-type injection region 7.
In the step 3, the material of the p-type cap layers is etched using high temperature sense coupling technique
Layer, 1 temperature of substrate is 300 DEG C, using BCl3Mixed gas with Ar is as etching gas.
In the step 3, the Source and drain metal level is formed by the way of photoetching, evaporation, stripping, in the source and drain metal
The natural oxide for removing sample surfaces before layer evaporation with diluted hydrochloric acid, by annealed alloy in 4 surface shape of the barrier layer
At Ohmic contact, the Source and drain metal level is formed by a metal deposition process, and the thickness of the Source and drain metal level is all identical.
In the step 4, the first barrier metal layer 9a and described second is formed by the way of photoetching, evaporation, stripping
Barrier metal layer 9b removes sample surfaces before the first barrier metal layer 9a and the second barrier metal layer 9b evaporations with diluted hydrochloric acid
Natural oxide.The first barrier metal layer 9a and the second barrier metal layer 9b are formed by a metal deposition process,
Thickness of the first barrier metal layer 9a and the second barrier metal layer 9b on the dielectric layer is identical.
In the step 5, using photoresist into line mask, after spin coating, photoetching, development, in the region of the separation layer 10
Ion implanting is carried out, for Implantation Energy between 50 keV, implantation dosage is 2 × 1015 cm-2Between, the separation layer 10 is formed,
And remove remaining photoresist.
The utility model can be formed and be exhausted by forming N-type injection region 7 in p-type cap layers between the gate and the drain
Area makes it have higher breakdown voltage.The utility model uses ion implantation technology, improves the making of GaN base HEMT device
The consistency and reliability of technique.The corresponding HEMT devices of first barrier metal layer 9a are enhancement device, the second barrier metal layer 9b
Corresponding HEMT device is depletion device, and enhanced and depletion type GaN HEMT devices are isolated by separation layer 10, to
Realize enhanced and depletion type GaN HEMT devices single-chip integration, described enhanced and depletion type GaN HEMT integrated morphologies
It is the enhanced and depletion type GaN HEMT integrated morphologies of complete plane with high density and high consistency, there is important grind
Study carefully value and wide application prospect.
Above-described embodiment is only the technical concepts and features for illustrating the utility model, is a kind of preferred embodiment, mesh
Be that person skilled in the art can understand the content of the utility model and implement according to this, this reality can not be limited with this
With novel protection domain.Equivalent transformation or modification made by all Spirit Essences according to the present utility model should all be covered at this
Within the protection domain of utility model.
Claims (10)
1. a kind of enhanced and depletion type GaN HEMT integrated morphologies, including：
Substrate；
Buffer layer is formed on the substrate；
It is characterized in that, the HEMT integrated morphologies further include the enhanced HEMT device being formed on the buffer layer and exhaust
Type HEMT device；
The enhanced HEMT device includes the first GaN channel layers being formed on the buffer layer, is formed in the first GaN
The first barrier layer on channel layer；
The depletion type HEMT device includes the 2nd GaN channel layers being formed on the buffer layer, is formed in the 2nd GaN
The second barrier layer on channel layer；
The HEMT integrated morphologies further include separation layer, and the separation layer is located at the first GaN channel layers and the 2nd GaN
With by the enhanced HEMT device and the consumption between channel layer and between first barrier layer and second barrier layer
Type HEMT device to the greatest extent is isolated.
2. according to claim 1 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：Described first
GaN channel layers and the 2nd GaN channel layers are integrally formed at constituting channel layer on the buffer layer, first barrier layer and
Second barrier layer, which is integrally formed on the channel layer, constitutes barrier layer, and the separation layer is by the channel layer and institute
Progress ion implanting in barrier layer is stated to be formed.
3. according to claim 1 or 2 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：It is described every
Absciss layer is the laminated construction formed by ion implanting, the injection element of the laminated construction be H, He, N, F, Mg, Ar, Zn, Si or
O。
4. according to claim 1 or 2 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：It is described every
The lower end of absciss layer extends in the buffer layer top.
5. according to claim 4 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：The separation layer
The thickness stretched into the buffer layer is 0-200nm.
6. according to claim 5 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：The buffer layer
Thickness be 1-3 μm.
7. according to claim 1 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：It is described enhanced
HEMT device further includes the first p-type cap layers being formed on first barrier layer and the first Source and drain metal level, it is described to be formed in
The first barrier metal layer and first medium layer in first p-type cap layers and one or more N-types being formed in the first p-type cap layers
Injection region；
The depletion type HEMT device further includes the second p-type cap layers and the second barrier metal layer being formed on second barrier layer
And it second Source and drain metal level, the second dielectric layer that is formed in the second p-type cap layers and is formed in the second p-type cap layers
One or more N-type injection regions.
8. according to claim 7 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：First P
Type cap layers, the second p-type cap layers be thickness be 30-200nm p-type doping AlGaN, AlInN, AlScN, AlN, GaN,
AlInGaN, AlInScN or AlGaScN layers, doping concentration is 1 × 1018 -1×1020 cm-3Between, doped chemical is Mg or C,
Or the codope of Mg and C；
And/or the dielectric layer is the single layer structure or laminated construction that thickness is 1-200nm, the single layer structure or described folded
Every layer of layer structure is silicon nitride, silica, alumina nitrogen or aln layer；
And/or first barrier metal layer, second barrier metal layer are the single layer structure or lamination knot that thickness is 10nm-1 μm
Every layer of structure, the single layer structure or the laminated construction is tantalum nitride, titanium nitride, titanium, nickel, platinum, gold, tungsten or aluminium layer；
And/or first Source and drain metal level, second Source and drain metal level are the single layer structure or folded that thickness is 10nm-1 μm
Every layer of layer structure, the single layer structure or the laminated construction is nickel, germanium, gold, palladium, titanium, copper, platinum, tungsten, aluminium layer；
And/or between first barrier metal layer and first Source and drain metal level between be separated with multiple N-type injection regions, institute
Multiple N-type injection regions are separated between stating between the second barrier metal layer and second Source and drain metal level, the N-type injection region
Width is 20nm-10 μm, 200nm-20 μm is divided between adjacent N-type injection region, the number of the N-type injection region is 1-25；
The upper and lower surface of the N-type injection region flushes simultaneously with the upper and lower surface of the first p-type cap layers or the second p-type cap layers respectively
Vertically penetrate the first p-type cap layers or the second p-type cap layers；The N-type injection region be n-type doping AlGaN,
AlInN, AlScN, AlN, GaN, AlInGaN, AlInScN or AlGaScN layers, doped chemical Si, doping concentration is 1 × 1018
-1×1020 cm-3Between；
And/or the level interval between the first medium layer and first Source and drain metal level is 10nm-3 μm；Described second
Level interval between dielectric layer and second Source and drain metal level is 10nm-3 μm.
9. according to claim 1 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：The substrate is
One kind in silicon, sapphire, single-crystal silicon carbide substrate；
And/or the buffer layer is AlN, AlGaN or GaN layer.
10. according to claim 1 enhanced and depletion type GaN HEMT integrated morphologies, it is characterised in that：Described first
GaN channel layers, the 2nd GaN channel layers are the GaN single crystal layer that thickness is 1-500nm；
And/or first barrier layer, second barrier layer be thickness be 5-200nm AlGaN, AlInN, AlScN,
AlN, GaN, AlInGaN, AlInScN or AlGaScN layers.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277345A (en) * | 2019-05-15 | 2019-09-24 | 福建省福联集成电路有限公司 | A kind of manufacturing method and sensor of sensor |
| CN110752258A (en) * | 2019-11-13 | 2020-02-04 | 华南理工大学 | Normally-off HEMT device prepared by doping nano-hole gate and preparation method |
| CN112310208A (en) * | 2019-07-29 | 2021-02-02 | 华为技术有限公司 | Enhanced gallium nitride-based transistor, preparation method thereof and electronic device |
-
2018
- 2018-04-19 CN CN201820559173.0U patent/CN208028062U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277345A (en) * | 2019-05-15 | 2019-09-24 | 福建省福联集成电路有限公司 | A kind of manufacturing method and sensor of sensor |
| CN110277345B (en) * | 2019-05-15 | 2021-11-19 | 福建省福联集成电路有限公司 | Sensor manufacturing method and sensor |
| CN112310208A (en) * | 2019-07-29 | 2021-02-02 | 华为技术有限公司 | Enhanced gallium nitride-based transistor, preparation method thereof and electronic device |
| CN110752258A (en) * | 2019-11-13 | 2020-02-04 | 华南理工大学 | Normally-off HEMT device prepared by doping nano-hole gate and preparation method |
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