CN116504805A - High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof - Google Patents

High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof Download PDF

Info

Publication number
CN116504805A
CN116504805A CN202310275915.2A CN202310275915A CN116504805A CN 116504805 A CN116504805 A CN 116504805A CN 202310275915 A CN202310275915 A CN 202310275915A CN 116504805 A CN116504805 A CN 116504805A
Authority
CN
China
Prior art keywords
layer
gan
thickness
algan
electron mobility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310275915.2A
Other languages
Chinese (zh)
Inventor
程斌
白俊春
平加峰
汪福进
贾永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Xingang Semiconductor Co ltd
Original Assignee
Jiangsu Xingang Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Xingang Semiconductor Co ltd filed Critical Jiangsu Xingang Semiconductor Co ltd
Priority to CN202310275915.2A priority Critical patent/CN116504805A/en
Publication of CN116504805A publication Critical patent/CN116504805A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a high electron mobility transistor with a vertical AlGaN/GaN structure and a preparation method thereof, wherein the preparation method comprises the following steps: 1. growing epitaxial materials; 2. realizing a vertical structure; 3. manufacturing a drain electrode; 4. manufacturing a source electrode; 5. annealing ohmic metal; 6. manufacturing a gate electrode; 7. and finishing the manufacture of the interconnection leads. The method can solve the problems that the threshold voltage of the conventional GaN-based high electron mobility transistor device is smaller than 0 and the voltage withstand capability is poor.

Description

High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronic devices, relates to a high electron mobility transistor and a preparation method thereof, and particularly relates to a high electron mobility transistor with a vertical AlGaN/GaN structure and a preparation method thereof.
Background
The GaN material has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity and the like, so that the GaN material has unique advantages in the aspects of preparing high-voltage, high-temperature, high-power and high-density integrated electronic devices. The GaN material can form a heterojunction structure with AlGaN, inAlN and other materials. Since the barrier layer material such as AlGaN or InAlN has spontaneous polarization and piezoelectric polarization effects, a two-dimensional electron gas (2 DEG) having high concentration and high mobility is formed at the heterojunction interface. The characteristics can not only improve the carrier mobility and the working frequency of the GaN-based device, greatly improve the saturation current of the device and greatly increase the power of the device, but also reduce the on-resistance and the switching delay of the device.
The GaN-based HEMT (High Electron Mobility Transistor ) device has the characteristics of high breakdown characteristic, high switching speed, small on-resistance and the like, and has wide application prospects in the power electronic fields of power management, wind power generation, solar batteries, electric automobiles and the like. Compared with the traditional MOS device, the GaN-based HEMT device has higher switching speed and bears higher reverse voltage, can improve efficiency, reduce loss and save energy, and has huge market application prospect in the 600V-1200V device range. Moreover, the GaN material has the mutually perpendicular polar surface and nonpolar surface, and the device can generate 2DEG in the material structure direction of the polar surface and not generate 2DEG in the material structure direction of the nonpolar surface perpendicular to the polar surface through reasonably planning the material structure.
However, the current GaN-based HENT devices suffer from several drawbacks: 1. due to the polarization characteristics of the material, high-concentration two-dimensional electron gas exists at the heterojunction interface, so that the device is in a conducting state under zero grid bias, namely a depletion type device (normally open), and the circuit design is more complicated than that of an enhancement type device (normally closed), namely the difficulty and cost of the circuit design are increased. 2. From the safety point of view, especially for devices used in the high voltage field, the device is required to be in an off state when no voltage is applied, so that the whole circuit is prevented from being burnt out due to accidental conduction of the device, and even the danger of difficult prediction is caused. 3. For devices used in high voltage environments, the maximum sustainable voltage is required to be 2 times or even 3 times higher than the working voltage of the device, so that the device can be ensured to work stably and efficiently in complex application environments.
In view of the above-mentioned technical drawbacks of the prior art, there is a need to provide a novel high electron mobility transistor and a method for manufacturing the same, so as to overcome the above-mentioned drawbacks.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a high electron mobility transistor with a vertical AlGaN/GaN structure and a preparation method thereof, so as to solve the problems that the threshold voltage of the conventional GaN-based high electron mobility transistor device is smaller than 0 and the voltage withstand capability is poor.
In order to achieve the above object, the present invention provides the following technical solutions:
a method for fabricating a high electron mobility transistor having a vertical AlGaN/GaN structure, comprising the steps of:
1) In self-supporting N + -growing a C-doped GaN layer with a thickness of 3-30um on a GaN substrate;
2) Growing N with thickness of 1-3um on the C-doped GaN layer _ -a GaN transit layer;
3) Removing part of N by dry plasma etching _ -a GaN transit layer and the C-doped GaN layer underneath it to form two steps and a recess between the two steps;
4) Etching the two steps by dry plasma etching to remove part of the N of the steps _ -a GaN transit layer and a portion of the C-doped GaN layer located therebelow to form a stair step;
5) Integrally growing a GaN channel layer with the thickness of 200nm-500 nm;
6) Growing an AlGaN barrier layer with an Al component of 15-35% and a thickness of 10-30nm on the GaN channel layer to form an AlGaN/GaN structure;
7) In the self-supporting N + -depositing a drain electrode on the back side of the GaN substrate;
8) Removing the topmost AlGaN/GaN structure to expose the N_ -GaN transition layer, thereby forming a source window;
9) Depositing a source electrode over the source window;
10 Depositing a gate electrode on the AlGaN barrier layer above the step height;
11 And manufacturing interconnection leads.
Preferably, the GaN channel layer is a polar plane in a vertical direction and a nonpolar plane in a horizontal direction, and a side surface of the AlGaN barrier layer is a polar plane c-plane, so that the AlGaN/GaN structure has a two-dimensional electron gas in a vertical direction.
Preferably, the steps have a length of 10 μm to 15 μm and the distance between two steps is 20 μm to 30 μm.
Preferably, the step length is 1 μm to 3 μm or 5 μm to 8 μm.
Preferably, the drain electrode is formed by stacking a Ti layer, an Al layer, a Ni layer and an Au layer, wherein the Ti layer has a thickness of 20nm, the Al layer has a thickness of 160nm, the Ni layer has a thickness of 55nm, and the Au layer has a thickness of 45nm.
Preferably, the source electrode is formed by stacking a Ti layer, an Al layer, a Ni layer and Au, wherein the thickness of the Ti layer is 20nm, the thickness of the Al layer is 160nm, the thickness of the Ni layer is 55nm, and the thickness of the Au layer is 45nm.
Preferably, after step 9) is completed, a metal anneal is first performed, followed by step 10), wherein the metal anneal is N at 870 ℃ 2 The rapid thermal annealing was performed in an atmosphere for 30 seconds.
Preferably, the gate electrode is formed by stacking a Ni layer and an Au layer, wherein the thickness of the Ni layer is 45nm, and the thickness of the Au layer is 200nm.
Preferably, the interconnection lead is formed by stacking a Ti layer and an Au layer, the thickness of the Ti layer is 20nm, and the thickness of the Au layer is 200nm.
In addition, the invention also provides a high electron mobility transistor with a vertical AlGaN/GaN structure, which is characterized in that the transistor is prepared by adopting the preparation method.
Compared with the prior art, the high electron mobility transistor with the vertical AlGaN/GaN structure and the preparation method thereof have one or more of the following beneficial technical effects:
1. according to the invention, the vertical structure is realized, so that the current of the device can vertically circulate, the high breakdown characteristic of the GaN material is fully reflected, and meanwhile, the active area of the device is increased on the unit area, so that higher current density is realized.
2. The invention uses the difference between the perpendicular polar surface and the nonpolar surface of the GaN material, so that the side surface of the material is the polar surface c surface, two-dimensional electron gas (2 DEG) is generated in the vertical direction through the polarization effect, and the nonpolar surface is arranged on the upper layer, so that the 2DEG is not generated, the grid electrode prepared in the horizontal direction can not be in direct contact with the 2DEG, and the grid electrode voltage which is corrected is required to be applied when the channel is opened, thereby realizing the enhancement type work of the device.
3. Compared with a vertical GaN-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the structure of the invention realizes an AlGaN/GaN heterostructure through a regrowth technology, and generates 2DEG through polarization, so that the device can conduct electricity by utilizing the 2DEG, and compared with a bulk GaN material, the 2DEG has higher electron mobility, can obtain higher output current density, and meanwhile, the high-frequency characteristic of the device can not be degraded.
Drawings
FIG. 1 is a self-supporting N + -a schematic structural diagram of a GaN substrate.
Fig. 2 is a schematic structural view of the C-doped GaN layer grown on the basis of fig. 1.
FIG. 3 is a view of FIG. 2 with N grown thereon _ -schematic structural diagram after GaN transit layer.
Fig. 4 is a schematic view of the structure after forming steps on the basis of fig. 3.
Fig. 5 is a schematic view of the structure after forming the step on the basis of fig. 4.
Fig. 6 is a schematic structural view of the GaN channel layer grown on the basis of fig. 5.
Fig. 7 is a schematic structural diagram of the AlGaN barrier layer grown on the basis of fig. 6.
Fig. 8 is a schematic view of the structure after the drain electrode is deposited on the basis of fig. 7.
Fig. 9 is a schematic view of the structure after forming the source window on the basis of fig. 8.
Fig. 10 is a schematic view of the structure after the source electrode is deposited on the basis of fig. 9.
Fig. 11 is a schematic structural view of the gate electrode after deposition on the basis of fig. 10.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings, which are not to be construed as limiting the scope of the invention.
For power devices, it is critical to achieve enhanced and high voltage operation. From the standpoint of safety and energy consumption, it is necessary that no extra leakage occurs in the event of a power outage. The preparation of enhanced devices with superior performance is one research direction of great research value. The research of combining third-generation semiconductor GaN with enhancement is a great research from the application point of view. The so-called enhancement mode (E-mode) device (also called normally-off device), i.e. turned off in zero-bias state, does not need to apply negative voltage to turn off as depletion mode device does, and can greatly reduce the extra power loss of the circuit. The enhanced AlGaN/GaN HEMT is used in the fields of low voltage and high frequency, and for power switch application, the normally-off characteristic is a necessary condition for ensuring safe operation and simple gate driving configuration, and meanwhile, the use of an enhanced device can simplify the design of a circuit. It can be seen that to realize a GaN power device with good characteristics, it is necessary to simultaneously satisfy that the device is enhancement type and can withstand higher voltages, that is, to realize an enhancement type GaN HEMT device with high breakdown voltage. The vertical structure can fully exert the high breakdown characteristic of the GaN material, and is more beneficial to realizing a GaN-based device with high breakdown voltage; meanwhile, the heterostructure is combined to generate 2DEG, so that the vertical structure AlGaN/GaN high electron mobility transistor with high breakdown characteristic can be obtained; and then the polar surface and the nonpolar surface are separated, so that the lower part of the grid electrode of the device is contacted with the nonpolar surface which does not generate 2DEG, the enhancement work of the device is realized, and the AlGaN/GaN enhancement type high electron mobility transistor with the high breakdown characteristic and the vertical structure can be realized.
The invention provides a high electron mobility transistor with a vertical AlGaN/GaN structure and a preparation method thereof, and aims to solve the problems that a conventional HEMT device is a depletion type device and has lower breakdown voltage at present.
The preparation method of the high electron mobility transistor with the vertical AlGaN/GaN structure comprises the following steps:
1. as shown in fig. 1, a self-supporting N is provided + GaN substrate 1.
The self-supporting N + The GaN substrate 1 serves as a substrate layer of a high electron mobility transistor. Preferably, the self-supporting N + The GaN substrate 1 has a thickness of 1mm-2mm.
2. As shown in fig. 2, in the self-supporting N + Growing a C-doped GaN layer 2 with a thickness of 3-30um on the GaN substrate 1, wherein the doping concentration of C is 5-8X10 17 /cm 3 。
Because the GaN layer is a C-doped GaN layer, the introduced C-doping can introduce an electron trap energy level or an acceptor energy level in the GaN forbidden band, so that conduction band electrons are trapped by the electron trap or compensated by the acceptor, and a high-resistance GaN material is obtained. Therefore, in the invention, the C-doped GaN layer 2 is a high-resistance GaN layer, so that the C-doped GaN layer can inhibit the electric leakage of the substrate layer of the device and improve the breakdown voltage of the device.
3. As shown in FIG. 3, N with a thickness of 1-3um is grown on the C-doped GaN layer 2 _ A GaN transit layer 3.
4. As shown in fig. 4, a part of the N is removed by dry plasma etching _ A GaN transit layer 3 and said C-doped GaN layer 2 located thereunder to form two steps a and a recess b between said two steps a.
Preferably, the length of the step a is 10 μm to 15 μm, and the interval between the two steps a, that is, the length of the groove b is 20 μm to 30 μm.
5. As shown in fig. 5, the two steps a are etched by dry plasma etching, and a part of the n_ -GaN transit layer 3 of the step a and a part of the C-doped GaN layer 2 located thereunder are removed to form a stepped step C.
Preferably, the thickness of the removed portion of the C-doped GaN layer 2 is 1-2.5um.
More preferably, the step c has a length of 1 μm to 3 μm or 5 μm to 8 μm.
6. As shown in fig. 6, a GaN channel layer 4 having a thickness of 200nm to 500nm is grown as a whole.
Since the polar and nonpolar planes of the GaN material are themselves perpendicular to each other, the horizontal direction is naturally nonpolar when the vertical direction is a polar plane. In the invention, MOCVD can be used for growing the high-quality N-type GaN epitaxial layer, so that the N-type GaN epitaxial layer can be grown in the vertical direction, the two-dimensional quantum well formed by the N-type GaN epitaxial layer and the AlGaN barrier layer has lower hole injection barrier and better electron limiting capability, and the naturally nonpolar GaN epitaxial layer is grown in the horizontal direction.
Therefore, in the present invention, the GaN channel layer 4 is made to be a polar surface in the vertical direction and a nonpolar surface in the horizontal direction.
7. As shown in fig. 7, an AlGaN barrier layer 5 having an Al composition of 15 to 35% and a thickness of 10 to 30nm is grown on the GaN channel layer 4 to form an AlGaN/GaN structure.
In the present invention, the AlGaN/GaN structure is a heterostructure. The side surface of the AlGaN barrier layer 5 is a polar surface c-plane, so that the AlGaN/GaN structure has a two-dimensional electron gas d in the vertical direction. Meanwhile, since the horizontal direction of the GaN channel layer 4 is a nonpolar plane, there is no piezoelectric polarization effect, and thus, 2DEG is not generated in the horizontal direction.
8. As shown in fig. 8, in the self-supporting N + The drain electrode 6 is deposited on the back side of the GaN substrate 1.
In the present invention, the drain electrode 6 is preferably formed by laminating a Ti layer, an Al layer, a Ni layer, and Au layer. Wherein the thickness of the Ti layer is 20nm, the thickness of the Al layer is 160nm, the thickness of the Ni layer is 55nm, and the thickness of the Au layer is 45nm.
9. As shown in fig. 9, the topmost AlGaN/GaN structure is removed to expose the n_ -GaN transit layer 3, thereby forming a source window.
10. As shown in fig. 10, a source electrode 7 is deposited on the source window.
Preferably, the source electrode 7 is formed by stacking a Ti layer, an Al layer, a Ni layer, and an Au layer. Wherein the thickness of the Ti layer is 20nm, the thickness of the Al layer is 160nm, the thickness of the Ni layer is 55nm, and the thickness of the Au layer is 45nm.
In the present invention, after the deposition of the source electrode 7, a metal anneal is performed. Wherein the metal annealing is rapid thermal annealing performed in an N2 atmosphere at 870 ℃ for 30 seconds. The ohmic contact metal can be alloyed by the metal annealing treatment, thereby completing the fabrication of the source electrode and the drain electrode.
11. As shown in fig. 11, a gate electrode 8 is deposited on the AlGaN barrier layer 5 above the step c.
Preferably, the gate electrode 8 is formed by laminating a Ni layer and an Au layer. Wherein the thickness of the Ni layer is 45nm, and the thickness of the Au layer is 200nm.
12. And manufacturing interconnection leads.
After the deposition of the gate electrode 8, the interconnection leads are fabricated, thus completing the fabrication of the entire high electron mobility transistor having a vertical AlGaN/GaN structure.
Preferably, the interconnection leads are laminated by using Ti layers and Au layers. Wherein the thickness of the Ti layer is 20nm, and the thickness of the Au layer is 200nm.
The high electron mobility transistor having a vertical AlGaN/GaN structure and the method of manufacturing the same according to the present invention will be described in detail with several specific embodiments so that those skilled in the art can implement the present invention according to the description of the present invention.
[ embodiment one ]
The preparation method of the high electron mobility transistor with the vertical AlGaN/GaN structure of the embodiment comprises the following steps:
step 1. Epitaxial material growth
1.1 In self-supporting N) + -growing a high-resistance C-doped GaN layer with a thickness of 3-30 μm on a GaN substrate using an MOCVD process;
1.2 On the high-resistance C-doped GaN layer, N with thickness of 1-3 μm is grown by MOCVD process - -a GaN transit layer.
Step 2, realizing vertical structure
2.1 Primary step treatment
A photoresist throwing machine is adopted to throw photoresist at the rotating speed of 3500 revolutions per minute, and a photoresist mask is obtained; exposing by using an NSR1755I7A photoetching machine to form a window mask pattern of which only part of the N-GaN transition layer is reserved;
then the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 The plasma is etched at an etching rate of 1nm/s to remove the excess N - -a GaN transit layer and a high-resistance C-doped GaN layer.
Wherein the step length of the reserved N-GaN transition layer and the high-resistance C-doped GaN layer is 10 μm-15 μm, and the interval between the two steps is 20 μm-30 μm.
2.2 Step-wise step treatment
Throwing positive photoresist on the surface of an epitaxial material at a rotation speed of 5000 revolutions per minute, wherein the type of the photoresist is AZ6130, a photoresist mask with the thickness of 2.5 mu m is obtained, then the photoresist mask is baked in a high-temperature oven with the temperature of 80 ℃ for 10 minutes, and then a window mask pattern of a gate groove is obtained by photoetching by adopting an NSR1755I7A photoetching machine;
then, after development is completed, opening a window pattern on the N-GaN transition layer to be etched below the grid electrode, and protecting other places by using photoresist as a mask;
then the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 Etching the plasma at an etching rate of 1nm/s to remove the N-GaN transition layer below the grid electrode and etch away part of the high-resistance C-doped GaN layer;
wherein N is etched away - The length of the stepped steps of the GaN transit layer and the partially high-resistance C-doped GaN layer is 1 μm to 3 μm.
2.3 Realizing AlGaN/GaN heterostructure by regrowth
Firstly, growing a GaN channel layer with the thickness of 200nm-500nm on a substrate which is etched to form a step by adopting an MOCVD process;
and then growing an AlGaN barrier layer with an Al component of 15% and a thickness of 30nm on the substrate on which the GaN channel layer is grown.
Step 3, drain electrode fabrication
Carrying out drain ohmic metal deposition on the back of the material, adopting an ohm-50 electron beam evaporation table to manufacture a drain electrode at an evaporation rate of 0.1nm/s, and sequentially selecting Ti/Al/Ni/Au as the drain metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm;
step 4, manufacturing a source electrode
4.1 Source electrode window fabrication
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then baking for 10min in a high-temperature oven with the temperature of 80 ℃, exposing by adopting an NSR1755I7A photoetching machine, exposing the AlGaN/GaN heterostructure of which the source is to be realized on the topmost layer, and protecting the rest parts;
finally, the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 The plasma is etched at an etching rate of 1nm/s, and is exposed to the outside after the photoetchingThe source electrode window is formed by the AlGaN/GaN heterostructure.
4.2 Source electrode deposition
Firstly, throwing photoresist on the front surface of a vertical structure substrate of a stepped step of an AlGaN/GaN heterostructure with a source window of a drain electrode, wherein the front surface of the vertical structure substrate is provided with the stepped step, and the photoresist is thrown at a rotating speed of 5000 revolutions per minute by adopting a photoresist throwing machine, so that the thickness of a photoresist mask is 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a source region mask pattern;
then, adopting an ohm-50 electron beam evaporation table to manufacture a source electrode at an evaporation rate of 0.1nm/s, wherein Ti/Al/Ni/Au is sequentially selected as source metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm; and (5) metal stripping is carried out after the source ohmic contact metal evaporation is completed, so that a complete source electrode is obtained.
Step 5 ohmic Metal annealing
N at 870℃using RTP500 rapid thermal annealing furnace 2 And (3) performing rapid thermal annealing for 30 seconds in the atmosphere, and alloying ohmic contact metal to finish the manufacture of source and drain electrodes.
Step 6, manufacturing the gate electrode
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a grid region mask pattern;
finally, evaporating gate metal by an ohm-50 electron beam evaporation table at an evaporation rate of 0.1nm/s, wherein the gate metal sequentially adopts Ni/Au, the thickness of Ni is 45nm, and the thickness of Au is 200nm; and (5) metal stripping is carried out after evaporation is completed, so that a complete gate electrode is obtained.
And 7, completing the manufacture of the interconnection leads.
Firstly, spin positive photoresist at a rotation speed of 5000 rpm by using a spin coater; exposing by using an NSR1755I7A photoetching machine to form an electrode lead mask pattern; then, an ohm Iker-50 electron beam evaporation table is adopted to carry out lead electrode metal evaporation on the substrate with the mask manufactured at the evaporation rate of 0.3nm/s, wherein the thickness of Ti is 20nm, and the thickness of Au is 200nm; and finally, stripping after the metal of the lead electrode is evaporated, so as to obtain the complete lead electrode.
[ example two ]
The preparation method of the high electron mobility transistor with the vertical AlGaN/GaN structure of the embodiment comprises the following steps:
step 1. Epitaxial material growth
1.1 In self-supporting N) + -growing a high-resistance C-doped GaN layer of 3-30 μm on a GaN substrate material using an MOCVD process;
1.2 On the high-resistance C-doped GaN layer, 1-3 μm N is grown by MOCVD process - -a GaN transit layer.
Step 2, realizing vertical structure
2.1 Primary step treatment
A photoresist throwing machine is adopted to throw photoresist at the rotating speed of 3500 revolutions per minute, and a photoresist mask is obtained; exposing with NSR1755I7A photoetching machine to form N only - -a window mask pattern of a GaN transit layer;
then the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 The plasma is etched at an etching rate of 1nm/s to remove the excess N - -a GaN transit layer and a high-resistance C-doped GaN layer;
wherein, reserved N - The step length of the GaN transit layer and the high-resistance C-doped GaN layer is 10 μm to 15 μm, while the spacing between the two preliminary steps is 20 μm to 30 μm.
2.2 Step-wise step treatment
Throwing positive photoresist on the surface of an epitaxial material at a rotation speed of 5000 revolutions per minute, wherein the type of the photoresist is AZ6130, a photoresist mask with the thickness of 2.5 mu m is obtained, then the photoresist mask is baked in a high-temperature oven with the temperature of 80 ℃ for 10 minutes, and then a window mask pattern of a gate groove is obtained by photoetching by adopting an NSR1755I7A photoetching machine;
then, after development is completed, opening a window pattern on the N-GaN transition layer to be etched below the grid electrode, and protecting other places by using photoresist as a mask;
then the substrate with the mask pattern is etched by an ICP98c type inductively coupled plasma etching machine in Cl2 plasma at the etching rate of 1nm/s to remove N below the grid electrode - -a GaN transit layer and etching away part of the highly resistive C-doped GaN layer;
wherein N is etched away - The length of the stepped steps of the GaN transit layer and the partially high-resistance C-doped GaN layer is 5 μm to 8 μm.
2.3 Realizing AlGaN/GaN heterostructure by regrowth
Firstly, growing a GaN channel layer with the thickness of 200nm-500nm on a substrate which is etched to form a step by adopting an MOCVD process;
then growing an AlGaN barrier layer with the Al component of 25% and the thickness of 20nm on the substrate on which the GaN channel layer is grown;
step 3, drain electrode fabrication
And carrying out drain ohmic metal deposition on the back of the material, and adopting an ohm-50 electron beam evaporation table to manufacture a drain electrode at an evaporation rate of 0.1nm/s, wherein Ti/Al/Ni/Au is sequentially selected as the drain metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm.
Step 4, manufacturing a source electrode
4.1 Source electrode window fabrication
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then baking for 10min in a high-temperature oven with the temperature of 80 ℃, exposing by adopting an NSR1755I7A photoetching machine, exposing the AlGaN/GaN heterostructure of which the source is to be realized on the topmost layer, and protecting the rest parts;
finally, the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 And etching the plasma at an etching rate of 1nm/s, and removing the exposed AlGaN/GaN heterostructure after photoetching to form a source electrode window.
4.2 Source electrode deposition
Firstly, throwing photoresist on the front surface of a vertical structure substrate of a stepped step of an AlGaN/GaN heterostructure with a source window of a drain electrode, wherein the front surface of the vertical structure substrate is provided with the stepped step, and the photoresist is thrown at a rotating speed of 5000 revolutions per minute by adopting a photoresist throwing machine, so that the thickness of a photoresist mask is 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a source region mask pattern;
then, adopting an ohm-50 electron beam evaporation table to manufacture a source electrode at an evaporation rate of 0.1nm/s, wherein Ti/Al/Ni/Au is sequentially selected as source metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm; and (5) metal stripping is carried out after the source ohmic contact metal evaporation is completed, so that a complete source electrode is obtained.
Step 5 ohmic Metal annealing
N at 870℃using RTP500 rapid thermal annealing furnace 2 And (3) performing rapid thermal annealing for 30 seconds in the atmosphere, and alloying the ohmic contact metal to finish the manufacture of the source electrode and the drain electrode.
Step 6, manufacturing the gate electrode
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a grid region mask pattern;
finally, evaporating gate metal by an ohm-50 electron beam evaporation table at an evaporation rate of 0.1nm/s, wherein the gate metal sequentially adopts Ni/Au, the thickness of Ni is 45nm, and the thickness of Au is 200nm; and (5) metal stripping is carried out after evaporation is completed, so that a complete gate electrode is obtained.
And 7, completing the manufacture of the interconnection leads.
Firstly, spin positive photoresist at a rotation speed of 5000 rpm by using a spin coater; exposing by using an NSR1755I7A photoetching machine to form an electrode lead mask pattern; then, an ohm Iker-50 electron beam evaporation table is adopted to carry out lead electrode metal evaporation on the substrate with the mask manufactured at the evaporation rate of 0.3nm/s, wherein the thickness of Ti is 20nm, and the thickness of Au is 200nm; and finally, stripping after the metal of the lead electrode is evaporated, so as to obtain the complete lead electrode.
[ example III ]
The preparation method of the high electron mobility transistor with the vertical AlGaN/GaN structure of the embodiment comprises the following steps:
step 1. Epitaxial material growth
1.1 In self-supporting N) + -growing a high-resistance C-doped GaN layer of 3-30 μm on a GaN substrate material using an MOCVD process;
1.2 On the high-resistance C-doped GaN layer, 1-3 μm N is grown by MOCVD process - -a GaN transit layer.
Step 2, realizing vertical structure
2.1 Primary step treatment
A photoresist throwing machine is adopted to throw photoresist at the rotating speed of 3500 revolutions per minute, and a photoresist mask is obtained; exposing with NSR1755I7A photoetching machine to form N only - -a window mask pattern of a GaN transit layer;
then the substrate with the mask pattern is etched by an ICP98c type inductively coupled plasma etching machine in Cl2 plasma at the etching rate of 1nm/s to remove redundant N - -a GaN transit layer and a high-resistance C-doped GaN layer;
wherein, reserved N - The step length of the GaN transit layer and the high-resistance C-doped GaN layer is 10 μm to 15 μm, while the spacing between the two preliminary steps is 20 μm to 30 μm.
2.2 Step-wise step treatment
Throwing positive photoresist on the surface of an epitaxial material at a rotation speed of 5000 revolutions per minute, wherein the type of the photoresist is AZ6130, a photoresist mask with the thickness of 2.5 mu m is obtained, then the photoresist mask is baked in a high-temperature oven with the temperature of 80 ℃ for 10 minutes, and then a window mask pattern of a gate groove is obtained by photoetching by adopting an NSR1755I7A photoetching machine;
then, after the development is completed, N needing to be etched below the grid electrode - The GaN transition layer opens a window pattern, and the rest is protected by using the photoresist as a mask;
then the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 The plasma is etched at an etching rate of 1nm/s to remove the under-gateSquare N - -a GaN transit layer and etching away part of the highly resistive C-doped GaN layer;
wherein N is etched away - The length of the stepped steps of the GaN transit layer and the partially high-resistance C-doped GaN layer is 5 μm to 8 μm.
2.3 Realizing AlGaN/GaN heterostructure by regrowth
Firstly, growing a GaN channel layer with the thickness of 200nm-500nm on a substrate which is etched to form a step by adopting an MOCVD process;
and then growing an AlGaN barrier layer with the Al component of 35% and the thickness of 10nm on the substrate on which the GaN channel layer is grown.
Step 3, drain electrode fabrication
And carrying out drain ohmic metal deposition on the back of the material, and adopting an ohm-50 electron beam evaporation table to manufacture a drain electrode at an evaporation rate of 0.1nm/s, wherein Ti/Al/Ni/Au is sequentially selected as the drain metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm.
Step 4, manufacturing a source electrode
4.1 Source electrode window fabrication
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then baking for 10min in a high-temperature oven with the temperature of 80 ℃, exposing by adopting an NSR1755I7A photoetching machine, exposing the AlGaN/GaN heterostructure of which the source is to be realized on the topmost layer, and protecting the rest parts;
finally, the substrate with the mask pattern is etched in Cl by an ICP98c type inductively coupled plasma etching machine 2 Etching the plasma at an etching rate of 1nm/s, and removing the exposed AlGaN/GaN heterostructure after photoetching to form a source electrode window;
4.2 Source electrode deposition
Firstly, throwing photoresist on the front surface of a vertical structure substrate of a stepped step of an AlGaN/GaN heterostructure with a source window of a drain electrode, wherein the front surface of the vertical structure substrate is provided with the stepped step, and the photoresist is thrown at a rotating speed of 5000 revolutions per minute by adopting a photoresist throwing machine, so that the thickness of a photoresist mask is 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a source region mask pattern;
then, adopting an ohm-50 electron beam evaporation table to manufacture a source electrode at an evaporation rate of 0.1nm/s, wherein Ti/Al/Ni/Au is sequentially selected as source metal, wherein the thickness of Ti is 20nm, the thickness of Al is 160nm, the thickness of Ni is 55nm and the thickness of Au is 45nm; and (5) metal stripping is carried out after the source ohmic contact metal evaporation is completed, so that a complete source electrode is obtained.
Step 5 ohmic Metal annealing
Finally, the rapid thermal annealing furnace is further utilized by RTP500, and N is at 870 DEG C 2 And (3) performing rapid thermal annealing for 30 seconds in the atmosphere, and alloying the ohmic contact metal to finish the manufacture of the source electrode and the drain electrode.
Step 6, manufacturing the gate electrode
Firstly, spin coating is carried out by a spin coater at a rotation speed of 5000 revolutions per minute to obtain a photoresist mask with a thickness of 0.8 mu m;
then, baking for 10min in a high-temperature oven with the temperature of 80 ℃, and exposing by adopting an NSR1755I7A photoetching machine to form a grid region mask pattern;
finally, evaporating gate metal by an ohm-50 electron beam evaporation table at an evaporation rate of 0.1nm/s, wherein the gate metal sequentially adopts Ni/Au, the thickness of Ni is 45nm, and the thickness of Au is 200nm; and (5) metal stripping is carried out after evaporation is completed, so that a complete gate electrode is obtained.
And 7, completing the manufacture of the interconnection leads.
Firstly, spin positive photoresist at a rotation speed of 5000 rpm by using a spin coater; exposing by using an NSR1755I7A photoetching machine to form an electrode lead mask pattern; then, an ohm Iker-50 electron beam evaporation table is adopted to carry out lead electrode metal evaporation on the substrate with the mask manufactured at the evaporation rate of 0.3nm/s, wherein the thickness of Ti is 20nm, and the thickness of Au is 200nm; and finally, stripping after the metal of the lead electrode is evaporated, so as to obtain the complete lead electrode.
The high electron mobility transistor with the vertical AlGaN/GaN structure and the preparation method thereof can solve the problems that the threshold voltage of the conventional GaN-based HEMT device is smaller than 0 and the voltage withstand capability is poor.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and are not intended to limit the scope of the present invention. Modifications and equivalent substitutions can be made by those skilled in the art based on the present teachings without departing from the spirit and scope of the present teachings.

Claims (10)

1. A method for fabricating a high electron mobility transistor having a vertical AlGaN/GaN structure, comprising the steps of:
1) In self-supporting N + -growing a C-doped GaN layer (2) with a thickness of 3-30um on a GaN substrate (1);
2) Growing N with thickness of 1-3um on the C-doped GaN layer (2) _ -a GaN transit layer (3);
3) Removing part of N by dry plasma etching _ -a GaN transit layer (3) and the C-doped GaN layer (2) underneath it to form two steps (a) and a recess (b) between the two steps (a);
4) Etching the two steps (a) by dry plasma etching to remove part of the N of the steps (a) _ -a GaN transit layer (3) and a portion of said C-doped GaN layer (2) located therebelow to form a step (C);
5) A GaN channel layer (4) with the thickness of 200nm-500nm is integrally grown;
6) Growing an AlGaN barrier layer (5) with an Al component of 15-35% and a thickness of 10-30nm on the GaN channel layer (4) to form an AlGaN/GaN structure;
7) In the self-supporting N + -depositing a drain electrode (6) on the back side of the GaN substrate (1);
8) Removing the topmost AlGaN/GaN structure to expose the N _ -a GaN transit layer (3) forming a source window;
9) -depositing a source electrode (7) on the source window;
10 -depositing a gate electrode (8) on the AlGaN barrier layer (5) above the step (c);
11 And manufacturing interconnection leads.
2. The method of manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein the GaN channel layer (4) is a polar plane in a vertical direction and a nonpolar plane in a horizontal direction, and the AlGaN barrier layer (5) has a side surface of a polar plane c-plane, so that the AlGaN/GaN structure has a two-dimensional electron gas (d) in a vertical direction.
3. The method for manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein the step (a) has a length of 10 μm to 15 μm,
the distance between the two steps (a) is 20 μm to 30 μm.
4. The method of manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein the length of said step (c) is 1 μm to 3 μm or 5 μm to 8 μm.
5. The method for manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein said drain electrode (6) is formed by stacking a Ti layer, an Al layer, a Ni layer and an Au layer, wherein the thickness of said Ti layer is 20nm, the thickness of said Al layer is 160nm, the thickness of said Ni layer is 55nm, and the thickness of said Au layer is 45nm.
6. The method for manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein said source electrode (7) is formed by stacking a Ti layer, an Al layer, a Ni layer and an Au layer, wherein the Ti layer has a thickness of 20nm, the Al layer has a thickness of 160nm, the Ni layer has a thickness of 55nm, and the Au layer has a thickness of 45nm.
7. The high electron mobility with vertical AlGaN/GaN structure according to claim 1A method for producing a rate transistor, characterized in that after step 9) is completed, a metal anneal is first performed, followed by step 10), wherein the metal anneal is N at 870 DEG C 2 The rapid thermal annealing was performed in an atmosphere for 30 seconds.
8. The method for manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein said gate electrode (8) is formed by laminating a Ni layer and an Au layer, wherein the thickness of said Ni layer is 45nm and the thickness of said Au layer is 200nm.
9. The method for manufacturing a high electron mobility transistor having a vertical AlGaN/GaN structure according to claim 1, wherein said interconnection lead is formed by stacking a Ti layer and Au layer, said Ti layer having a thickness of 20nm and said Au layer having a thickness of 200nm.
10. A high electron mobility transistor having a vertical AlGaN/GaN structure, which is prepared by the preparation method according to any one of claims 1 to 9.
CN202310275915.2A 2023-03-21 2023-03-21 High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof Pending CN116504805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310275915.2A CN116504805A (en) 2023-03-21 2023-03-21 High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310275915.2A CN116504805A (en) 2023-03-21 2023-03-21 High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116504805A true CN116504805A (en) 2023-07-28

Family

ID=87327493

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310275915.2A Pending CN116504805A (en) 2023-03-21 2023-03-21 High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116504805A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978943A (en) * 2023-09-14 2023-10-31 广东致能科技有限公司 Enhanced semiconductor device and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116978943A (en) * 2023-09-14 2023-10-31 广东致能科技有限公司 Enhanced semiconductor device and preparation method thereof
CN116978943B (en) * 2023-09-14 2024-01-30 广东致能科技有限公司 Enhanced semiconductor device and preparation method thereof

Similar Documents

Publication Publication Date Title
CN108962977B (en) SBD (silicon carbide) -integrated silicon carbide trench MOSFETs (metal-oxide-semiconductor field effect transistors) and preparation method thereof
CN109004017B (en) HEMT device with polarization junction longitudinal leakage current barrier layer structure and preparation method thereof
CN106158923A (en) Enhancement mode GaN FinFET based on many two dimension raceway grooves
CN109950323B (en) Polarized superjunction III-nitride diode device and manufacturing method thereof
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN113013242A (en) P-channel GaN-based heterojunction field effect transistor based on n-GaN gate
CN113113469A (en) High-voltage-resistance double-gate transverse HEMT device and preparation method thereof
CN111081763B (en) Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof
WO2019242100A1 (en) Gallium oxide semiconductor electronic device with vertical structure and manufacturing method therefor
CN116504805A (en) High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof
US20210384345A1 (en) Vertical umosfet device with high channel mobility and preparation method thereof
CN104659082A (en) AlGaN/GaN HEMT device with vertical structure and method for manufacturing device
CN113555429A (en) Normally-on HFET device with high breakdown voltage and low on-resistance and preparation method thereof
CN210897283U (en) Semiconductor device with a plurality of transistors
CN205564759U (en) Novel enhancement mode III -V heterojunction field effect transistor
CN111509042A (en) MIS structure GaN high electron mobility transistor and preparation method thereof
CN105826369A (en) Novel enhanced III-V heterojunction field effect transistor
CN115692184A (en) P-AlGaN gate enhancement transistor based on selective wet etching process and preparation method
CN115458596A (en) HEMT based on Fin-JFET gate structure and manufacturing method thereof
CN112909076B (en) Mixed Schottky barrier diode structure with P-type nickel oxide material
CN110676166B (en) FinFET enhanced device with P-GaN cap layer and manufacturing method thereof
CN113659013A (en) Schottky diode with p-type oxide dielectric composite mixed anode and manufacturing method thereof
CN116092936A (en) Insulated gate high electron mobility transistor and preparation method thereof
CN111415998A (en) GaN-based Schottky diode and preparation method thereof
CN205911315U (en) GaN base schottky diode who mixes positive pole electrode structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination