CN105826369A - Novel enhanced III-V heterojunction field effect transistor - Google Patents
Novel enhanced III-V heterojunction field effect transistor Download PDFInfo
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- 230000005669 field effect Effects 0.000 title abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims abstract description 25
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000012010 growth Effects 0.000 claims description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000010287 polarization Effects 0.000 description 5
- 230000002269 spontaneous effect Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 125000005842 heteroatom Chemical group 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000003698 anagen phase Effects 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention provides a novel enhanced III-V heterojunction field effect transistor. The novel enhanced III-V heterojunction field effect transistor is characterized in that a second semiconductor layer is formed on a substrate material layer; a drain electrode and a source electrode are formed on the second semiconductor layer; the drain electrode and the source electrode are connected through a first semiconductor layer, and a channel is formed between the drain electrode and the source electrode through ohmic contact with the first semiconductor layer; the first semiconductor layer has a forbidden band width which is greater than the forbidden band width of the second semiconductor layer; the second semiconductor layer and the first semiconductor layer are combined together to form a heterostructure; and the thickness of the first semiconductor layer is less than or equal to the critical thickness of two-dimensional electron gas 2DEG in the heterostructure so as to exhaust the natural two-dimensional electron gas 2DEG in the heterostructure. Compared with the prior art, the novel enhanced III-V heterojunction field effect transistor utilizes the thin barrier layer scheme to obtain the exhausted channel, and utilizes the high gate voltage to re-induce the 2DEG, so that the enhanced device with stable performance can be realized.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of novel enhancement type III-V hetero-junctions
Field-effect transistor.
Background technology
Binary or ternary compound (even multi-element compounds) that some III and V group element are constituted have
There is piezoelectricity and spontaneous polarization effect, when they combine composition hetero-junctions (as
AlGaN/GaN), the two-dimensional electron gas (2DEG) of high concentration can be formed in the interface of hetero-junctions, with
2DEG at heterojunction boundary is that the device of conductive mechanism is referred to as hetero junction field effect pipe (HFET), also
It is properly termed as HEMT (HEMT).
HFET device has that high electron mobility, device operating frequencies be high and high efficiency feature.Micro-
The transmission of wave power emitter stage and field of power electronics have very important application prospect.But, so far
Till, as there is a natural shortcoming in HFET device, with AlGaN/GaN during enhancement device
As a example by HFET, due to extremely strong piezoelectricity and spontaneous polarization, in the case of without any applied voltage,
Heterojunction boundary defines the 2DEG of high concentration, and HFET device is natural for depletion type (open type).HFET
The device application in logic circuit and Power Electronic Circuit of the drawbacks limit of device, the former needs to strengthen
Type and the logical complement of depletion type, and the latter is for safety and energy-conservation consideration, it can be more desirable to strengthen
Type device.Refering to Fig. 1, it show the sectional view of prior art depletion type III-V HFET device, comprise
Substrate material layer 9, the second semiconductor layer 10, the first semiconductor layer 14, two-dimensional electron gas 11, electric leakage
Pole 12, source electrode 13, gate dielectric layer 15 and gate electrode 16, wherein, the second semiconductor layer 10 and
Heterojunction structure is constituted, due to the thickness of the first semiconductor layer 14 in prior art between semi-conductor layer 14
Exceed critical thickness, so in the case of being not added with any applied voltage, due to the piezoelectricity pole of material system
Change and spontaneous polarization, in heterojunction boundary, the i.e. first quasiconductor and the interface of the second quasiconductor, i.e. deposit
Two-dimensional electron gas 2DEG in high concentration.
Prior art, in order to realize enhancement mode HFET device, generally has following several ways to obtain:
Grid lower channel F ion injection technique: inject the anion of F the most under the gate in the barrier layer in portion, lean on
Channel electrons under grid is exhausted by negative potential, it is achieved the positive threshold (enhancement mode) of device.
Groove gate technique: with dry etching technology by unkind for grid lower part barrier layer, when thickness is less than critical thickness
Time, the 2DEG under grid will exhaust.Only when grid voltage is higher than a certain voltage, just can again induce
2DEG.Achieve enhancement device.
Utilizing the device of P-AlGaN layer, this device is to add one layer of p-AlGaN layer in grid lower portion,
Due to the proportionality action that can carry, the 2DEG of raceway groove is made to exhaust.
There is different inferior positions in the most several technology, wherein F ion injection technique in reliability and obtains bigger
Threshold value aspect existing problems, in terms of technology controlling and process, there is bigger difficulty, P-AlGaN skill in groove gate technique
There is the shortcomings such as Material growth is difficult, devices switch frequency is low in art.
Therefore, for drawbacks described above present in currently available technology, it is necessary to study, to provide one in fact
The scheme of kind, solves defect present in prior art.
Summary of the invention
In view of this, it is an object of the invention to provide a kind of novel enhancement type III-V hetero junction field effect brilliant
Body pipe, to solve the problems referred to above.
A kind of novel enhancement type III-V HFET, including substrate material layer, the second half leads
Body layer, the first semiconductor layer, drain electrode, source electrode, first medium layer, second dielectric layer and gate electrode,
Wherein,
Described substrate material layer forms described second semiconductor layer, structure on described second semiconductor layer
Produce drain electrode and source electrode, between described drain electrode and source electrode by the first semiconductor layer be connected and with
First semiconductor layer Ohmic contact thus form raceway groove；Described first semiconductor layer is than described second quasiconductor
Layer has bigger energy gap；
Described second semiconductor layer and described first semiconductor layer combine composition heterojunction structure；Described
The thickness of the first semiconductor layer is not more than the critical thickness forming two-dimensional electron gas 2DEG on heterojunction structure,
Make two-dimensional electron gas 2DEG natural in described heterojunction structure depleted；
Described first semiconductor layer surface is additionally provided with first medium layer, and described first medium layer is provided with described
Gate electrode, described gate electrode covers two edges extensions of whole channel length and described gate electrode and surpasses respectively
Cross described drain electrode and the source electrode edge near raceway groove side, described gate electrode and described drain electrode,
Described second dielectric layer it is provided with between source electrode.
Preferably, described second dielectric layer is only located at described gate electrode and described drain electrode and the friendship of source electrode
Marginal portion repeatedly.
Preferably, it is additionally provided with to improve hetero-junctions between described first semiconductor layer and the second semiconductor layer
The interposed layer of the mobility of the two-dimensional electron gas at interface, the thickness of described interposed layer is 1nm.
Preferably, described interposed layer is AlN layer.
Preferably, described first semiconductor layer is AlGaN layer, and its thickness is 3～10nm；Described second
Semiconductor layer is GaN layer, and its thickness is 2 μm.
Preferably, described first semiconductor layer is AlN layer, and its thickness is 5nm；Described second quasiconductor
Layer is GaN layer, and its thickness is 2 μm.
Preferably, the Si of growth in situ when described first medium layer is growth heterogeneous structure material3N4, it is thick
Degree is 5～25nm.
Preferably, between described gate electrode and first medium layer, it is additionally provided with the 3rd dielectric layer, the described 3rd
Dielectric layer is for reducing the grid leakage current of device further.
Preferably, described second dielectric layer is SiO2Layer, its thickness is 100nm.
Preferably, described second dielectric layer exceeds described drain electrode, source electricity respectively towards raceway groove one lateral edges
The length of pole is 0.5 μm.
Preferably, the distance between described drain electrode and described source electrode is 2.5 μm.
Relative to prior art, the novel enhancement type III-V HFET that the present invention provides,
Utilize thin barrier layer scheme to obtain the raceway groove exhausted, and use MIS grid structure, use high gate voltage again
Induce 2DEG, thus realize the enhancement device of stable performance.
Accompanying drawing explanation
Fig. 1 is the generalized section of prior art routine enhancement mode III-V HFET device.
Fig. 2 is the generalized section of novel enhancement type III-V HFET of the present invention.
Fig. 3 is the top view of novel enhancement type III-V HFET of the present invention.
Label declaration:
Substrate material layer 1, the second semiconductor layer 2, the first semiconductor layer 3, drain electrode 4, source electrode 5,
First medium layer 6, second dielectric layer 7, gate electrode 8.
Detailed description of the invention
The following is the specific embodiment of the present invention and combine accompanying drawing, technical scheme is made further
Describe, but the present invention is not limited to these embodiments.
The defect existed for prior art, the structure of HFET device in prior art is carried out by applicant
In-depth study, it has been found that the barrier layer of conventional device, the thickness of the i.e. first semiconductor layer exceedes
Critical thickness, so in the case of being not added with any applied voltage, due to material system piezoelectric polarization and
, in heterojunction boundary, the i.e. first quasiconductor and the interface of the second quasiconductor, i.e. there is height in spontaneous polarization
The two-dimensional electron gas 2DEG of concentration.Want to obtain enhancement device, it is necessary to use groove grid, F ion to inject
The special process such as doping.There is the shortcoming being difficult to accurately control and additionally extending process cycle in these technique,
It addition, slot grid structure is due to etching technics to be used in technical process, be there is damage in device channel, because of
This, the performance for device has damage, it addition, there is also certain hidden danger in terms of the reliability of device.F
Injection technology is difficult to be accurately controlled, and there is hidden danger in terms of reliability.
In order to overcome disadvantage mentioned above, the present invention proposes a kind of novel enhancement type III-V hetero junction field effect crystal
Pipe, sees shown in Fig. 2 and Fig. 3, and wherein Fig. 2 is the profile of device, and Fig. 3 is its top view, bag
Include substrate material layer the 1, second semiconductor layer the 2, first semiconductor layer 3, drain electrode 4, source electrode 5,
One dielectric layer 6, second dielectric layer 7 and gate electrode 8, wherein,
Substrate material layer 1 is formed the second semiconductor layer 2, the second semiconductor layer 2 constructs electric leakage
Pole 4 and source electrode 5, be connected and with first by the first semiconductor layer 3 between drain electrode 4 and source electrode 5
Semiconductor layer 3 Ohmic contact thus form raceway groove；First semiconductor layer 3 to the second semiconductor layer 2 has
Bigger energy gap；
Second semiconductor layer 2 and the first semiconductor layer 3 combine composition heterojunction structure；The first half lead
The thickness of body layer 3 is not more than the critical thickness forming two-dimensional electron gas 2DEG on heterojunction structure, makes the
Two-dimensional electron gas 2DEG natural in semi-conductor layer 3 heterojunction structure is depleted；By the of thin structure
The design of semi-conductor layer, owing to the thickness of the first semiconductor layer is less than critical thickness, eliminates heterogeneous
The two-dimensional electron gas 2DEG of high concentration is naturally occurred in structure, therefore, in the case of without additional grid voltage,
There is not 2DEG in the heterogeneous interface of the first semiconductor layer and the second semiconductor layer, only exceedes when additional grid voltage
A certain positive threshold voltage, could induce the 2DEG of high concentration in channels, it is achieved thereby that enhancement mode shape
State；Thus enormously simplify the technique forming enhancement device.
First semiconductor layer 3 surface is additionally provided with first medium layer 6, and first medium layer 6 is provided with gate electrode 8,
Gate electrode 8 covers two edges extensions of whole channel length and gate electrode 8 and exceedes drain electrode 4 He respectively
Source electrode 5, near the edge of raceway groove side, is provided with between gate electrode 8 and drain electrode 4, source electrode 5
Second medium layer 7.Due to the channel structure using gate electrode to be completely covered, it is achieved that gate voltage is for raceway groove
The control completely of 2DEG, thus realize the device of no current pull-in effect.
In a preferred embodiment, second dielectric layer 7 is only located at gate electrode 8 and drain electrode 4 and source
The marginal portion of the crossover of electrode 5.The purpose of second dielectric layer 7 is to stop gate electrode 8 and electric leakage
Pole 4 and the electric connection of source electrode 5, but gate capacitance can be impacted again by second dielectric layer 7, Jin Erying
Ring grid-control ability and amplifying power.This structure makes second dielectric layer 7 only covering grid electrode 8 and drain electrode 4
With the marginal portion of the crossover of source electrode 5, it is completely covered compared with first medium layer with second dielectric layer,
On the premise of realizing good electrical isolation, it is possible to ensure bigger gate capacitance, there is bigger device transconductance,
Device is made to have bigger grid-control ability and amplifying power.Preferably, the thickness of second dielectric layer should be tried one's best
Little.So, below the orthographic projection of grid, second dielectric layer is considerably less, makes the minimizing of gate capacitance drop to
Low.
Meanwhile, novel enhancement type III-V HFET of the present invention realize technique and existing skill
The technique of art HFET device is essentially identical, it is not necessary to the extra complex process degree increasing device.The present invention
Device can be realized by following main technological steps: (1) substrate material grow: in suitable substrate material
Upper (such as Si substrate), answers cushion, the second semiconductor layer, selection according to Material growth rule growth phase
Property growth interposed layer, the first semiconductor layer, in situ Si3N4Layer.(2) substrate material cleans: uses and closes
Suitable cleaning program, it is thus achieved that clean material surface.(3) source-drain electrode structure.(3) second medium
Layer growth.(4) second gate dielectric layer constituency etching.(5) gate electrode structure.(6) it is passivated and encapsulates.
Therefore, use technique scheme, the most extra complex process degree increasing device, threshold value electricity
Pressure can set by arranging the parameter such as the first layer semiconductor thickness and first medium layer thickness, it is achieved that device
The commercial production of the repeatability of technique, beneficially device.
Embodiment 1: the present embodiment novel enhancement type III-V HFET includes following a few portion
Point: backing material comprises Si material and the low temperature AI N cushion grown thereon, the second semiconductor layer
For GaN material layer (thickness is about 2 μm), the first semiconductor layer is that (thickness is about 3～10 to AlGaN layer
Nm), between the first and second semiconductor layers, it is provided with AlN interposed layer (thickness is about 1nm), is used for
Improve the electrology characteristic of 2DEG.First medium layer is growth in situ Si3N4Layer, thickness is about 5～25nm.
Source, drain electrode all use Ti/Al/Ni/Au (20/120/50/200nm) through Metal deposition and high-temperature thermal annealing shape
Become.Distance between source-drain electrode is 2.5 μm.Second dielectric layer is SiO2Layer, its thickness is about 100nm.
Second dielectric layer is all 0.5 μm towards one layer of edge of channel center beyond source, the length of drain electrode.Grid electricity
Pole uses Ni/Au (50/150nm).
Embodiment 2: the present embodiment novel enhancement type III-V HFET includes following a few portion
Point: backing material comprises SiC material and the low temperature AI N cushion grown thereon, the second semiconductor layer
For GaN material layer (thickness is about 2 μm), the first semiconductor layer is AlN layer (thickness is about 5nm),
First medium layer is growth in situ Si3N4Layer, thickness is about 5～25nm.Source, drain electrode all use
Ti/Al/Ni/Au (20/120/50/200nm) is formed with high-temperature thermal annealing through Metal deposition.Between source-drain electrode
Distance be 2.5 μm.Second dielectric layer is SiO2Layer, its thickness is about 100nm.Second dielectric layer court
It is all 0.5 μm beyond source, the length of drain electrode to one layer of edge of channel center.Gate electrode uses
Ni/Au(50/150nm)。
The explanation of above example is only intended to help to understand method and the core concept thereof of the present invention.Should refer to
Go out, for those skilled in the art, under the premise without departing from the principles of the invention,
The present invention can also be carried out some improvement and modification, these improve and modification also falls into right of the present invention and wants
In the protection domain asked.Multiple amendment to these embodiments is for those skilled in the art
It will be apparent that General Principle defined herein can be without departing from the spirit or scope of the present invention
In the case of realize in other embodiments.Therefore, the present invention is not intended to be limited to shown in the application
These embodiments, and it is to fit to consistent with principle disclosed in the present application and features of novelty the widest
Scope.
Claims (9)
1. a novel enhancement type III-V HFET, it is characterised in that include substrate
Material layer (1), the second semiconductor layer (2), the first semiconductor layer (3), drain electrode (4), source
Electrode (5), first medium layer (6), second dielectric layer (7) and gate electrode (8), wherein,
Form described second semiconductor layer (2) described substrate material layer (1) is upper, described the second half
Drain electrode (4) and source electrode (5), described drain electrode (4) and source electricity is constructed on conductor layer (2)
Between pole (5) by the first semiconductor layer (3) be connected and with the first semiconductor layer (3) Ohmic contact from
And form raceway groove；Described first semiconductor layer (3) has bigger than described second semiconductor layer (2)
Energy gap；
Described second semiconductor layer (2) and described first semiconductor layer (3) combine composition heterogeneous
Structure；The thickness of described first semiconductor layer (3) is not more than formation two-dimensional electron gas on heterojunction structure
The critical thickness of 2DEG, makes two-dimensional electron gas 2DEG natural in described heterojunction structure depleted；
Described first semiconductor layer (3) surface is additionally provided with first medium layer (6), described first medium layer
(6) being provided with described gate electrode (8), described gate electrode (8) covers whole channel length and described grid
Two edges extensions of electrode (8) exceed described drain electrode (4) and source electrode (5) respectively near raceway groove
The edge of side, is provided with between (5) at described gate electrode (8) and described drain electrode (4), source electrode
Described second dielectric layer (7).
Novel enhancement type III-V HFET the most according to claim 1, it is special
Levy and be, described second dielectric layer (7) be only located at described gate electrode (8) and described drain electrode (4) and
The marginal portion of the crossover of source electrode (5).
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, be additionally provided with between described first semiconductor layer (3) and the second semiconductor layer (2) in order to
Improving the interposed layer of the mobility of the two-dimensional electron gas of heterojunction boundary, the thickness of described interposed layer is 1nm.
Novel enhancement type III-V HFET the most according to claim 3, it is special
Levying and be, described interposed layer is AlN layer.
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, described first semiconductor layer (3) is AlGaN layer, and its thickness is 3～10nm；Described
Second semiconductor layer (2) is GaN layer.
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, described first semiconductor layer (3) is AlN layer；Described second semiconductor layer (2) is
GaN layer.
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, the Si of growth in situ when described first medium layer (6) is growth heterogeneous structure material3N4,
Its thickness is 5～25nm.
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, between described gate electrode (8) and first medium layer (6), be additionally provided with the 3rd dielectric layer,
Described 3rd dielectric layer is for reducing the grid leakage current of device further.
Novel enhancement type III-V HFET the most according to claim 1 and 2,
It is characterized in that, described second dielectric layer (7) is SiO2Layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610297662.9A CN105826369A (en) | 2016-05-06 | 2016-05-06 | Novel enhanced III-V heterojunction field effect transistor |
| US15/755,424 US10283598B2 (en) | 2016-05-06 | 2017-05-02 | III-V heterojunction field effect transistor |
| PCT/CN2017/082738 WO2017190643A1 (en) | 2016-05-06 | 2017-05-02 | Novel iii-v heterostructure field effect transistor |
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| CN201610297662.9A CN105826369A (en) | 2016-05-06 | 2016-05-06 | Novel enhanced III-V heterojunction field effect transistor |
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| CN106645323A (en) * | 2016-11-30 | 2017-05-10 | 南京大学 | Polar solvent chemical sensor based on oxide heterojunction and preparation method |
| WO2017190643A1 (en) * | 2016-05-06 | 2017-11-09 | 杭州电子科技大学 | Novel iii-v heterostructure field effect transistor |
| CN111599865A (en) * | 2020-05-29 | 2020-08-28 | 江南大学 | GaN-based P-channel MOSFET and preparation method thereof |
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| US20110278644A1 (en) * | 2010-05-11 | 2011-11-17 | Iqe Rf, Llc | Group iii-nitride enhancement mode field effect devices and fabrication methods |
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| US20110278644A1 (en) * | 2010-05-11 | 2011-11-17 | Iqe Rf, Llc | Group iii-nitride enhancement mode field effect devices and fabrication methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017190643A1 (en) * | 2016-05-06 | 2017-11-09 | 杭州电子科技大学 | Novel iii-v heterostructure field effect transistor |
| CN106645323A (en) * | 2016-11-30 | 2017-05-10 | 南京大学 | Polar solvent chemical sensor based on oxide heterojunction and preparation method |
| CN111599865A (en) * | 2020-05-29 | 2020-08-28 | 江南大学 | GaN-based P-channel MOSFET and preparation method thereof |
| CN111599865B (en) * | 2020-05-29 | 2021-08-24 | 江南大学 | GaN-based P-channel MOSFET and preparation method thereof |
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Application publication date: 20160803 |