CN205881909U - Novel normal pass type III -V heterojunction field effect transistor - Google Patents
Novel normal pass type III -V heterojunction field effect transistor Download PDFInfo
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- CN205881909U CN205881909U CN201620407034.7U CN201620407034U CN205881909U CN 205881909 U CN205881909 U CN 205881909U CN 201620407034 U CN201620407034 U CN 201620407034U CN 205881909 U CN205881909 U CN 205881909U
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Abstract
The utility model provides a novel normal pass type III V heterojunction field effect transistor, including substrate material layer, the 2nd semiconductor layer, medium template layer, drain electrode, source electrode, first dielectric layer, second dielectric layer and gate electrode, the 2nd semiconductor layer and a semiconductor layer body combine to form the heterojunction channel together, and medium template layer sets up on a semiconductor layer body and an equidistant formation n window, and a semiconductor layer body is grown along a n window and is formed a n bulge, thereby bulge makes a semiconductor layer exceed critical thickness and forms two dimensional electron gas 2DEG in bulge's projection area territory. Compared with the prior art, the utility model discloses the barrier layer that utilizes special design obtains the discrete channel to the channel of gate electrode between with source, drain electrode covers completely, thereby realizes the complete control to channel two dimensional electron gas, can avoid " the electric current collapses " effect of device, this device can obtain higher breakdown voltage and cutoff frequency simultaneously.
Description
Technical field
This utility model relates to technical field of semiconductor device, particularly relates to a kind of novel normally-off III-V different
Matter junction field effect transistor.
Background technology
Binary or ternary compound (even multi-element compounds) that some III and V group element are constituted have
There is piezoelectricity and spontaneous polarization effect, when they combine composition hetero-junctions (as
AlGaN/GaN), the two-dimensional electron gas (2DEG) of high concentration can be formed in the interface of hetero-junctions, with
2DEG at heterojunction boundary is that the device of conductive mechanism is referred to as hetero junction field effect pipe (HFET), also
It is properly termed as HEMT (HEMT).
HFET device has that high electron mobility, device operating frequencies be high and high efficiency feature.Micro-
The transmission of wave power emitter stage and field of power electronics have very important application prospect.But, so far
Till, there is a natural shortcoming in HFET device, as a example by AlGaN/GaN HFET, due to pole
Strong piezoelectricity and spontaneous polarization, in the case of without any applied voltage, heterojunction boundary is i.e. formed
The 2DEG of high concentration, HFET device is natural for open type (depletion type).The defect of HFET device
Limiting device application in logic circuit and Power Electronic Circuit, the former needs normally-off and open type
Logical complement, and the latter is for safety and energy-conservation consideration, it can be more desirable to normally-off device.
Prior art, in order to realize open type HFET device, generally has following several ways to obtain:
Grid lower channel F ion injection technique: inject the anion of F the most under the gate in the barrier layer in portion, lean on
Channel electrons under grid is exhausted by negative potential, it is achieved the positive threshold (enhancement mode) of device.
Groove gate technique: with dry etching technology by unkind for grid lower part barrier layer, when thickness is less than critical thickness
Time, the 2DEG under grid will exhaust.Only when grid voltage is higher than a certain voltage, just can again induce
2DEG.Achieve enhancement device.
Utilizing the device of P-AlGaN layer, this device is to add one layer of P-AlGaN layer in grid lower portion,
Due to the proportionality action that can carry, the 2DEG of raceway groove is made to exhaust.
There is different inferior positions in the most several technology, wherein F ion injection technique in reliability and obtains bigger
Threshold value aspect existing problems, in terms of technology controlling and process, there is bigger difficulty, P-AlGaN skill in groove gate technique
There is the shortcomings such as Material growth is difficult, devices switch frequency is low in art.
It addition, existing device is due to gate electrode only covering part raceway groove, so, the uncontrollable grid of gate voltage,
Raceway groove between drain electrode.When device is by "Off" state to "On" state, due to " empty matrix effect ",
Raceway groove between grid, leakage cannot be opened in time, causes channel resistance to increase, thus forms " current collapse "
Effect.
Therefore, for drawbacks described above present in currently available technology, it is necessary to study, to provide one in fact
The scheme of kind, solves defect present in prior art.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of novel normally-off III-V heterojunction field to imitate
Answer transistor, to solve the problems referred to above.
A kind of novel normally-off III-V HFET, including substrate material layer, the second half leads
Body layer, medium template layer, drain electrode, source electrode, first medium layer, second dielectric layer and gate electrode,
Wherein,
Described substrate material layer forms described second semiconductor layer, structure on described second semiconductor layer
Produce drain electrode and source electrode；
Described first semiconductor layer includes body and n the bossing formed along this this bulk-growth, n >=1；
Described second semiconductor layer and the first semiconductor layer body are combined together to form hetero-junctions raceway groove, should
Hetero-junctions raceway groove two ends connect described drain electrode and source electrode respectively；The thickness of described first semiconductor layer body
Degree is not more than the critical thickness forming two-dimensional electron gas 2DEG on hetero-junctions raceway groove, makes described hetero-junctions
Two-dimensional electron gas 2DEG natural in raceway groove is depleted；
Described medium template layer is arranged on described first semiconductor layer body and forms n window at equal intervals,
Described first semiconductor layer body forms described n bossing along described n window growth；Described convex
Playing part makes described first semiconductor layer beyond critical thickness thus in view field's shape of described bossing
Become two-dimensional electron gas 2DEG, described hetero-junctions raceway groove is formed n equally spaced two-dimensional electron gas
2DEG region；
Described first semiconductor layer surface is additionally provided with first medium layer, and described first medium layer is provided with described
Gate electrode, described gate electrode covers two edges extensions of whole channel length and described gate electrode and surpasses respectively
Cross described drain electrode and the source electrode edge near raceway groove side, described gate electrode and described drain electrode,
Described second dielectric layer it is provided with between source electrode.
Preferably, described bossing is continuous distribution or is divided into m part, m >=1 along its direction of growth.
Preferably, described second dielectric layer is only located at described gate electrode and described drain electrode and the friendship of source electrode
Marginal portion repeatedly.
Preferably, it is additionally provided with to improve hetero-junctions between described first semiconductor layer and the second semiconductor layer
The interposed layer of the mobility of the two-dimensional electron gas at interface, described interposed layer is AlN layer.
Preferably, described first semiconductor layer is AlGaN layer；Described second semiconductor layer is GaN layer.
Preferably, described first semiconductor layer is AlN layer, and described second semiconductor layer is GaN layer.
Preferably, the Si of growth in situ when described first medium layer is growth heterogeneous structure material3N4, it is thick
Degree is 5～25nm.
Preferably, described medium template layer is the SiO of LPCVD growth2Layer.
Preferably, described second dielectric layer is SiO2Layer.
Preferably, described second dielectric layer exceeds described drain electrode, source electrode respectively towards raceway groove one lateral edges
Length be 0.5 μm.
Relative to prior art, the novel normally-off III-V hetero junction field effect crystal that this utility model provides
Pipe, utilizes the barrier layer of particular design to obtain discontinuous raceway groove, uses high gate voltage again to induce
2DEG, thus realize the normally-off device of stable performance.And can take according to the performance requirement of device
Flexile design.
Accompanying drawing explanation
Fig. 1 is the generalized section of this utility model novel normally-off III-V HFET.
Fig. 2 is this utility model novel normally-off III-V HFET, when n=2, m=1,
First
Quasiconductor and the second semiconductor portions and the left view of medium template part.
Fig. 3 is this utility model novel normally-off III-V HFET, when n=2, m=1,
First
Quasiconductor and the second semiconductor portions and the front view of medium template part.
Fig. 4 is this utility model novel normally-off III-V HFET, when n=2, m=1,
First
Quasiconductor and the second semiconductor portions and the top view of medium template part.
Label declaration:
Substrate material layer 1, the second semiconductor layer 2, the first semiconductor layer body 3, the first convex semiconductor layer
Play part 4, two-dimensional electron gas 5, medium template 6, first medium layer 7, second dielectric layer 8, gate electrode
9, source electrode 10, drain electrode 11.
Detailed description of the invention
The following is specific embodiment of the utility model and combine accompanying drawing, the technical solution of the utility model is made
Further description, but this utility model is not limited to these embodiments.
The defect existed for prior art, the structure of HFET device in prior art is carried out by applicant
In-depth study, it has been found that the barrier layer of conventional device, the thickness of the i.e. first semiconductor layer exceedes
Critical thickness, so in the case of being not added with any applied voltage, due to material system piezoelectric polarization and
, in heterojunction boundary, the i.e. first quasiconductor and the interface of the second quasiconductor, i.e. there is height in spontaneous polarization
The two-dimensional electron gas 2DEG of concentration.Want to obtain normally-off device, it is necessary to use groove grid, F ion to inject
The special process such as doping.These technique exists and is difficult to the shortcoming that accurately controls, it addition, slot grid structure due to
, there is damage to device channel, therefore, for the performance of device in etching technics to be used in technical process
There is damage, it addition, there is also certain hidden danger in terms of the reliability of device.F injection technology is difficult to carry out essence
True control, and in terms of reliability, there is hidden danger.
In order to overcome disadvantage mentioned above, the utility model proposes a kind of novel normally-off III-V hetero junction field effect
Transistor, sees shown in Fig. 1, Fig. 2, Fig. 3 and Fig. 4, and wherein Fig. 1 is the generalized section of device,
Fig. 2-to Fig. 4 is n=2, and during m=1, the three of the first quasiconductor and the second quasiconductor and medium template part regard
Figure, wherein, Fig. 2 is left view, and Fig. 3 is front view, and Fig. 4 is top view.This utility model is novel
Normally-off III-V HFET includes substrate material layer 1, the second semiconductor layer 2, first
Semiconductor layer body 3, the first semiconductor layer projection part 4, two-dimensional electron gas 5, medium template 6, the
One dielectric layer 7, second dielectric layer 8, gate electrode 9, source electrode 10, drain electrode 11.
Wherein, substrate material layer 1 forms the second semiconductor layer 2, the second semiconductor layer 2 constructs
Go out drain electrode 11 and source electrode 10, and on the second semiconductor layer 2, form the first semiconductor layer body 3,
First semiconductor layer body 3 and the second semiconductor layer 2 combine composition heterojunction structure；Drain electrode 11
And by the raceway groove phase formed between the first semiconductor layer body 3 with the second quasiconductor 2 between source electrode 10
Even；First semiconductor layer has bigger energy gap than the second semiconductor layer；First semiconductor layer body 3
Thickness be not more than on heterojunction structure formed two-dimensional electron gas 2DEG critical thickness.
Structural medium template layer 6 on the first semiconductor layer body 3, and make on medium template layer 6 and etc.
Interval forms n window, and it is individual convex that the first semiconductor layer body 3 forms described n along this n window growth
Play part 4；Bossing makes described first semiconductor layer beyond critical thickness thus at described bossing
View field forms two-dimensional electron gas 2DEG, forms n equally spaced two dimension on described hetero-junctions raceway groove
Electron gas 2DEG region.
If only existing the first semiconductor layer body 3, heterojunction structure is not enough to produce two-dimensional electron gas
2DEG；Due to the place that there is the first semiconductor protrusion part 4, the first semiconductor layer body 3 and the
The gross thickness of semiconductor bossing 4 exceedes the critical thickness that can produce two-dimensional electron gas 2DEG,
So at the heterojunction boundary of lower section that there is the first semiconductor protrusion part 4, there is two-dimensional electron gas
2DEG.And then at heterojunction boundary, discontinuous two-dimensional electron gas 2DEG is distributed.Due to two dimension
Electron gas 2DEG's is discontinuous, and when without gate voltage, it is normal that conducting channel is formed without HFET device
Pass type.Only when gate voltage is more than threshold voltage, the two-dimensional electron gas 2DEG at heterojunction boundary is
Conducting channel can be formed continuously.
Using technique scheme, the gate electrode of this device achieves all standing of raceway groove between source, leakage,
So when device works, gate voltage can control raceway groove completely, it is achieved the instant shut-in of raceway groove, so,
Can at utmost avoid " current collapse " effect.
Although it addition, the gate electrode of this device covers between source, drain electrode, owing to the first quasiconductor has
The two-dimensional electron gas of bossing is commonly present, so the equivalent grid length of device is only on the first quasiconductor
Without the length of bossing, so, this device obtains higher cut-off frequency.Simultaneously as device
Length positive correlation between breakdown voltage and source, drain electrode, so, this device can obtain higher simultaneously
Breakdown voltage.
First semiconductor layer surface is additionally provided with first medium layer 7, and first medium layer 7 is provided with gate electrode 9,
Gate electrode 9 covers two edges extensions of whole channel length and gate electrode 9 and exceedes drain electrode 11 He respectively
Source electrode 10, near the edge of raceway groove side, sets between gate electrode 9 and drain electrode 11, source electrode 10
There is second dielectric layer 8.Due to the channel structure using gate electrode to be completely covered, it is achieved that gate voltage is for ditch
The control completely of road 2DEG, thus realize the device of no current pull-in effect.
In a preferred embodiment, being perpendicular to source, on direction that drain electrode is connected, the first half lead
Body layer bossing 4 can be continuous distribution, it is also possible to is divided into m part.Described dielectric layer template 6
Present discontinuous on direction between source, drain electrode.
In a preferred embodiment, second dielectric layer 8 is only located at gate electrode 9 and drain electrode 11 and source
The marginal portion of the crossover of electrode 10.The purpose of second dielectric layer 8 is to stop gate electrode 9 and electric leakage
Pole 11 and the electric connection of source electrode 10, but gate capacitance can be impacted again by second dielectric layer 8, and then
Affect grid-control ability and amplifying power.This structure makes second dielectric layer 8 only covering grid electrode 9 and electric leakage
The marginal portion of the crossover of pole 11 and source electrode 10, is completely covered first medium layer phase with second dielectric layer
Ratio, on the premise of realizing good electrical isolation, it is possible to ensure bigger gate capacitance, have bigger device
Mutual conductance, makes device have bigger grid-control ability and amplifying power.Preferably, the thickness of second dielectric layer
Should be the least.So, below the orthographic projection of grid, second dielectric layer is considerably less, makes the minimizing of gate capacitance
It is preferably minimized.
Meanwhile, this utility model novel enhancement type III-V HFET realize technique with existing
The technique having technology HFET device is essentially identical, it is not necessary to the extra complex process degree increasing device.This
The device of utility model can be realized by following main technological steps: (1) substrate material grows: properly
(such as Si substrate) on backing material, answer cushion, the second quasiconductor according to Material growth rule growth phase
Layer, selective growth interposed layer, the first semiconductor layer body 3, medium template layer 6.(2) to medium
Template layer carries out photoetching and etching, forms the growth window of the first semiconductor layer projection part 4.(3) raw
Long first semiconductor layer projection part 4.(4) source-drain electrode structure.(5) first medium layer growth.(4)
Second medium layer growth and constituency etching.(5) gate electrode structure.(6) it is passivated and encapsulates.
Use technique scheme, normally-off device can be realized；Further, use due to the channel material of device
Be growth and not have such as in groove-gate MOSFETs use etching technics, so heterojunction boundary will not be formed
Destroy, thus be conducive to improving device performance.
Embodiment 1: the present embodiment novel normally-off III-V HFET includes following a few portion
Point: backing material comprises Si material and the low temperature AI N cushion grown thereon, the second semiconductor layer
For GaN material layer (thickness is about 2 μm), the Part I of the first semiconductor layer is that AlGaN layer is (thick
Degree is about 3nm), between the first semiconductor layer and the second semiconductor layer Part I, it is provided with AlN inserts
Layer (thickness is about 1nm), for improving the electrology characteristic of 2DEG.Medium template layer is that LPCVD is (low
Pressure chemical vapor sedimentation) SiO that grows2Layer, it takes the numerical value n=2 of window, m=1, window along source,
A length of 0.5 μm that drain electrode is connected on direction, along the length being perpendicular to source, drain electrode is connected on direction
It is 100 μm.First medium layer is growth in situ Si3N4 layer, and thickness is about 10nm, second dielectric layer
For hfO2, thickness is 100nm.Source, drain electrode all use Ti/Al/Ni/Au (20/120/50/200nm)
Formed with high-temperature thermal annealing through Metal deposition.Distance between source-drain electrode is 2.5 μm.Second dielectric layer
It is all 0.5 μm beyond source, the length of drain electrode towards one layer of edge of channel center.Gate electrode uses
Ni/Au(50/150nm)。
Embodiment 2: the present embodiment novel normally-off III-V HFET includes following a few portion
Point: backing material comprises SiC material and the low temperature AI N cushion grown thereon, the second semiconductor layer
For GaN material layer (thickness is about 2 μm), the Part I of the first semiconductor layer is that AlN layer is (thick
Degree is about 3nm).Medium template layer is the SiO of LPCVD growth2Layer, it takes the numerical value of window
N=2, m=3, window along source, a length of 0.5 μm that is connected on direction of drain electrode, along being perpendicular to source, electric leakage
A length of 20 μm being extremely connected on direction.First medium layer is growth in situ Si3N4Layer, thickness is about
10nm, second dielectric layer is hfO2, thickness is 100nm.Source, drain electrode all use Ti/Al/Ni/Au
(20/120/50/200nm) formed with high-temperature thermal annealing through Metal deposition.Distance between source-drain electrode is 2.5
μm.Second dielectric layer is all 0.5 μm towards one layer of edge of channel center beyond source, the length of drain electrode.
Gate electrode uses Ni/Au (50/150nm).
The explanation of above example is only intended to help to understand method of the present utility model and core concept thereof.
It should be pointed out that, for those skilled in the art, without departing from this utility model principle
On the premise of, it is also possible to this utility model is carried out some improvement and modification, and these improve and modify also to fall
Enter in this utility model scope of the claims.To the multiple amendment of these embodiments to this area
Be apparent from for professional and technical personnel, General Principle defined herein can without departing from
Realize in other embodiments in the case of spirit or scope of the present utility model.Therefore, this utility model
It is not intended to be limited to these embodiments shown in the application, and is to fit to former with disclosed in the present application
The widest scope that reason is consistent with features of novelty.
Claims (9)
1. a novel normally-off III-V HFET, it is characterised in that include substrate material layer, the first semiconductor layer, the second semiconductor layer, medium template layer, drain electrode, source electrode, first medium layer, second dielectric layer and gate electrode, wherein,
Described substrate material layer is formed described second semiconductor layer, described second semiconductor layer constructs drain electrode and source electrode；
Described first semiconductor layer includes body and n the bossing formed along this this bulk-growth, and n is more than or equal to 1；
Described second semiconductor layer and the first semiconductor layer body are combined together to form hetero-junctions raceway groove, and these hetero-junctions raceway groove two ends connect described drain electrode and source electrode respectively；The thickness of described first semiconductor layer body is not more than the critical thickness forming two-dimensional electron gas 2DEG on hetero-junctions raceway groove, makes two-dimensional electron gas 2DEG natural in described hetero-junctions raceway groove depleted；
Described medium template layer is arranged on described first semiconductor layer body and forms n window at equal intervals, and described first semiconductor layer body forms described n bossing along described n window growth；Described bossing makes described first semiconductor layer beyond critical thickness thus form two-dimensional electron gas 2DEG in the view field of described bossing, forms n equally spaced two-dimensional electron gas 2DEG region on described hetero-junctions raceway groove；
Described first semiconductor layer surface is additionally provided with first medium layer, described first medium layer is provided with described gate electrode, described gate electrode covers two edges extensions of whole channel length and described gate electrode and exceedes described drain electrode and the source electrode edge near raceway groove side respectively, is provided with described second dielectric layer between described gate electrode and described drain electrode, source electrode.
Novel normally-off III-V HFET the most according to claim 1, it is characterised in that described bossing is continuous distribution or is divided into m part along its direction of growth, m is more than or equal to 1.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described second dielectric layer is only located at described gate electrode and described drain electrode and the marginal portion of the crossover of source electrode.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterized in that, being additionally provided with to improve the interposed layer of the mobility of the two-dimensional electron gas of heterojunction boundary between described first semiconductor layer and the second semiconductor layer, described interposed layer is AlN layer.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described first semiconductor layer is AlGaN layer；Described second semiconductor layer is GaN layer.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described first semiconductor layer is AlN layer, described second semiconductor layer is GaN layer.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that the Si of growth in situ when described first medium layer is growth heterogeneous structure material3N4, its thickness is 5～25nm.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described medium template layer is SiO2Layer.
Novel normally-off III-V HFET the most according to claim 1 and 2, it is characterised in that described second dielectric layer is SiO2Layer.
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| WO2017190643A1 (en) * | 2016-05-06 | 2017-11-09 | 杭州电子科技大学 | Novel iii-v heterostructure field effect transistor |
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