CN113745331A - Group III nitride grooved gate normally-off P-channel HEMT device and manufacturing method thereof - Google Patents
Group III nitride grooved gate normally-off P-channel HEMT device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a group III nitride groove gate normally-off P channel HEMT device and a manufacturing method thereof. The HEMT device comprises a double heterojunction structure formed by a first semiconductor, a second semiconductor and a third semiconductor, wherein the double heterojunction structure is provided with a double two-dimensional hole gas (2 DHG); the third semiconductor has a smaller band gap than the second semiconductor, is easily removed by a band-selective Photoelectrochemical Etching (PEC) technology, and forms a groove structure; the groove structure and the grid structure are arranged in a matched mode, and two-dimensional hole gas in the second semiconductor corresponding to the area below the grid can be exhausted. The groove gate normally-off type P channel HEMT device with large output current and low on-resistance can be effectively realized.
Description
Technical Field
The invention relates to a normally-off P-channel transistor, in particular to a polarization-effect-based group III nitride D-2DHG (Double-2 dimensional hole gas) groove gate normally-off HEMT (high Electron Mobility transistors) device and a preparation method thereof, belonging to the technical field of semiconductors.
Background
Power electronics are the core elements of power electronics systems. With the rapid development of power electronic technology, the limitations of the traditional silicon material and the second generation semiconductor material are increasingly prominent, due to the urgent requirements of power systems in terms of high frequency, low loss, high power capacity and the like. Third-generation wide bandgap semiconductor materials typified by GaN and SiC have been rapidly developed. GaN has the characteristics of large forbidden band width, high saturated hole drift speed, large critical breakdown electric field, stable chemical property and the like. Compared with SiC materials, GaN has unique characteristics such as piezoelectric polarization and spontaneous polarization effect, and the AlGaN/GaN heterojunction structure has a high-density and high-mobility two-dimensional electron gas (2DEG) surface density of about 10 due to the polarization effect13cm-2Mobility higher than 1500cm2V · s. The HEMT prepared by the A1GaN/GaN heterojunction enables a GaN device to have low on-resistance and high working frequency, and can meet the requirements of high power, higher frequency, smaller volume and higher temperature.
The threshold voltage of a commercial p-GaN gate HEMT is about +1.5V, the highest forward gate operating voltage is about 7V, while the threshold voltage of a Si-based power switch device in a power system is generally more than 3V, and the forward gate operating voltage can reach 18V. Besides improving the threshold voltage and the gate voltage swing of the p-GaN gate HEMT, the GaN power monolithic integration is developed to reduce the parasitic inductance in the package and shorten the gate loop, and the method is also an important research direction for improving the circuit stability and the switching speed. The most commonly used CMOS (complementary Metal Oxide semiconductor) inverter is integrated on a single chip, and has the advantages of low power consumption, high noise tolerance, high logic swing, high input impedance, low input capacitance and the like.
At present, the gap between the performance and the theoretical performance of the developed GaN CMOS is large, wherein the research on the n-channel A1GaN/GaN HEMT device is mature. P-channel GaN HEMT devices based on polarized 2DHG remain an important direction of research in the GaN field. p-channel GaN devices also face a number of problems, the most significant of which are the low mobility of holes and the normally-off technology. The highest mobility of holes reported to date is 43cm2Such low hole mobility results in very low current density for p-channel devices. Meanwhile, the areal density of the 2DHG can reach 1013Depletion is difficult, which makes it very difficult to achieve a high current density, high switching ratio, normally off p-channel device. At present, the method for realizing the normally-off p-channel device mainly adopts groove gate, A1GaN cap layer and 2DEG back gate regulation and control technologies, but the output current and the on-off ratio of the device are sacrificed by the technologies. The recessed gate structure has unique advantages, such as easy structural implementation, low gate leakage, large gate voltage swing, etc., and is currently the most popular method for implementing p-channel GaN HEMTs. However, the problems of etching damage and interface states caused by etching are difficult to solve, so that the performance of the conventional p-channel HEMT device is far from the theoretical value. For example, the structure of a conventional p-channel GaN HEMT device is shown in fig. 1 a-1 b, the device adopts a double-layer Mg-doped p-GaN cap layer structure with different concentrations, the device performance is shown in fig. 2a and 2b, the on-resistance is 400 Ω · mm, the output current is 5mA/mm, and the on-off ratio is 6 × 105. The device performance has reached the higher level of p-channel GaN HEMT devices studied at present, but the device has a large distance from the theoretical limit of GaN, and the output current, on-resistance and on-off ratio of the device have a large room for improvement.
Disclosure of Invention
The invention mainly aims to provide a group III nitride groove gate normally-off type P channel HEMT device, a preparation method and application thereof, so as to overcome the defects of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a group III nitride groove gate normally-off type P channel HEMT device which comprises a first semiconductor, a second semiconductor and a third semiconductor which are sequentially stacked, wherein the second semiconductor is respectively matched with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction; two-dimensional hole gases (2DHG) serving as a first hole channel and a second hole channel are respectively formed in the first heterojunction and the second heterojunction; and a groove structure is formed in the region of the third semiconductor corresponding to the grid electrode, the groove structure is matched with the grid electrode structure, and the grid electrode structure can exhaust two-dimensional hole gas in the second semiconductor corresponding to the region below the grid electrode.
In some embodiments, the third semiconductor material comprises a group III nitride containing In and is formed as a p-type semiconductor by Mg doping.
In some embodiments, the gate structure includes a gate electrode and a gate dielectric layer, the gate electrode is at least partially disposed in the groove structure, the gate dielectric layer is at least disposed between the gate electrode and a groove wall of the groove structure, and the gate electrode and the gate dielectric layer cooperate with the second semiconductor remaining in the area under the gate electrode to form a metal-insulator-semiconductor structure.
The embodiment of the invention also provides a method for manufacturing the group III nitride groove gate normally-off type P channel HEMT device, which comprises the following steps:
sequentially growing a first semiconductor, a second semiconductor and a third semiconductor on a substrate, enabling the second semiconductor to be respectively matched with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, enabling two-dimensional hole gas to be formed in the first heterojunction to serve as a first hole channel, enabling two-dimensional hole gas to be formed in the second heterojunction to serve as a second hole channel, and removing a local region of the third semiconductor corresponding to a grid electrode to form a groove structure,
or sequentially growing a first semiconductor and a second semiconductor on the substrate to form a first heterojunction, forming two-dimensional hole gas in the first heterojunction to serve as a first hole channel, arranging a mask on the second semiconductor, growing a third semiconductor on the surface of the second semiconductor exposed from the mask to form a second heterojunction, forming two-dimensional hole gas in the second semiconductor to serve as a second hole channel, and forming a groove structure in a region of the third semiconductor corresponding to the grid; and
and arranging a source electrode, a drain electrode and a grid electrode structure which are matched with the first heterojunction and the second heterojunction, wherein the grid electrode structure is matched with the groove structure and can exhaust two-dimensional hole gas in the region below the groove structure in the second semiconductor.
In some embodiments, the method of making further comprises:
arranging a mask on the third semiconductor, removing a local area of the third semiconductor distributed below the grid electrode in an etching mode with energy band selectivity, and enabling the etching depth to reach the second semiconductor to form a groove structure;
and depositing and forming a continuous gate dielectric layer at least on the groove wall of the groove structure.
The embodiment of the invention also provides a method for using the group III nitride groove gate normally-off type P channel HEMT device, which comprises the following steps: applying a voltage less than a turn-on voltage to a gate of the HEMT device to electrically connect a source and a drain through two-dimensional holes, thereby turning on the HEMT device; or applying a voltage larger than the starting voltage to the grid electrode of the HEMT device, so that the two-dimensional hole gas in the first heterojunction and positioned in the area below the grid electrode is exhausted, and the HEMT device is turned off.
Compared with the prior art, the embodiment of the invention realizes double-layer 2DHG by using a double-heterojunction structure, can effectively improve the output current of a P-channel HEMT device, reduces the on-resistance, further removes a narrow-bandgap material on the upper layer of the heterojunction by combining the energy band selective PEC etching technology with low etching damage to realize a groove gate structure, can effectively avoid etching damage, reduces the surface state, improves the uniformity and the repeatability and the like, and obviously improves the device performance. The invention can effectively realize the optimization of the normally-off characteristic and the conduction characteristic of the P-channel HEMT device.
Drawings
FIG. 1a is a schematic diagram of a prior art p-channel HEMT device material structure;
FIG. 1b is a schematic diagram of a recessed gate structure of a conventional p-channel HEMT device;
fig. 2a and 2b show the output characteristics, on-resistance and on-off ratio of the HEMT device of fig. 1 a-1 b, respectively;
fig. 3 is a schematic structural diagram of an HEMT device in an embodiment of the present invention;
fig. 4 is a flow chart of a process for fabricating a HEMT device in an embodiment of the present invention;
fig. 5a and 5b respectively show simulation transfer characteristic curves of a HEMT device in linear coordinates and log coordinates according to an embodiment of the present invention;
fig. 6 shows an analog simulation output characteristic curve of a HEMT device in an embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
One aspect of the embodiments of the present invention provides a group III nitride recessed gate normally-off P-channel HEMT device, including a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, the second semiconductor cooperating with the first semiconductor and the third semiconductor respectively to form a first heterojunction and a second heterojunction; two-dimensional hole gas serving as a first hole channel and a second hole channel is formed in the first heterojunction and the second heterojunction respectively; and a groove structure is formed in the region of the third semiconductor corresponding to the grid electrode, the groove structure is matched with the grid electrode structure, and the grid electrode structure can exhaust two-dimensional hole gas in the second semiconductor corresponding to the region below the grid electrode.
Further, the first heterojunction and the second heterojunction are matched to form a double-heterojunction structure.
Further, a local region of the third semiconductor corresponding to the gate is removed to form the recess structure.
Further, the second semiconductor is formed on the first semiconductor and has a band gap narrower than that of the first semiconductor.
Further, the third semiconductor has a smaller band gap than the second semiconductor and is easily removed using band-selective Photoelectrochemical Etching (PEC) techniques.
Further, the material of the first semiconductor, the second semiconductor and the third semiconductor is selected from group III nitrides, but not limited thereto.
For example, the material of the third semiconductor includes a group III nitride containing In, and In which the Mg doping concentration gradually increases In a direction away from the second semiconductor.
Preferably, the In-containing group III nitride includes InxGa1-xN，0.01≤x≤0.02。
Further, the third semiconductor is a Mg-doped p-type semiconductor, wherein the Mg doping concentration is 1 × 1017cm-3To 1X 1020cm-3。
For example, the material of the second semiconductor includes u-GaN, p-GaN, etc., and is not limited thereto.
For example, the material of the first semiconductor includes AlGaN and the like, but is not limited thereto.
Furthermore, the grid structure comprises a grid and a grid dielectric layer, the grid is at least partially arranged in the groove structure, the grid dielectric layer is at least arranged between the grid and the groove wall of the groove structure, and the grid dielectric layer are matched with a second semiconductor reserved in the area under the grid to form a metal-insulator-semiconductor structure.
Preferably, the material of the gate dielectric layer includes, but is not limited to, silicon oxide, silicon nitride, or aluminum oxide.
Further, the HEMT device further comprises a source electrode and a drain electrode, wherein the source electrode and the drain electrode form ohmic contact with the double heterojunction structure, particularly the third semiconductor, and the source electrode and the drain electrode can be electrically connected through the first hole channel and the second hole channel.
Further, an insertion layer is arranged between the first semiconductor and the second semiconductor. Preferably, the material of the insertion layer includes AlN or the like, but is not limited thereto.
Further, the first semiconductor is formed on a buffer layer formed on a substrate. Preferably, the buffer layer is made of GaN or the like, but is not limited thereto.
Furthermore, a nucleation layer is distributed between the buffer layer and the substrate. Preferably, the material of the nucleation layer includes AlN or the like, and is not limited thereto.
The structure of a typical HEMT device in the above embodiments of the present application can be seen from fig. 3.
Another aspect of the embodiments of the present invention also provides a method for manufacturing the group III nitride recessed gate normally-off P-channel HEMT device, including:
sequentially growing a first semiconductor, a second semiconductor and a third semiconductor on a substrate, enabling the second semiconductor to be respectively matched with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, enabling two-dimensional hole gas to be formed in the first heterojunction to serve as a first hole channel, and enabling two-dimensional hole gas to be formed in the second heterojunction to serve as a second hole channel;
removing a local region of the third semiconductor corresponding to the grid electrode, thereby forming a groove structure; and
and arranging a source electrode, a drain electrode and a grid electrode structure which are matched with the first heterojunction and the second heterojunction, wherein the grid electrode structure is matched with the groove structure and can exhaust two-dimensional hole gas in the region below the groove structure in the second semiconductor.
Further, the preparation method can also comprise the following steps:
arranging a mask on the third semiconductor, removing a local area of the third semiconductor distributed below the grid electrode in an etching mode with energy band selectivity, and enabling the etching depth to reach the second semiconductor to form a groove structure;
and depositing and forming a continuous gate dielectric layer at least on the groove wall of the groove structure.
Further, the etching manner with band selectivity includes a Photo-electrochemical (PEC) etching technique, but is not limited thereto.
In some more specific embodiments, the preparation method may further include:
providing a heterojunction comprising a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor and having a narrower bandgap than the first semiconductor, the heterojunction having a 2DHG formed therein;
providing a third semiconductor on the heterojunction, the third semiconductor having a narrower band gap than the second semiconductor and having a 2DHG formed therein;
arranging a mask on the third semiconductor, etching the third semiconductor exposed from the mask by an energy band selective PEC etching technology, and enabling the etching to stop when reaching the second semiconductor, thereby forming a groove structure corresponding to the grid in the third semiconductor; and
and manufacturing a source electrode, a drain electrode, a grid electrode and a grid medium, enabling the grid electrode and the grid medium and the second semiconductor reserved in the area under the grid to form an MIS structure, and enabling the source electrode and the drain electrode to be electrically connected through the 2DHG, wherein the 2DHG reserved in the second semiconductor in the area under the grid is depleted.
Further, the source electrode and the drain electrode are electrically connected through a two-dimensional hole gas in a double heterojunction structure, which includes a two-dimensional hole gas formed in the first heterojunction and the second heterojunction.
Specifically, when a certain negative voltage is applied to the gate, the source and the drain can be electrically connected through the double 2DHG in the double heterojunction structure.
Preferably, the preparation method further comprises the following steps: and epitaxially growing In-containing III-group nitride on the second semiconductor upper region to form a groove structure.
In some more specific embodiments, the preparation method may include:
providing a heterojunction comprising a first semiconductor (also can be considered a barrier layer) and a second semiconductor (also can be considered a first channel layer) formed on the first semiconductor and having a narrower bandgap than the first semiconductor, the heterojunction having a 2DHG formed therein;
arranging a mask on the second semiconductor, and growing a third semiconductor (which can also be regarded as a cap layer or a second channel layer) on the surface of the second semiconductor exposed in the mask to form a groove structure; and
and manufacturing a source electrode, a drain electrode, a grid electrode and a grid medium, enabling the grid electrode and the grid medium and the second semiconductor remained in the area under the grid electrode to form a metal-insulator-semiconductor (MIS) structure, and depleting 2DHG in the second semiconductor of the area under the grid electrode.
In the above embodiments of the present invention, the first semiconductor, the second semiconductor, and the third semiconductor may be formed by epitaxial growth methods known in the art, and unless otherwise specified, various operations in the fabrication process of the HEMT device may also be well known in the art, and the materials of devices such as a gate, a source, a drain, and the like are also known in the art and thus are not described herein again.
Another aspect of an embodiment of the present invention also provides a method of using the trench-gate normally-off P-channel HEMT device, including: applying a voltage smaller than a turn-on voltage to a gate of the HEMT device, so that a source electrode and a drain electrode are electrically connected through two-dimensional hole gas (double 2DHG in a double heterojunction structure), and the HEMT device is turned on; or applying a voltage larger than the starting voltage to the grid electrode of the HEMT device, so that the two-dimensional hole gas in the first heterojunction and positioned in the area below the grid electrode is exhausted, and the HEMT device is turned off.
The technical solution of the present invention will be further explained with reference to examples. Various materials and devices used in the following examples are commercially available, and the materials used therein such as an epitaxial growth process, an etching process, etc. may be implemented in a manner well known in the art unless otherwise specified.
Further, referring to fig. 4, the method for manufacturing the HEMT may include the following steps:
(1) sequentially growing and forming a GaN buffer layer, an AlGaN barrier layer (namely, a first semiconductor), a GaN channel layer (namely, a second semiconductor) and an InGaN channel layer (namely, a third semiconductor) on a substrate in any one of Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) or Hydride Vapor Phase Epitaxy (HVPE), wherein the GaN channel layer and the AlGaN barrier layer form a heterojunction, and 2DHG is formed in the heterojunction;
(2) etching InGaN (namely, a third semiconductor) in the grid region by at least using the metal mask or the insulating dielectric layer mask through a PEC etching technology with energy band selection until the GaN layer is etched, and forming a groove structure;
(3) removing the etching mask, and depositing a dielectric layer on the surface of the formed groove structure by adopting any one mode of Plasma Enhanced Chemical Vapor Deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) or Atomic Layer Deposition (ALD);
(4) and etching the source and drain regions in a manner of dry etching such as Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP) and the like, wet etching or combination of the dry etching and the wet etching to expose the InGaN (third semiconductor) layer, so that the source and the drain can form good ohmic contact with the heterojunction. And respectively manufacturing a source electrode and a drain electrode in the etched source and drain regions and manufacturing a grid electrode in the grid electrode region in a metal deposition mode of electron beam Evaporation (EB) or magnetron sputtering (Sputter).
As an alternative, in the foregoing steps (1) - (2), an AlGaN barrier layer and a GaN channel layer may be grown, a patterned mask may be disposed on the GaN channel layer to expose the surface of the GaN channel layer except the region corresponding to the gate structure, and then an InGaN channel layer may be grown to form a groove structure in the InGaN channel layer, and then the operations of steps (3), (4), and the like may be continued.
When the HEMT is in use, the gate-source voltage V is satisfiedGsGreater than a threshold voltage VTHTime (V)GS＜VTH) The device is in an off state; when the gate-source voltage is less than the threshold voltage (V)Gs＞VTH) The device is in an on state.
Further, fig. 5a and 5b show transfer characteristic curves, V, of the device in simulation example 1ds-5V, where fig. 5a corresponds to linear coordinates and fig. 5b corresponds to logarithmic coordinates. Fig. 6 shows the output characteristic curve of the device of simulation example 1. The parameters used in fig. 5a, 5b and 6 for the HEMT device samples were set as follows: the barrier layer is 40nm thick Al0.23Ga0.77N, the first channel layer is GaN with a thickness of 10nm, and the second channel layer is In with a thickness of 40nm0.07Ga0.93N; the gate dielectric in the simulation adopts Al with the thickness of 5nm2O3The dielectric layer and the gate are set to Ti metal work function, and the source and drain ohmic contacts are set to specific contact resistance of 0.0001 omega cm2. And (3) simulation results: the threshold voltage of the device is-0.7V, the subthreshold swing is 115mV/decade, and the on/off state current ratio is 108Output current of 107.4 omega mm @ Vgs＝-6V，Vds＝-5V。
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A group III nitride groove gate normally-off type P channel HEMT device is characterized by comprising a first semiconductor, a second semiconductor and a third semiconductor which are sequentially stacked, wherein the second semiconductor is respectively matched with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction; two-dimensional hole gas serving as a first hole channel and a second hole channel is formed in the first heterojunction and the second heterojunction respectively; and a groove structure is formed in the region of the third semiconductor corresponding to the grid electrode, the groove structure is matched with the grid electrode structure, and the grid electrode structure can exhaust two-dimensional hole gas in the second semiconductor corresponding to the region below the grid electrode.
2. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the third semiconductor has a smaller bandgap than the second semiconductor; and/or the third semiconductor material comprises a group III nitride containing In; preferably, the In-containing group III nitride includes InxGa1-xN，0.01≤x≤0.2。
3. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the third semiconductor is a Mg-doped p-type semiconductor, wherein the Mg doping concentration is 1 x 1017cm-3To 1X 1020cm-3。
4. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the grid structure comprises a grid and a grid dielectric layer, the grid is at least partially arranged in the groove structure, the grid dielectric layer is at least arranged between the grid and the groove wall of the groove structure, and the grid dielectric layer are matched with a second semiconductor reserved in the area under the grid to form a metal-insulator-semiconductor structure.
5. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the HEMT device further comprises a source electrode and a drain electrode, wherein the source electrode and the drain electrode form ohmic contact with the third semiconductor, and the source electrode and the drain electrode can be electrically connected through the first hole channel and the second hole channel.
6. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the first semiconductor is made of AlGaN; and/or the material of the second semiconductor comprises GaN; and/or an insertion layer is further arranged between the first semiconductor and the second semiconductor, and preferably, the material of the insertion layer comprises A1N; and/or the gate dielectric layer is made of silicon oxide, silicon nitride or aluminum oxide.
7. The group III nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein: the first semiconductor is formed on a buffer layer formed on a substrate; preferably, the buffer layer is made of GaN.
8. The method of fabricating a group III nitride recessed gate normally-off P-channel HEMT device according to any one of claims 1-7, comprising:
sequentially growing a first semiconductor, a second semiconductor and a third semiconductor on a substrate, enabling the second semiconductor to be respectively matched with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, enabling two-dimensional hole gas to be formed in the first heterojunction to serve as a first hole channel, enabling two-dimensional hole gas to be formed in the second heterojunction to serve as a second hole channel, and removing a local region of the third semiconductor corresponding to a grid electrode to form a groove structure,
or sequentially growing a first semiconductor and a second semiconductor on the substrate to form a first heterojunction, forming two-dimensional hole gas in the first heterojunction to serve as a first hole channel, arranging a mask on the second semiconductor, growing a third semiconductor on the surface of the second semiconductor exposed from the mask to form a second heterojunction, forming two-dimensional hole gas in the second semiconductor to serve as a second hole channel, and forming a groove structure in a region of the third semiconductor corresponding to the grid; and
and arranging a source electrode, a drain electrode and a grid electrode structure which are matched with the first heterojunction and the second heterojunction, wherein the grid electrode structure is matched with the groove structure and can exhaust two-dimensional hole gas in the region below the groove structure in the second semiconductor.
9. The method of manufacturing of claim 8, further comprising:
arranging a mask on the third semiconductor, removing a local area of the third semiconductor distributed below the grid electrode in an etching mode with energy band selectivity, and enabling the etching depth to reach the second semiconductor to form a groove structure;
depositing and forming a continuous gate dielectric layer at least on the groove wall of the groove structure;
preferably, the etching mode with the energy band selectivity is a photoelectrochemical etching method;
preferably, the operation of etching the third semiconductor to form the groove structure is self-stopped when reaching the second semiconductor.
10. A manufacturing method of a group III nitride groove gate normally-off P channel HEMT device is characterized by comprising the following steps:
providing a heterojunction comprising a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor and having a narrower band gap than the first semiconductor, the heterojunction having a two-dimensional hole gas formed therein;
providing a third semiconductor on the heterojunction, the third semiconductor having a narrower band gap than the second semiconductor, thereby forming a two-dimensional hole gas in the second semiconductor;
arranging a mask on the third semiconductor, etching the third semiconductor exposed from the mask by an energy band selective PEC etching technology, and enabling the etching to stop automatically when reaching the second semiconductor, thereby forming a groove structure corresponding to the grid; and
and manufacturing a source electrode, a drain electrode, a grid electrode and a grid medium, enabling the grid electrode and the grid medium and the second semiconductor reserved in the area under the grid to form an MIS structure, and enabling the source electrode and the drain electrode to be electrically connected through the two-dimensional hole gas, wherein the two-dimensional hole gas reserved in the second semiconductor in the area under the grid is exhausted.
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