WO2021237901A1

WO2021237901A1 - Iii-nitride grooved gate normally-off-type p-channel hemt device and manufacturing method therefor

Info

Publication number: WO2021237901A1
Application number: PCT/CN2020/102915
Authority: WO
Inventors: 于国浩; 张宝顺; 张丽; 张晓东; 宋亮; 吴冬东
Original assignee: 中国科学院苏州纳米技术与纳米仿生研究所
Priority date: 2020-05-28
Filing date: 2020-07-20
Publication date: 2021-12-02
Also published as: CN113745331A

Abstract

Disclosed are an III-nitride grooved gate normally-off-type P-channel HEMT device and a manufacturing method therefor. The HEMT device comprises a double-heterojunction structure formed by a first semiconductor, a second semiconductor and a third semiconductor, wherein the double-heterojunction structure has double-2-dimensional hole gases (2DHG); the third semiconductor has a band gap smaller than that of the second semiconductor, with the band gap being easily removed by using photoelectrochemical corrosion (PEC) technology selected according to an energy band, so as to form a groove structure; and the groove structure and a gate electrode structure are arranged in a matching manner, such that 2-dimensional hole gas in an area inside the second semiconductor which corresponds to the bottom of a gate electrode can be depleted. By means of the present application, a grooved gate normally-off-type P-channel HEMT device with a large output current and low on-resistance can be effectively realized.

Description

Group III nitride groove gate normally-off P-channel HEMT device and manufacturing method thereof

Technical field

This application relates to a normally-off P-channel transistor, and in particular to a group III nitride D-2DHG (Double-2dimentional hole gas) groove gate normally-off HEMT based on the polarization effect (High Electron Mobility Transistors) devices and preparation methods thereof belong to the field of semiconductor technology.

Background technique

Power electronic devices are the core components of power electronic systems. With the rapid development of power electronics technology, the limitations of traditional silicon materials and second-generation semiconductor materials have become increasingly prominent due to the urgent needs of power systems in terms of high frequency, low loss, and high power capacity. The third-generation wide-bandgap semiconductor materials represented by GaN and SiC have been developed rapidly. GaN has the characteristics of large forbidden band width, high saturation hole drift speed, large critical breakdown electric field, and stable chemical properties. Compared with SiC materials, GaN has its unique characteristics, such as piezoelectric polarization and spontaneous polarization effects. Due to the polarization effect, the AlGaN/GaN heterojunction structure has high-density and high-mobility two-dimensional electrons. The surface density of 2DEG is about 10 ¹³ cm ^-2 , and the mobility is higher than 1500 cm ² /(V·s). The HEMT prepared with AlGaN/GaN heterojunction enables GaN devices to have low on-resistance and high operating frequency, which can achieve the requirements of high power, higher frequency, smaller volume and higher temperature.

The threshold voltage of commercial p-GaN gate HEMT is about +1.5V, and the highest forward gate operating voltage is about 7V, while the threshold voltage of Si-based power switching devices in power systems is generally above 3V, and the forward gate works The voltage can reach 18V. In addition to increasing the threshold voltage and gate voltage swing of p-GaN gate HEMT, the development of GaN power monolithic integration to reduce parasitic inductance in the package and shorten the gate loop is also an important research direction to improve circuit stability and increase switching speed . The single chip integrates the most commonly used CMOS (Complementary Metal Oxide Semiconductor) inverter, which has the advantages of low power consumption, high noise tolerance, high logic swing, high input impedance and low input capacitance.

At present, there is a large gap between the performance and theoretical performance of the developed GaN CMOS. Among them, the research on n-channel AlGaN/GaN HEMT devices has been relatively mature. The p-channel GaN HEMT device based on polarization 2DHG is still an important research direction in the GaN field. P-channel GaN devices still face many problems, the most important of which is the low mobility of holes and normally-off technology. The highest hole mobility reported so far is 43cm ² /V·s. Such a low hole mobility makes the current density of p-channel devices very low. At the same time, the areal density of 2DHG can reach 10 ¹³ , which is more difficult to deplete, which makes it very difficult to realize a normally-off p-channel device with high current density and high switching ratio. At present, the methods to realize normally-off p-channel devices mainly include groove gate, AlGaN cap layer and 2DEG back gate control technology, but these technologies will sacrifice the output current and switching ratio of the device. The grooved gate structure has its unique advantages, such as easy realization in structure, low gate leakage and large gate voltage swing, etc., and it is currently the most popular method to realize p-channel GaN HEMT. However, it has been difficult to solve the problems of etching damage and interface state caused by etching, so that the performance of the existing p-channel HEMT devices is far from the theoretical value. For example, the structure of an existing p-channel GaN HEMT device is shown in Figure 1a-Figure 1b. The device adopts a p-GaN cap layer structure doped with two layers of Mg at different concentrations. The device performance is shown in Figure 2a and Figure 2b. As shown, the on-resistance is 400Ω·mm, the output current is 5mA/mm, and the on-off ratio is 6×105. The device performance has reached the higher level of the p-channel GaN HEMT devices currently studied, but there is still a long way to go to the theoretical limit of GaN. There is still much room for improvement in the output current, on-resistance and switching ratio of the device.

Summary of the invention

The main purpose of this application is to provide a III-nitride recessed gate normally-off P-channel HEMT device, its preparation method and application, so as to overcome the deficiencies of the prior art.

In order to achieve the foregoing invention objectives, the technical solutions adopted in this application include:

The embodiment of the present application provides a III-nitride recessed gate normally-off P-channel HEMT device, which includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, and the second semiconductor is respectively connected to the first semiconductor. The semiconductor and the third semiconductor cooperate to form a first heterojunction and a second heterojunction; the first heterojunction and the second heterojunction are respectively formed as a first hole channel and a second hole channel The two-dimensional hole gas (2DHG) of the third semiconductor; the region of the third semiconductor corresponding to the gate is formed with a groove structure, and the groove structure is arranged in cooperation with the gate structure, and the gate structure can be The two-dimensional hole gas corresponding to the area under the gate is depleted.

In some embodiments, the material of the third semiconductor includes a group III nitride containing In, and is formed into a p-type semiconductor by Mg doping.

In some embodiments, the gate structure includes a gate and a gate dielectric layer, the gate is at least partially disposed in the groove structure, and the gate dielectric layer is disposed at least in the groove of the gate and the groove structure. Between the walls, and the gate and the gate dielectric layer cooperate with the second semiconductor remaining in the region under the gate to form a metal-insulator-semiconductor structure.

The embodiment of the present application also provides a method for manufacturing the III-nitride recessed gate normally-off P-channel HEMT device, which includes:

The first semiconductor, the second semiconductor, and the third semiconductor are sequentially grown on the substrate, and the second semiconductor is made to cooperate with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, and A two-dimensional hole gas is formed in the first heterojunction as a first hole channel, and a two-dimensional hole gas is formed in the second heterojunction as a second hole channel, and the The third semiconductor corresponding to the partial area of the gate is removed, thereby forming a groove structure,

Alternatively, a first semiconductor and a second semiconductor are sequentially grown on the substrate to form a first heterojunction, and a two-dimensional hole gas is formed in the first heterojunction as the first hole channel, and then A mask is set on the second semiconductor, and then a third semiconductor is grown on the surface of the second semiconductor exposed from the mask to form a second heterojunction, and a two-dimensional hole gas is formed in the second semiconductor as A second hole channel, while forming a groove structure in the region of the third semiconductor corresponding to the gate; and

The source, drain, and gate structures matched with the first heterojunction and the second heterojunction are arranged, and the gate structure is arranged in cooperation with the groove structure, and the structure can be integrated into the second semiconductor The two-dimensional cavity gas in the area below the groove structure is exhausted.

In some embodiments, the preparation method further includes:

Setting a mask on the third semiconductor, and removing a local area of the third semiconductor distributed under the gate through an etching method with band selectivity, and the etching depth reaches the second semiconductor to form a groove structure;

At least a continuous gate dielectric layer is deposited on the groove wall of the groove structure.

An embodiment of the present application also provides a method for using the III-nitride recessed gate normally-off P-channel HEMT device, which includes: applying a voltage less than the turn-on voltage to the gate of the HEMT device to make the source The electrode and the drain are electrically connected by a two-dimensional hole gas, so that the HEMT device is turned on; or, a voltage greater than the turn-on voltage is applied to the gate of the HEMT device to make the first heterojunction located in the region under the gate The two-dimensional hole gas is depleted, so that the HEMT device is turned off.

Compared with the prior art, the above embodiments of the present application use a double heterojunction structure to achieve a double-layer 2DHG, which can effectively increase the output current of the P-channel HEMT device, reduce the on-resistance, and then combine energy band selection with low etching damage The flexible PEC etching technology removes the narrow band gap material located on the upper layer of the heterojunction to realize the grooved gate structure, which can effectively avoid etching damage, reduce surface state, improve uniformity and repeatability, etc., and significantly improve device performance. This application can effectively realize the optimization of the normally-off characteristic and the conduction characteristic of the P-channel HEMT device.

Description of the drawings

FIG. 1a is a schematic diagram of the material structure of an existing p-channel HEMT device;

FIG. 1a is a schematic diagram of a recessed gate structure of an existing p-channel HEMT device;

Fig. 2a and Fig. 2b respectively show the output characteristics, on-resistance and switching ratio of the HEMT device shown in Fig. 1a-1b;

FIG. 3 is a schematic structural diagram of a HEMT device in an embodiment of the present application;

FIG. 4 is a process flow chart of a manufacturing process of a HEMT device in an embodiment of the present application;

5a and 5b respectively show simulation transfer characteristic curves of a HEMT device in linear coordinates and log coordinates in an embodiment of the present application;

Fig. 6 shows a simulation output characteristic curve of a HEMT device in an embodiment of the present application.

Detailed ways

In view of the deficiencies in the prior art, the inventor of this case was able to propose the technical solution of this application after long-term research and extensive practice. The technical solution, its implementation process and principles will be further explained as follows.

One aspect of the embodiments of the present application provides a III-nitride recessed gate normally-off P-channel HEMT device, which includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, and the second semiconductors are respectively Cooperating with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction; the first heterojunction and the second heterojunction are respectively formed as a first hole channel and a second hole A two-dimensional hole gas in a hole channel; a groove structure is formed in the region of the third semiconductor corresponding to the gate, and the groove structure is arranged in cooperation with the gate structure. Corresponding to the depletion of the two-dimensional hole gas in the area under the gate.

Further, the first heterojunction and the second heterojunction cooperate to form a double heterojunction structure.

Further, a partial area of the third semiconductor corresponding to the gate is removed to form the groove structure.

Further, the second semiconductor is formed on the first semiconductor and has a band gap narrower than that of the first semiconductor.

Further, the third semiconductor has a smaller band gap than the second semiconductor, and is easy to remove by using a band-selective photoelectrochemical corrosion (PEC) technology.

Further, the materials of the first semiconductor, the second semiconductor, and the third semiconductor are all selected from group III nitrides, but are not limited thereto.

For example, the material of the third semiconductor includes a group III nitride containing In, and the doping concentration of Mg gradually increases in a direction away from the second semiconductor.

Preferably, the In-containing group III nitride includes In _x Ga _1-x N, 0.01≤x≤0.02.

Further, the third semiconductor is a Mg-doped p-type semiconductor, wherein the Mg doping concentration is 1×10 ¹⁷ cm ^-3 to 1×10 ²⁰ cm ^-3 .

For example, the material of the second semiconductor includes u-GaN, p-GaN, etc., and is not limited thereto.

For example, the material of the first semiconductor includes AlGaN, etc., and is not limited thereto.

Further, the gate structure includes a gate and a gate dielectric layer, the gate is at least partially disposed in the groove structure, and the gate dielectric layer is at least disposed between the gate and the groove wall of the groove structure Moreover, the gate and the gate dielectric layer cooperate with the second semiconductor remaining in the region under the gate to form a metal-insulator-semiconductor structure.

Preferably, the material of the gate dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, etc., and is not limited thereto.

Further, the HEMT device further includes a source electrode and a drain electrode. The source electrode and the drain electrode form an ohmic contact with the double heterojunction structure, especially the third semiconductor therein, and the source electrode and the drain electrode It can be electrically connected through the first hole channel and the second hole channel.

Further, an insertion layer is also provided between the first semiconductor and the second semiconductor. Preferably, the material of the insertion layer includes AlN, etc., and is not limited thereto.

Further, the first semiconductor is formed on a buffer layer, and the buffer layer is formed on a substrate. Preferably, the material of the buffer layer includes GaN, etc., and is not limited thereto.

Further, a nucleation layer is also distributed between the buffer layer and the substrate. Preferably, the material of the nucleation layer includes AlN, etc., and is not limited thereto.

The structure of a typical HEMT device in the above embodiments of the present application can be referred to as shown in FIG. 3.

Another aspect of the embodiments of the present application also provides a method for preparing the III-nitride recessed gate normally-off P-channel HEMT device, which includes:

The first semiconductor, the second semiconductor, and the third semiconductor are sequentially grown on the substrate, and the second semiconductor is made to cooperate with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, and Forming a two-dimensional hole gas in the first heterojunction as a first hole channel, and forming a two-dimensional hole gas in the second heterojunction as a second hole channel;

Removing a local area of the third semiconductor corresponding to the gate to form a groove structure; and

Further, the preparation method may also include:

Further, the etching method with energy band selectivity includes a photo-electrochemical (PEC, Photo-electrochemical) etching technology, and is not limited thereto.

In some more specific embodiments, the preparation method may further include:

Providing a heterojunction including a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor and having a band gap narrower than the first semiconductor, and 2DHG formed in the heterojunction;

Disposing a third semiconductor on the heterojunction, the third semiconductor having a narrower band gap than the second semiconductor, and 2DHG is formed in the second semiconductor;

A mask is set on the third semiconductor, and the third semiconductor exposed from the mask is etched by the band-selective PEC etching technique, and the etching is automatically stopped when it reaches the second semiconductor, thereby A groove structure corresponding to the gate is formed in the third semiconductor; and

Fabricate source, drain, gate and gate dielectrics, so that the gate, gate dielectric and the second semiconductor remaining in the region under the gate form an MIS structure, and the source and drain can pass through the 2DHG electricity Connection, wherein the 2DHG remaining in the second semiconductor in the region under the gate is depleted.

Further, the source and drain are electrically connected by a two-dimensional hole gas in a double heterojunction structure, which includes two-dimensional hole gas formed in the first heterojunction and the second heterojunction .

Specifically, when a certain negative voltage is applied to the gate, the source and the drain can be electrically connected through the double 2DHG in the double heterojunction structure.

Preferably, the preparation method may further include: epitaxially growing a group III nitride containing In on the second semiconductor to form a groove structure.

In some more specific embodiments, the preparation method may include:

Provide a heterojunction comprising a first semiconductor (also can be considered as a barrier layer) and a second semiconductor (also can be considered as a first channel layer), the second semiconductor is formed on the first semiconductor and has a narrower than The band gap of the first semiconductor, 2DHG is formed in the heterojunction;

A mask is set on the second semiconductor, and the surface of the second semiconductor exposed in the mask is grown to form a third semiconductor (which can also be considered as a cap layer or a second channel layer) to form a groove structure; and

The source electrode, the drain electrode, the gate electrode and the gate dielectric are fabricated so that the gate electrode, the gate dielectric and the second semiconductor remaining in the region under the gate form a metal-insulator-semiconductor structure (MIS), and the gate region The 2DHG in the second semiconductor is exhausted.

In the above embodiments of the present application, the first semiconductor, the second semiconductor, and the third semiconductor can be formed by an epitaxial growth method known in the industry, and unless otherwise specified, each operation in the HEMT device preparation process can also be the same. The materials of components known in the art, such as the gate, source, and drain, are also known in the art, so they will not be repeated here.

Another aspect of the embodiments of the present application also provides a method for using the grooved gate normally-off P-channel HEMT device, which includes: applying a voltage less than the turn-on voltage to the gate of the HEMT device to make the source The electrode and the drain are electrically connected through a two-dimensional hole gas (double 2DHG in a double heterojunction structure), so that the HEMT device is turned on; or, a voltage greater than the turn-on voltage is applied to the gate of the HEMT device to make The two-dimensional hole gas in the region under the gate in the first heterojunction is depleted, so that the HEMT device is turned off.

The technical solution of the present application will be further explained below in conjunction with embodiments. The various raw materials and equipment used in the following embodiments can be purchased from the market, and if not specifically stated, the epitaxial growth process, etching process, etc. used therein can be implemented in a well-known manner in the art.

Embodiment 1 This embodiment provides a D-2DHG groove gate normally-off HEMT based on the polarization effect, which includes a GaN buffer layer, an AlGaN barrier layer (i.e., the first semiconductor), and a GaN channel that are sequentially grown on a substrate. Layer (ie the second semiconductor) and the InGaN channel layer (ie the third semiconductor), where the GaN channel layer and the AlGaN barrier layer form a first heterojunction, and a 2DHG, GaN channel is formed in the first heterojunction The layer and the InGaN channel layer form a second heterojunction, and 2DHG is also formed in the second heterojunction. The region corresponding to the gate in the InGaN channel layer is removed to form a groove structure, and the groove structure is arranged in cooperation with the gate structure. The gate structure includes a gate electrode and a gate dielectric layer. The gate electrode is partially arranged in the groove structure. The gate dielectric layer is arranged at least between the gate electrode and the groove wall of the groove structure. The AlGaN barrier layer remaining in the region under the gate cooperates to form a metal-insulator-semiconductor structure, which can deplete the two-dimensional hole gas corresponding to the region under the gate in the first heterojunction. The InGaN channel layer also forms ohmic contacts with the source and drain, so that the source and the drain can be electrically connected through the 2DHG in the double heterojunction structure of the HEMT.

Further, referring to FIG. 4, the preparation method of the HEMT may include the following steps:

(1) GaN buffer layer and AlGaN barrier layer ( That is, the first semiconductor), the GaN channel layer (ie, the second semiconductor), the InGaN channel layer (ie, the third semiconductor), where the GaN channel layer and the AlGaN barrier layer form a heterojunction, and the heterojunction 2DHG is formed;

(2) At least with a metal mask or an insulating dielectric layer mask, the InGaN (that is, the third semiconductor) in the gate area is etched away by the PEC etching technique of band selection, and the GaN layer is etched to stop, forming a recess Slot structure

(3) Remove the etch mask, and deposit a dielectric layer on the surface of the groove structure by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD);

(4) Reactive ion etching RIE, inductively coupled plasma etching ICP and other dry etching, wet etching or a combination of dry and wet etching are used to etch the source and drain regions to expose The InGaN (third semiconductor) layer aims to form a good ohmic contact between the source and drain and the heterojunction. Using electron beam evaporation EB or magnetron sputtering Sputter and other metal deposition methods, the source and drain regions are respectively fabricated in the etched source and drain regions, and the grid is fabricated in the gate region.

As an optional alternative, in the foregoing steps (1)-(2), the AlGaN barrier layer and the GaN channel layer can be formed with a long length, and then a patterned mask is set on the GaN channel layer to make the GaN trench The area of the channel layer surface except for the area corresponding to the gate structure is exposed, and then the InGaN channel layer is grown to form a groove structure in the InGaN channel layer, and then the operations of steps (3), (4), etc. can be continued .

When the HEMT is in use, when the gate-source voltage V _{GS is} greater than the threshold voltage V _TH (V _GS ＜V _TH ), the device is in the off state; when the gate-source voltage is less than the threshold voltage (V _GS ＞V _TH ), The device is in the on state.

Further, Fig. 5a and Fig. 5b respectively show the device transfer characteristic curve of the simulation simulation embodiment 1, V _ds =-5V, wherein Fig. 5a corresponds to the linear coordinate, and Fig. 5b corresponds to the logarithmic coordinate. FIG. 6 shows the output characteristic curve of the device of the simulation simulation embodiment 1. FIG. The parameters used in the corresponding HEMT device samples in Figure 5a, Figure 5b and Figure 6 are set as follows: the barrier layer is 40nm thick Al _0.23 Ga _0.77 N, the first channel layer is 10nm thick GaN, and the second channel layer is 40nm thick In _0.07 Ga _0.93 N; In the simulation, a 5nm thick Al ₂ O ₃ dielectric layer is used as the gate dielectric, the gate is set to a Ti metal work function, and the specific contact resistance of the source and drain ohmic contacts is set to 0.0001Ω·cm ² . Simulation results: device threshold voltage -0.7V, subthreshold swing 115mV/decade, on/off state current ratio 10 ⁸ , output current 107.4Ω·mm@V _gs =-6V, V _ds =-5V.

It should be understood that the above-mentioned embodiments only illustrate the technical ideas and features of the application, and their purpose is to enable those familiar with the technology to understand the content of the application and implement them accordingly, and cannot limit the scope of protection of the application. All equivalent changes or modifications made according to the spirit and essence of this application shall be covered by the scope of protection of this application.

Claims

A III-nitride recessed gate normally-off P-channel HEMT device, which is characterized by comprising a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, and the second semiconductor is respectively connected to the first semiconductor and the third semiconductor. The semiconductors cooperate to form a first heterojunction and a second heterojunction; the first heterojunction and the second heterojunction are respectively formed with a two-dimensional cavity as a first hole channel and a second hole channel. Hole gas; the region of the third semiconductor corresponding to the gate is formed with a groove structure, and the groove structure is arranged in cooperation with the gate structure. The cavitation gas is exhausted.
The III-nitride recessed gate normally-off P-channel HEMT device according to claim 1, wherein: the third semiconductor has a smaller band gap than the second semiconductor; and/or, the third semiconductor The material of the semiconductor includes Group III nitride containing In; preferably, the Group III nitride containing In includes In x Ga 1x N, 0.01≤x≤0.2.
The III-nitride recessed gate normally-off P-channel HEMT device according to claim 1, wherein the third semiconductor is a Mg-doped p-type semiconductor, wherein the Mg doping concentration is 1×10 17 cm -3 to 1×10 20 cm -3 .
The III-nitride recessed gate normally-off P-channel HEMT device according to claim 1, wherein the gate structure includes a gate and a gate dielectric layer, and the gate is at least partially disposed on the In the groove structure, the gate dielectric layer is at least disposed between the gate and the groove wall of the groove structure, and the gate and the gate dielectric layer cooperate with the second semiconductor remaining in the region under the gate to form a metal- Insulator-semiconductor structure.
The III-nitride recessed gate normally-off P-channel HEMT device of claim 1, wherein the HEMT device further comprises a source electrode and a drain electrode, and the source electrode, the drain electrode and the third semiconductor An ohmic contact is formed, and the source and drain can be electrically connected through the first hole channel and the second hole channel.
The III-nitride recessed gate normally-off P-channel HEMT device according to claim 1, wherein the material of the first semiconductor includes AlGaN; and/or the material of the second semiconductor includes GaN And/or, an insertion layer is further provided between the first semiconductor and the second semiconductor, preferably, the material of the insertion layer includes AlN; and/or, the material of the gate dielectric layer includes silicon oxide, nitrogen Silicon or alumina.
The III-nitride recessed gate normally-off P-channel HEMT device according to claim 1, wherein the first semiconductor is formed on a buffer layer, and the buffer layer is formed on a substrate; preferably The material of the buffer layer includes GaN.
7. The method for manufacturing a III-nitride recessed gate normally-off P-channel HEMT device according to any one of claims 1-7, characterized in that it comprises:

The first semiconductor, the second semiconductor, and the third semiconductor are sequentially grown on the substrate, and the second semiconductor is made to cooperate with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, and A two-dimensional hole gas is formed in the first heterojunction as a first hole channel, and a two-dimensional hole gas is formed in the second heterojunction as a second hole channel, and the The third semiconductor corresponding to the partial area of the gate is removed, thereby forming a groove structure,

Alternatively, a first semiconductor and a second semiconductor are sequentially grown on the substrate to form a first heterojunction, and a two-dimensional hole gas is formed in the first heterojunction as the first hole channel, and then A mask is set on the second semiconductor, and then a third semiconductor is grown on the surface of the second semiconductor exposed from the mask to form a second heterojunction, and a two-dimensional hole gas is formed in the second semiconductor as A second hole channel, while forming a groove structure in the region of the third semiconductor corresponding to the gate; and

The source, drain, and gate structures matched with the first heterojunction and the second heterojunction are arranged, and the gate structure is arranged in cooperation with the groove structure, and the structure can be integrated into the second semiconductor The two-dimensional cavity gas in the area below the groove structure is exhausted.
8. The manufacturing method of claim 8, further comprising:

Setting a mask on the third semiconductor, and removing a local area of the third semiconductor distributed under the gate through an etching method with band selectivity, and the etching depth reaches the second semiconductor to form a groove structure;

At least depositing a continuous gate dielectric layer on the groove wall of the groove structure;

Preferably, the etching method with energy band selectivity is a photoelectrochemical etching method;

Preferably, the operation of etching the third semiconductor to form the groove structure automatically stops when it reaches the second semiconductor.
A method for manufacturing a III-nitride grooved gate normally-off P-channel HEMT device, which is characterized in that it comprises:

A heterojunction including a first semiconductor and a second semiconductor is provided, the second semiconductor is formed on the first semiconductor and has a band gap narrower than that of the first semiconductor, and a two-dimensional void is formed in the heterojunction Cavitation

Disposing a third semiconductor on the heterojunction, the third semiconductor having a narrower band gap than the second semiconductor, thereby forming a two-dimensional hole gas in the second semiconductor;

A mask is set on the third semiconductor, and the third semiconductor exposed from the mask is etched by the band-selective PEC etching technique, and the etching is stopped when it reaches the second semiconductor, thereby forming A groove structure corresponding to the gate; and

The source, drain, gate, and gate dielectric are fabricated so that the gate, the gate dielectric and the second semiconductor remaining in the region under the gate form an MIS structure, and the source and drain can pass through the two-dimensional space. The hole gas is electrically connected, wherein the two-dimensional hole gas in the second semiconductor remaining in the region under the gate is depleted.