WO2021237901A1 - Dispositif hemt à canal p de type normalement bloqué de grille rainurée de nitrure de groupe iii et son procédé de fabrication - Google Patents

Dispositif hemt à canal p de type normalement bloqué de grille rainurée de nitrure de groupe iii et son procédé de fabrication Download PDF

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WO2021237901A1
WO2021237901A1 PCT/CN2020/102915 CN2020102915W WO2021237901A1 WO 2021237901 A1 WO2021237901 A1 WO 2021237901A1 CN 2020102915 W CN2020102915 W CN 2020102915W WO 2021237901 A1 WO2021237901 A1 WO 2021237901A1
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semiconductor
gate
heterojunction
channel
hemt device
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Chinese (zh)
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于国浩
张宝顺
张丽
张晓东
宋亮
吴冬东
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中国科学院苏州纳米技术与纳米仿生研究所
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • This application relates to a normally-off P-channel transistor, and in particular to a group III nitride D-2DHG (Double-2dimentional hole gas) groove gate normally-off HEMT based on the polarization effect (High Electron Mobility Transistors) devices and preparation methods thereof belong to the field of semiconductor technology.
  • group III nitride D-2DHG Double-2dimentional hole gas
  • polarization effect High Electron Mobility Transistors
  • Power electronic devices are the core components of power electronic systems.
  • the third-generation wide-bandgap semiconductor materials represented by GaN and SiC have been developed rapidly.
  • GaN has the characteristics of large forbidden band width, high saturation hole drift speed, large critical breakdown electric field, and stable chemical properties.
  • SiC materials GaN has its unique characteristics, such as piezoelectric polarization and spontaneous polarization effects. Due to the polarization effect, the AlGaN/GaN heterojunction structure has high-density and high-mobility two-dimensional electrons.
  • the surface density of 2DEG is about 10 13 cm -2 , and the mobility is higher than 1500 cm 2 /(V ⁇ s).
  • the HEMT prepared with AlGaN/GaN heterojunction enables GaN devices to have low on-resistance and high operating frequency, which can achieve the requirements of high power, higher frequency, smaller volume and higher temperature.
  • the threshold voltage of commercial p-GaN gate HEMT is about +1.5V, and the highest forward gate operating voltage is about 7V, while the threshold voltage of Si-based power switching devices in power systems is generally above 3V, and the forward gate works The voltage can reach 18V.
  • CMOS Complementary Metal Oxide Semiconductor
  • the single chip integrates the most commonly used CMOS (Complementary Metal Oxide Semiconductor) inverter, which has the advantages of low power consumption, high noise tolerance, high logic swing, high input impedance and low input capacitance.
  • the areal density of 2DHG can reach 10 13 , which is more difficult to deplete, which makes it very difficult to realize a normally-off p-channel device with high current density and high switching ratio.
  • the methods to realize normally-off p-channel devices mainly include groove gate, AlGaN cap layer and 2DEG back gate control technology, but these technologies will sacrifice the output current and switching ratio of the device.
  • the grooved gate structure has its unique advantages, such as easy realization in structure, low gate leakage and large gate voltage swing, etc., and it is currently the most popular method to realize p-channel GaN HEMT.
  • the performance of the existing p-channel HEMT devices is far from the theoretical value.
  • the structure of an existing p-channel GaN HEMT device is shown in Figure 1a- Figure 1b.
  • the device adopts a p-GaN cap layer structure doped with two layers of Mg at different concentrations.
  • the device performance is shown in Figure 2a and Figure 2b. As shown, the on-resistance is 400 ⁇ mm, the output current is 5mA/mm, and the on-off ratio is 6 ⁇ 105.
  • the device performance has reached the higher level of the p-channel GaN HEMT devices currently studied, but there is still a long way to go to the theoretical limit of GaN. There is still much room for improvement in the output current, on-resistance and switching ratio of the device.
  • the main purpose of this application is to provide a III-nitride recessed gate normally-off P-channel HEMT device, its preparation method and application, so as to overcome the deficiencies of the prior art.
  • the embodiment of the present application provides a III-nitride recessed gate normally-off P-channel HEMT device, which includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, and the second semiconductor is respectively connected to the first semiconductor.
  • the semiconductor and the third semiconductor cooperate to form a first heterojunction and a second heterojunction; the first heterojunction and the second heterojunction are respectively formed as a first hole channel and a second hole channel
  • the two-dimensional hole gas (2DHG) of the third semiconductor; the region of the third semiconductor corresponding to the gate is formed with a groove structure, and the groove structure is arranged in cooperation with the gate structure, and the gate structure can be The two-dimensional hole gas corresponding to the area under the gate is depleted.
  • the material of the third semiconductor includes a group III nitride containing In, and is formed into a p-type semiconductor by Mg doping.
  • the gate structure includes a gate and a gate dielectric layer, the gate is at least partially disposed in the groove structure, and the gate dielectric layer is disposed at least in the groove of the gate and the groove structure. Between the walls, and the gate and the gate dielectric layer cooperate with the second semiconductor remaining in the region under the gate to form a metal-insulator-semiconductor structure.
  • the embodiment of the present application also provides a method for manufacturing the III-nitride recessed gate normally-off P-channel HEMT device, which includes:
  • the first semiconductor, the second semiconductor, and the third semiconductor are sequentially grown on the substrate, and the second semiconductor is made to cooperate with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, and A two-dimensional hole gas is formed in the first heterojunction as a first hole channel, and a two-dimensional hole gas is formed in the second heterojunction as a second hole channel, and the The third semiconductor corresponding to the partial area of the gate is removed, thereby forming a groove structure,
  • a first semiconductor and a second semiconductor are sequentially grown on the substrate to form a first heterojunction, and a two-dimensional hole gas is formed in the first heterojunction as the first hole channel, and then A mask is set on the second semiconductor, and then a third semiconductor is grown on the surface of the second semiconductor exposed from the mask to form a second heterojunction, and a two-dimensional hole gas is formed in the second semiconductor as A second hole channel, while forming a groove structure in the region of the third semiconductor corresponding to the gate; and
  • the source, drain, and gate structures matched with the first heterojunction and the second heterojunction are arranged, and the gate structure is arranged in cooperation with the groove structure, and the structure can be integrated into the second semiconductor
  • the two-dimensional cavity gas in the area below the groove structure is exhausted.
  • the preparation method further includes:
  • At least a continuous gate dielectric layer is deposited on the groove wall of the groove structure.
  • An embodiment of the present application also provides a method for using the III-nitride recessed gate normally-off P-channel HEMT device, which includes: applying a voltage less than the turn-on voltage to the gate of the HEMT device to make the source
  • the electrode and the drain are electrically connected by a two-dimensional hole gas, so that the HEMT device is turned on; or, a voltage greater than the turn-on voltage is applied to the gate of the HEMT device to make the first heterojunction located in the region under the gate
  • the two-dimensional hole gas is depleted, so that the HEMT device is turned off.
  • the above embodiments of the present application use a double heterojunction structure to achieve a double-layer 2DHG, which can effectively increase the output current of the P-channel HEMT device, reduce the on-resistance, and then combine energy band selection with low etching damage
  • the flexible PEC etching technology removes the narrow band gap material located on the upper layer of the heterojunction to realize the grooved gate structure, which can effectively avoid etching damage, reduce surface state, improve uniformity and repeatability, etc., and significantly improve device performance.
  • This application can effectively realize the optimization of the normally-off characteristic and the conduction characteristic of the P-channel HEMT device.
  • FIG. 1a is a schematic diagram of the material structure of an existing p-channel HEMT device
  • FIG. 1a is a schematic diagram of a recessed gate structure of an existing p-channel HEMT device
  • Fig. 2a and Fig. 2b respectively show the output characteristics, on-resistance and switching ratio of the HEMT device shown in Fig. 1a-1b;
  • FIG. 3 is a schematic structural diagram of a HEMT device in an embodiment of the present application.
  • FIG. 4 is a process flow chart of a manufacturing process of a HEMT device in an embodiment of the present application
  • 5a and 5b respectively show simulation transfer characteristic curves of a HEMT device in linear coordinates and log coordinates in an embodiment of the present application
  • Fig. 6 shows a simulation output characteristic curve of a HEMT device in an embodiment of the present application.
  • One aspect of the embodiments of the present application provides a III-nitride recessed gate normally-off P-channel HEMT device, which includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in sequence, and the second semiconductors are respectively Cooperating with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction; the first heterojunction and the second heterojunction are respectively formed as a first hole channel and a second hole A two-dimensional hole gas in a hole channel; a groove structure is formed in the region of the third semiconductor corresponding to the gate, and the groove structure is arranged in cooperation with the gate structure. Corresponding to the depletion of the two-dimensional hole gas in the area under the gate.
  • first heterojunction and the second heterojunction cooperate to form a double heterojunction structure.
  • the second semiconductor is formed on the first semiconductor and has a band gap narrower than that of the first semiconductor.
  • the third semiconductor has a smaller band gap than the second semiconductor, and is easy to remove by using a band-selective photoelectrochemical corrosion (PEC) technology.
  • PEC photoelectrochemical corrosion
  • the materials of the first semiconductor, the second semiconductor, and the third semiconductor are all selected from group III nitrides, but are not limited thereto.
  • the material of the third semiconductor includes a group III nitride containing In, and the doping concentration of Mg gradually increases in a direction away from the second semiconductor.
  • the In-containing group III nitride includes In x Ga 1-x N, 0.01 ⁇ x ⁇ 0.02.
  • the third semiconductor is a Mg-doped p-type semiconductor, wherein the Mg doping concentration is 1 ⁇ 10 17 cm -3 to 1 ⁇ 10 20 cm -3 .
  • the material of the second semiconductor includes u-GaN, p-GaN, etc., and is not limited thereto.
  • the material of the first semiconductor includes AlGaN, etc., and is not limited thereto.
  • the gate structure includes a gate and a gate dielectric layer, the gate is at least partially disposed in the groove structure, and the gate dielectric layer is at least disposed between the gate and the groove wall of the groove structure Moreover, the gate and the gate dielectric layer cooperate with the second semiconductor remaining in the region under the gate to form a metal-insulator-semiconductor structure.
  • the material of the gate dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, etc., and is not limited thereto.
  • the HEMT device further includes a source electrode and a drain electrode.
  • the source electrode and the drain electrode form an ohmic contact with the double heterojunction structure, especially the third semiconductor therein, and the source electrode and the drain electrode It can be electrically connected through the first hole channel and the second hole channel.
  • an insertion layer is also provided between the first semiconductor and the second semiconductor.
  • the material of the insertion layer includes AlN, etc., and is not limited thereto.
  • the first semiconductor is formed on a buffer layer, and the buffer layer is formed on a substrate.
  • the material of the buffer layer includes GaN, etc., and is not limited thereto.
  • a nucleation layer is also distributed between the buffer layer and the substrate.
  • the material of the nucleation layer includes AlN, etc., and is not limited thereto.
  • FIG. 3 The structure of a typical HEMT device in the above embodiments of the present application can be referred to as shown in FIG. 3.
  • Another aspect of the embodiments of the present application also provides a method for preparing the III-nitride recessed gate normally-off P-channel HEMT device, which includes:
  • the first semiconductor, the second semiconductor, and the third semiconductor are sequentially grown on the substrate, and the second semiconductor is made to cooperate with the first semiconductor and the third semiconductor to form a first heterojunction and a second heterojunction, and Forming a two-dimensional hole gas in the first heterojunction as a first hole channel, and forming a two-dimensional hole gas in the second heterojunction as a second hole channel;
  • the source, drain, and gate structures matched with the first heterojunction and the second heterojunction are arranged, and the gate structure is arranged in cooperation with the groove structure, and the structure can be integrated into the second semiconductor
  • the two-dimensional cavity gas in the area below the groove structure is exhausted.
  • preparation method may also include:
  • At least a continuous gate dielectric layer is deposited on the groove wall of the groove structure.
  • the etching method with energy band selectivity includes a photo-electrochemical (PEC, Photo-electrochemical) etching technology, and is not limited thereto.
  • PEC photo-electrochemical
  • the preparation method may further include:
  • a mask is set on the third semiconductor, and the third semiconductor exposed from the mask is etched by the band-selective PEC etching technique, and the etching is automatically stopped when it reaches the second semiconductor, thereby A groove structure corresponding to the gate is formed in the third semiconductor;
  • Source, drain, gate and gate dielectrics so that the gate, gate dielectric and the second semiconductor remaining in the region under the gate form an MIS structure, and the source and drain can pass through the 2DHG electricity Connection, wherein the 2DHG remaining in the second semiconductor in the region under the gate is depleted.
  • the source and drain are electrically connected by a two-dimensional hole gas in a double heterojunction structure, which includes two-dimensional hole gas formed in the first heterojunction and the second heterojunction .
  • the source and the drain can be electrically connected through the double 2DHG in the double heterojunction structure.
  • the preparation method may further include: epitaxially growing a group III nitride containing In on the second semiconductor to form a groove structure.
  • the preparation method may include:
  • a heterojunction comprising a first semiconductor (also can be considered as a barrier layer) and a second semiconductor (also can be considered as a first channel layer), the second semiconductor is formed on the first semiconductor and has a narrower than The band gap of the first semiconductor, 2DHG is formed in the heterojunction;
  • a mask is set on the second semiconductor, and the surface of the second semiconductor exposed in the mask is grown to form a third semiconductor (which can also be considered as a cap layer or a second channel layer) to form a groove structure; and
  • the source electrode, the drain electrode, the gate electrode and the gate dielectric are fabricated so that the gate electrode, the gate dielectric and the second semiconductor remaining in the region under the gate form a metal-insulator-semiconductor structure (MIS), and the gate region The 2DHG in the second semiconductor is exhausted.
  • MIS metal-insulator-semiconductor structure
  • the first semiconductor, the second semiconductor, and the third semiconductor can be formed by an epitaxial growth method known in the industry, and unless otherwise specified, each operation in the HEMT device preparation process can also be the same.
  • the materials of components known in the art, such as the gate, source, and drain, are also known in the art, so they will not be repeated here.
  • Another aspect of the embodiments of the present application also provides a method for using the grooved gate normally-off P-channel HEMT device, which includes: applying a voltage less than the turn-on voltage to the gate of the HEMT device to make the source
  • the electrode and the drain are electrically connected through a two-dimensional hole gas (double 2DHG in a double heterojunction structure), so that the HEMT device is turned on; or, a voltage greater than the turn-on voltage is applied to the gate of the HEMT device to make
  • the two-dimensional hole gas in the region under the gate in the first heterojunction is depleted, so that the HEMT device is turned off.
  • Embodiment 1 provides a D-2DHG groove gate normally-off HEMT based on the polarization effect, which includes a GaN buffer layer, an AlGaN barrier layer (i.e., the first semiconductor), and a GaN channel that are sequentially grown on a substrate.
  • Layer (ie the second semiconductor) and the InGaN channel layer (ie the third semiconductor) where the GaN channel layer and the AlGaN barrier layer form a first heterojunction, and a 2DHG, GaN channel is formed in the first heterojunction
  • the layer and the InGaN channel layer form a second heterojunction, and 2DHG is also formed in the second heterojunction.
  • the region corresponding to the gate in the InGaN channel layer is removed to form a groove structure, and the groove structure is arranged in cooperation with the gate structure.
  • the gate structure includes a gate electrode and a gate dielectric layer.
  • the gate electrode is partially arranged in the groove structure.
  • the gate dielectric layer is arranged at least between the gate electrode and the groove wall of the groove structure.
  • the AlGaN barrier layer remaining in the region under the gate cooperates to form a metal-insulator-semiconductor structure, which can deplete the two-dimensional hole gas corresponding to the region under the gate in the first heterojunction.
  • the InGaN channel layer also forms ohmic contacts with the source and drain, so that the source and the drain can be electrically connected through the 2DHG in the double heterojunction structure of the HEMT.
  • the preparation method of the HEMT may include the following steps:
  • GaN buffer layer and AlGaN barrier layer That is, the first semiconductor), the GaN channel layer (ie, the second semiconductor), the InGaN channel layer (ie, the third semiconductor), where the GaN channel layer and the AlGaN barrier layer form a heterojunction, and the heterojunction 2DHG is formed;
  • the InGaN (that is, the third semiconductor) in the gate area is etched away by the PEC etching technique of band selection, and the GaN layer is etched to stop, forming a recess Slot structure
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • ALD atomic layer deposition
  • Reactive ion etching RIE, inductively coupled plasma etching ICP and other dry etching, wet etching or a combination of dry and wet etching are used to etch the source and drain regions to expose
  • the InGaN (third semiconductor) layer aims to form a good ohmic contact between the source and drain and the heterojunction.
  • electron beam evaporation EB or magnetron sputtering Sputter and other metal deposition methods the source and drain regions are respectively fabricated in the etched source and drain regions, and the grid is fabricated in the gate region.
  • the AlGaN barrier layer and the GaN channel layer can be formed with a long length, and then a patterned mask is set on the GaN channel layer to make the GaN trench The area of the channel layer surface except for the area corresponding to the gate structure is exposed, and then the InGaN channel layer is grown to form a groove structure in the InGaN channel layer, and then the operations of steps (3), (4), etc. can be continued .
  • the HEMT When the HEMT is in use, when the gate-source voltage V GS is greater than the threshold voltage V TH (V GS ⁇ V TH ), the device is in the off state; when the gate-source voltage is less than the threshold voltage (V GS >V TH ), The device is in the on state.
  • FIG. 6 shows the output characteristic curve of the device of the simulation simulation embodiment 1.
  • the barrier layer is 40nm thick Al 0.23 Ga 0.77 N
  • the first channel layer is 10nm thick GaN
  • the second channel layer is 40nm thick In 0.07 Ga 0.93 N
  • a 5nm thick Al 2 O 3 dielectric layer is used as the gate dielectric
  • the gate is set to a Ti metal work function
  • the specific contact resistance of the source and drain ohmic contacts is set to 0.0001 ⁇ cm 2 .

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  • Junction Field-Effect Transistors (AREA)

Abstract

Sont divulgués un dispositif HEMT à canal P de type normalement bloqué de grille rainurée de nitrure de groupe III et son procédé de fabrication. Le dispositif HEMT comprend une structure à double hétérojonction formée par un premier semi-conducteur, un deuxième semi-conducteur et un troisième semi-conducteur, la structure à double hétérojonction comprenant des gaz de trou bidimensionnel double (2DHG) ; le troisième semi-conducteur a une bande interdite plus petite que celle du deuxième semi-conducteur, la bande interdite étant facilement retirée en utilisant la technologie de corrosion photoélectrochimique (PEC) choisie selon une bande d'énergie, de manière à former une structure de rainure ; et la structure de rainure et une structure d'électrode de grille étant agencées de manière correspondante, de telle sorte qu'un gaz de trou bidimensionnel dans une zone à l'intérieur du second semi-conducteur qui correspond au fond d'une électrode de grille peut être épuisé. Au moyen de la présente demande, un dispositif HEMT à canal P de type normalement bloqué à grille rainurée présentant un fort courant de sortie et une faible résistance à l'état passant peut être efficacement réalisé.
PCT/CN2020/102915 2020-05-28 2020-07-20 Dispositif hemt à canal p de type normalement bloqué de grille rainurée de nitrure de groupe iii et son procédé de fabrication WO2021237901A1 (fr)

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