WO2018032601A1 - Procédé de préparation d'un dispositif hemt à base de gan amélioré - Google Patents

Procédé de préparation d'un dispositif hemt à base de gan amélioré Download PDF

Info

Publication number
WO2018032601A1
WO2018032601A1 PCT/CN2016/102697 CN2016102697W WO2018032601A1 WO 2018032601 A1 WO2018032601 A1 WO 2018032601A1 CN 2016102697 W CN2016102697 W CN 2016102697W WO 2018032601 A1 WO2018032601 A1 WO 2018032601A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
etching
layer
oxygen
hemt
Prior art date
Application number
PCT/CN2016/102697
Other languages
English (en)
Chinese (zh)
Inventor
周宇
钟耀宗
孙钱
冯美鑫
高宏伟
杨辉
Original Assignee
中国科学院苏州纳米技术与纳米仿生研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院苏州纳米技术与纳米仿生研究所 filed Critical 中国科学院苏州纳米技术与纳米仿生研究所
Publication of WO2018032601A1 publication Critical patent/WO2018032601A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to a method for fabricating a High Electron Mobility Transistor (HEMT), and more particularly to a method for preparing an enhanced GaN-based HEMT device.
  • HEMT High Electron Mobility Transistor
  • HEMTs High Electron Mobility Transistors
  • the AlGaN/GaN heterojunction-based HEMTs are depleted (normally open), and this type of device is required for use in circuit-level systems.
  • the negative polarity gate drive circuit is designed to achieve switching control of the device, which greatly increases the complexity and cost of the circuit.
  • the p-type layer is epitaxially grown on the AlGaN barrier layer (unintentionally doped n-type), so that the entire epitaxial wafer range A pn junction is formed therein, and a space charge region (mainly distributed in the barrier layer and the channel layer) effectively depletes the two-dimensional electron gas at the channel.
  • the non-gate region on the epitaxial wafer needs to be etched to restore the depleted two-dimensional electron gas, as shown in FIG. Show.
  • the preparation of the enhanced HEMT based on the trench gate technology is another relatively simple solution.
  • a part of the AlGaN barrier layer under the gate is etched away in the device process, and the barrier layer is formed.
  • the two-dimensional electron gas in the gate region is depleted; and the two-dimensional electron gas concentration in the region between the gate source and the gate drain is maintained at the original level, as shown in FIG.
  • the aforementioned p-type gate technology and trench gate technology all require selective etching, and in the etching process, the former needs to etch a large area of the non-gate, and the latter needs to etch the gate area.
  • Conventional methods generally use high aluminum component etch stop layers (such as AlN) and GaN slow etch and control the etch depth by etch time, but still can not accurately control the etch depth, resulting in over-etching ) or under-etching occurs, which ultimately leads to poor electrical performance of the device.
  • a large number of surface defect states generated during the etching process will seriously affect the on-resistance, dynamic characteristics and threshold voltage stability of the device during operation.
  • the slow etching process requires a long etching time, so the mask material requirements are also high.
  • the main object of the present application is to provide a method for preparing a GaN-based enhanced HEMT device to overcome the deficiencies in the prior art.
  • the technical solution adopted by the present application includes:
  • Embodiments of the present application provide a method for fabricating a GaN-based enhanced HEMT, including: etching a selected region in an epitaxial structure of the HEMT with an etch reagent containing a selected substance, and etching the selected region The selected material in the predetermined region reacts with the selected material until an etching resistant material sufficient to cover the etched surface is formed, thereby preventing etching of the epitaxial structure by the etching reagent, thereby realizing etching automatically Terminate and obtain the desired HEMT device structure.
  • the preparation method includes: performing a sufficient amount of the etching resistant material on the etched surface during etching the selected region with an etch reagent containing the selected substance Aggregation forms an in-situ passivation layer to achieve automatic termination of the etch.
  • the preparation method includes: adjusting an etching parameter in real time according to at least an amount of a selected substance in the selected region and/or a required etching depth, the etching parameter including the etching At least one of the amount of the reagent, the content of the selected substance in the etching reagent, and the etching power to obtain the desired HEMT device structure while automatically completing the etching.
  • the etching reagent is an etching gas.
  • the selected substance is selected from the group consisting of oxygen-containing substances, further preferably an oxygen-containing gas, still more preferably oxygen or ozone or other oxygen-containing gas such as carbon dioxide or nitrogen oxide, and particularly preferably oxygen.
  • the selected material is selected from the group consisting of Al-containing semiconductor materials.
  • the epitaxial structure includes a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, at least when the etching is automatically terminated
  • a groove structure corresponding to the gate electrode is formed in the second semiconductor, and a groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or between the second semiconductor and the first semiconductor.
  • the inner wall of the groove structure is covered with an in-situ passivation layer formed by the accumulation of the sufficient amount of etching resistant material on the etched surface.
  • the epitaxial structure includes a first semiconductor, a second semiconductor formed on the first semiconductor, and a third semiconductor formed on the second semiconductor, wherein the first semiconductor and the second semiconductor cooperate to form a heterostructure
  • the third semiconductor has a conductivity different from that of the second semiconductor.
  • the third semiconductor is removed by etching except for a region corresponding to a region under the gate.
  • the second semiconductor is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface.
  • the GaN-based enhanced HEMT device provided by the present application is simple and easy to operate, can realize precise control of the etching process, effectively protects the electrical characteristics of the HEMT device, and has repeatability, uniformity and stability of the process. Reliable, low cost, and conducive to large-scale implementation.
  • FIG. 1 is a schematic diagram of a prior art fabrication of a p-type gate enhanced HEMT based on a selective etch technique.
  • FIG. 2 is a schematic diagram of an enhanced HEMT based on trench gate technology in the prior art.
  • FIG. 3 is an epitaxial structural diagram of an enhanced HEMT based on a p-GaN/AlGaN/GaN heterojunction in Embodiment 1 of the present application.
  • FIG. 4 is a schematic view showing the structure of the device shown in FIG. 3 after completion of p-GaN gate etching.
  • FIG. 5 is a schematic structural view of the device shown in FIG. 4 after isolation of the active region is completed.
  • Figure 6 is a schematic view showing the structure of the device of Figure 5 after completion of gate metal deposition.
  • Figure 7 is a schematic view showing the structure of the device of Figure 6 after completion of deposition of a passivation layer.
  • FIG. 8 is a schematic structural view of the device shown in FIG. 7 after completion of passivation etching.
  • FIG. 9 is a schematic structural view of the device of FIG. 8 after completion of source-drain ohmic contact and source field plate preparation.
  • Figure 10 is a schematic view showing the structure of the device shown in Figure 9 after the fabrication of the lead electrodes.
  • FIG. 11 is an epitaxial structural diagram of an enhanced HEMT based on a composite p-type layer in Embodiment 3 of the present application.
  • FIG. 12 is a structural diagram of an enhanced HEMT based on a composite p-type layer after completing a chip process in Embodiment 3 of the present application.
  • FIG. 13 is a diagram showing an epitaxial structure of an HEMT based on an AlGaN/GaN heterojunction in Embodiment 4 of the present application.
  • Figure 14 is a structural view of the device of Figure 13 after completion of preparation of source and drain ohmic contacts.
  • Figure 15 is a structural diagram of the device of Figure 14 after isolation of the active region is completed.
  • Figure 16 is a structural view of the device of Figure 15 after completion of deposition of the passivation layer.
  • Figure 17 is a block diagram of the device of Figure 16 after completion of gate fenestration.
  • Figure 18 is a structural view of the device of Figure 17 after etching the trench gate.
  • Figure 19 is a structural view of the device of Figure 18 after completion of deposition of the gate dielectric layer.
  • Figure 20 is a structural view of the device of Figure 19 after completion of gate metal deposition.
  • Figure 21 is a structural view of the device of Figure 20 after completion of source and drain ohmic contact opening.
  • Figure 22 is a structural view of the device of Figure 21 after completion of fabrication of the lead electrode.
  • Figure 23 is a structural view of the device of Figure 13 after completion of gate recess etching.
  • Figure 24 is a structural view of the device of Figure 23 after completion of p-GaN regrowth.
  • Figure 25 is a structural diagram of the device of Figure 24 after completion of p-GaN etching in a non-gate region.
  • Figure 26 is a block diagram of the device of Figure 25 after completion of the entire chip fabrication process.
  • the etching depth of the high aluminum component (such as AlN, etc.) and the slow etching of GaN and the etching depth controlled by the etching time cannot accurately control the etching depth, which is extremely easy to cause.
  • Over-etching or under-etching occurs, which eventually leads to poor electrical performance of the device.
  • a large number of surface defect states generated during the etching process will seriously affect the on-resistance, dynamic characteristics and threshold voltage stability of the device during operation.
  • the slow etching process requires a long etching time, so the mask material requirements are also high.
  • a method for preparing a GaN-based enhanced HEMT includes: etching a selected region in an epitaxial structure of the HEMT with an etch reagent containing a selected substance, and etching the selected region The selected material reacts with the selected material until an etch-resistant material sufficient to cover the etched surface is formed, thereby preventing etching of the epitaxial structure by the etch reagent, thereby achieving automatic termination of the etch, At the same time, the desired HEMT device structure is obtained.
  • the method of preparing includes: ???said sufficient amount of etching resistant material during etching of the selected region with an etch reagent containing the selected material An in-situ passivation layer is formed on the etched surface to achieve automatic termination of the etch.
  • the preparation method includes: adjusting an etching parameter in real time according to at least an amount of a selected substance in the selected region and/or a required etching depth, the etching parameter including at least the engraving At least one of an amount of the etching agent, a content of the selected substance in the etching reagent, and an etching power to obtain a desired HEMT device structure while achieving automatic termination of etching.
  • the etching reagent is an etching gas.
  • the selected substance may be selected from oxygen-containing gases such as oxygen O 2 , ozone O 3 , carbon dioxide CO 2 , nitrogen oxide (NO x ), etc., preferably oxygen.
  • oxygen-containing gases such as oxygen O 2 , ozone O 3 , carbon dioxide CO 2 , nitrogen oxide (NO x ), etc., preferably oxygen.
  • the etching gas contains any one or a mixture of two or more of chlorine gas, nitrogen gas, argon gas, and boron trichloride, and a mixed gas of oxygen.
  • the etching gas may be selected from the group consisting of chlorine gas, a mixed gas of oxygen and nitrogen, chlorine gas, a mixed gas of oxygen and argon, chlorine gas, boron trichloride, a mixed gas of oxygen and nitrogen, or chlorine gas, trichlorination.
  • a mixed gas of boron, oxygen and argon and is not limited thereto.
  • the selected material is selected from the group consisting of Al-containing semiconductor materials.
  • the selected material may be at least selected from AlGaN, AlN, AlInGaN, or AlInN, and is not limited thereto.
  • the etching reaction gas containing oxygen is used to chemically react with the materials such as AlGaN, AlN, AlInGaN, and AlInN in the epitaxial structure of the HEMT to form a strong bond energy and resist etching.
  • Al, Ga Al, Ga-O compound or the like (i.e., the aforementioned etching resistant material, preferably alumina, etc.), thereby effectively and reliably achieving the etching termination and precisely controlling the etching depth.
  • the selective etching of the epitaxial layers of different aluminum components can be realized by controlling the flow rate of the etching mixed gas, the oxygen content, etc., and the selective etching is automatically terminated.
  • the preparation method may further include: removing the etching resistant material covering the etched surface, or setting the etched material on the etched surface to be blunt Layer. More specifically, in this application, after removing the etching resistant material, the passivation layer is coated on the etching surface, or a passivation layer may be further disposed on the etching resistant material covering the etching surface, that is, At least one passivation layer is further coated on the in-situ passivation layer to better ensure device performance.
  • the technical solution of the present application is not only suitable for an epitaxial structure not containing a high aluminum component etch stop layer, but also fully applicable to an epitaxial structure containing an etch stop layer such as AlN, and the etching termination effect is better.
  • the etch stop layer may be distributed at any suitable position in the HEMT epitaxial structure, such as between the barrier layer and the channel layer, between the p-type layer and the barrier layer, and is not limited thereto.
  • the epitaxial structure includes a heterostructure formed mainly by a first semiconductor and a second semiconductor, and the second semiconductor is formed on the first semiconductor, and at least when the etching is automatically terminated, at least Forming a groove structure corresponding to the gate electrode in the second semiconductor, the groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or the second semiconductor and the first semiconductor between.
  • the inner wall of the groove structure is covered with an in-situ passivation layer formed by the formation of the sufficient amount of etching resistant material on the etched surface.
  • a third semiconductor is further formed on the second semiconductor, and the third semiconductor has the same conductivity as the second semiconductor, and when the etching is automatically terminated, a corresponding correspondence is formed in the third semiconductor and the second semiconductor.
  • the groove structure of the gate is further formed on the second semiconductor, and the third semiconductor has the same conductivity as the second semiconductor, and when the etching is automatically terminated, a corresponding correspondence is formed in the third semiconductor and the second semiconductor.
  • the aforementioned conductivity means that the semiconductor is n-type or p-type, and should not be understood as other meanings.
  • an insertion layer may be disposed between the first semiconductor and the second semiconductor, the insertion layer may or may not include the selected material, and a groove bottom surface of the groove structure is distributed to the second semiconductor At the interface with the insertion layer or at a set depth within the insertion layer.
  • the material of the insertion layer comprises AlN.
  • the epitaxial structure includes a first semiconductor, a second semiconductor formed on the first semiconductor, and a third semiconductor formed on the second semiconductor, wherein the first semiconductor and the second semiconductor are formed a heterostructure, the third semiconductor having a conductivity different from that of the second semiconductor, the third semiconductor excluding an area other than a region under the gate (ie, the gate region) when the etching is automatically terminated ( That is, the non-gate regions are all removed by etching.
  • the second semiconductor is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface.
  • the preparation method may further include: first performing an gate region of the second semiconductor (barrier layer) with an etching reagent (eg, an etching gas containing no oxygen) containing no selected substance. Etching, then regrowth the third semiconductor (p-type layer), and then etching the non-gate region of the third semiconductor with an etching reagent containing a selected substance (eg, an oxygen-containing etching gas) Unless the third semiconductor of the gate region.
  • an etching reagent eg, an etching gas containing no oxygen
  • first semiconductor and the second semiconductor have the same conductivity.
  • first semiconductor and the second semiconductor may have the same conductivity, for example, all of which are unintentionally doped n-type.
  • the third semiconductor is p-type or n-type.
  • the third semiconductor may be unintentionally doped n-type; if the HEMT is a p-type gate technology HEMT, the third semiconductor may be p-type.
  • the third semiconductor includes a first material layer and a second material layer formed on the first material layer, the second material layer does not contain the selected material, and the first material layer contains Selecting a material, in the process of etching the third semiconductor by an etch reagent, sequentially adjusting the content of the selected substance in the etch reagent to sequentially realize the second material layer and the first material layer Etching until the in-situ passivation layer is formed to automatically terminate the etch. For example, if it is necessary to etch the second material layer p-GaN/first material layer p-AlGaN, two etching reagents having different oxygen contents or only one etching reagent (in which the oxygen content is adjustable) may be used.
  • the latter is capable of simultaneously etching the second material layer p-GaN/first material layer p-AlGaN by adjusting the oxygen content to a suitable range, but etching the second semiconductor (the first material layer is formed) On the second semiconductor).
  • the third semiconductor includes a first material layer formed on the second semiconductor and a second material layer formed on the first material layer, the first material layer not including the selected a material, wherein the second material layer contains the selected material, and in the process of etching the third semiconductor by an etching reagent, the content of the selected substance in the etching reagent is adjusted, and the first Etching of the two material layers and the first material layer until reaching the interface of the first material layer and the second semiconductor or at a set depth within the second semiconductor, at the second semiconductor surface or the second semiconductor An in-situ passivation layer is formed therein to allow the etching to be automatically terminated.
  • the second material layer is first etched with a first etch reagent, and then the first material layer is etched with a second etch reagent until reaching the first material layer and the second material layer.
  • the selected material is not contained, and the second etching reagent contains the selected substance, or the content of the selected substance in the first etching reagent is lower than the content of the selected substance in the second etching reagent .
  • an etching reagent having an adjustable oxygen content and by adjusting the oxygen content therein, the same effect as the foregoing scheme can be achieved.
  • a stable oxygen-containing etching method including a flow rate of fixing an oxygen-containing etching gas
  • the material of the first semiconductor may include GaN, but is not limited thereto.
  • the material of the second semiconductor may include AlGaN, AlInN, or AlInGaN, but is not limited thereto.
  • an etch stop layer may be disposed between the third semiconductor and the second semiconductor or between the second semiconductor and the first semiconductor, and the etch stop layer includes the selected material, and the etching is automatic Terminating at a set depth in the surface of the etch stop layer or within the etch stop layer.
  • the material of the etch stop layer includes AlN, but is not limited thereto.
  • the material of the third semiconductor includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, or p-AlInGaN, but is not limited thereto.
  • the HEMT device of the present application is a p-gate based HEMT, wherein the p-type semiconductor material is not limited to p-GaN.
  • the present application is also applicable to enhanced HEMTs having other p-type layers, such as p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN, and composite structures thereof.
  • the p-type cap layer contains Al
  • an oxide layer (Al,Ga)O x for example, Al 2 O 3 ) is generated, thereby suppressing further etching, so that p can be used.
  • the material of the first material layer is selected from an Al-containing semiconductor material, preferably from p-AlGaN, p-AlInN, p-InGaN or p-AlInGaN.
  • the material of the second material layer is selected from a semiconductor material containing no Al, preferably p-GaN, but is not limited thereto.
  • the active region structure of the foregoing HEMT includes an AlGaN/AlN/GaN heterojunction, an AlInN/AlN/GaN heterojunction, or an AlInGaN/AlN/GaN heterojunction, but is not limited thereto.
  • the active region structure of the aforementioned HEMT includes a dual channel heterojunction.
  • the substrate material of the HEMT includes silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride or graphene, but is not limited thereto.
  • a method for preparing a GaN-based enhanced HEMT includes:
  • the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, and the second semiconductor having a larger than the first a band gap of the semiconductor, and the second semiconductor comprises an aluminum-containing component;
  • the in-situ passivation layer is mainly formed by agglomeration of an etch-resistant substance formed by the reaction of oxygen and an aluminum-containing component, the selected area corresponding to the gate, and the groove bottom surface of the groove structure is distributed in the Between the set depth in the second semiconductor or between the second semiconductor and the first semiconductor;
  • an electrode is fabricated on the epitaxial structure to obtain the HEMT.
  • a method for preparing a GaN-based enhanced HEMT includes:
  • the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, and a third semiconductor formed on the second semiconductor;
  • the epitaxial structure is etched from the etch window with an etch gas containing oxygen, and in-situ passivation is formed on the inner wall of the recess when the recess structure is etched into the epitaxial structure a layer, the etching is automatically terminated, and the in-situ passivation layer is mainly formed by aggregating an etching resistant substance formed by reacting oxygen with an aluminum-containing substance distributed in the second semiconductor or between the second semiconductor and the first semiconductor, a groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or between the second semiconductor and the first semiconductor;
  • the third semiconductor system functions as a cap layer, and the material thereof may be selected from GaN or the like.
  • preparation method may include:
  • the intercalation layer comprising an aluminum-containing substance
  • the groove bottom surface of the groove structure is distributed on the surface of the insertion layer or the insertion The set depth in the layer.
  • the oxygen content in the etching gas can also be adjusted during the etching of this embodiment.
  • a method for preparing a GaN-based enhanced HEMT includes:
  • the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, the second semiconductor having a larger than the first semiconductor a band gap, a third semiconductor is formed on the second semiconductor, the conductivity of the third semiconductor is different from the second semiconductor, and an aluminum-containing substance or a first portion is distributed between the first semiconductor and the second semiconductor
  • the second semiconductor comprises an aluminum-containing substance
  • Etching the region outside the selected region of the third semiconductor with an etching gas containing oxygen, and between the third semiconductor and the second semiconductor or when the region outside the selected region is etched away Forming an in-situ passivation layer on the surface of the semiconductor, the etching is automatically terminated, and the in-situ passivation layer is mainly formed by aggregation of an etching resistant material formed by reacting oxygen with an aluminum-containing component, the selected region corresponding to the gate ;
  • an electrode is fabricated on the epitaxial structure to obtain the HEMT.
  • preparation method may further include:
  • the etch stop layer comprising an aluminum-containing substance
  • the in-situ passivation layer is formed on the surface of the layer (wherein the in-situ passivation layer is distributed between the third semiconductor and the second semiconductor).
  • the oxygen content in the etching gas can also be adjusted during the etching of this embodiment.
  • preparation method may further include:
  • a source and a drain are then formed on the epitaxial structure.
  • the preparation method may further include: after the etching is automatically terminated, forming a passivation layer on the epitaxial structure, and then performing electrode fabrication.
  • each of the semiconductor layers, the passivation layer, the dielectric layer, and the like in the HEMT epitaxial structure may be formed by physical or chemical methods such as PECVD, MOCVD, ALD, and the like.
  • the preparation process of the HEMT device further includes isolating the active region, and preparing the source, the drain, and the gate by evaporation, sputtering, or the like, and the operations may be performed.
  • the source and the drain may be connected to an epitaxial structure, such as a barrier layer (generally the aforementioned second semiconductor) or a cap layer (generally the foregoing The three semiconductors form an ohmic contact.
  • the gate in the formed HEMT device, may be associated with an epitaxial structure, such as a barrier layer (generally the aforementioned second semiconductor), a p-type layer or a cap layer (generally the foregoing The third semiconductor) forms a Schottky contact or an ohmic contact, or a dielectric layer (such as an alumina material) may be disposed between the gate and the barrier layer, the p-type layer or the cap layer.
  • a barrier layer generally the aforementioned second semiconductor
  • a p-type layer or a cap layer generally the foregoing
  • the third semiconductor forms a Schottky contact or an ohmic contact, or a dielectric layer (such as an alumina material) may be disposed between the gate and the barrier layer, the p-type layer or the cap layer.
  • the material of the source, the drain, and the gate may be made of a metal material such as titanium, tungsten, nickel, gold, or the like, but is not limited thereto.
  • the formed HEMT device may also include or comprise a field plate structure.
  • the substrate material of the formed HEMT device may include silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, graphene, or the like, and is not limited thereto.
  • the HEMT preparation process provided by the present application can realize self-terminating of etching, and can realize precise control of etching depth while ensuring etching without delay of high aluminum component and ensuring that the etching rate is not lowered, and the etching is ensured to the utmost extent.
  • the two-dimensional electron gas in the region is not affected by the etching process, ensuring the electrical characteristics of the device, including output current, dynamic characteristic threshold voltage stability, etc., which greatly reduces the difficulty of implementing the enhanced HEMT by using p-gate technology and trench gate technology. Ensure the repeatability, uniformity and stability of the device process.
  • an in-situ passivation layer can be naturally formed on the surface of the semiconductor in the etching process, and the passivation layer can play a key protective role, thereby effectively reducing the deposition process due to the subsequent passivation layer. Problems such as surface damage and the resulting deterioration in electrical properties of materials and devices (such as increased on-resistance and significant current collapse effects).
  • P-type layer etching During the p-type layer etching process, oxygen can be introduced throughout the process; or oxygen can be introduced at a certain time according to actual needs. Further, the p-type layer may also be a p-AlGaN/p-GaN composite layer. Accordingly, the following Examples 1 to 3 are proposed:
  • MOCVD epitaxial growth of an enhanced HEMT epitaxial structure based on p-GaN/AlGaN/GaN heterojunction based on p-GaN/AlGaN/GaN heterojunction.
  • the p-type layer p-GaN has a thickness of 5 to 300 nm
  • the magnesium doping concentration ranges from 10 18 to 10 21 /cm 3
  • the AlGaN barrier layer has an Al composition x of 10% to 35% and a thickness of 5 ⁇ . 25 nm
  • AlN insertion layer is about 1 nm
  • GaN channel layer is 50 to 200 nm
  • the HEMT epitaxial structure is shown in FIG.
  • p-GaN is etched by ICP (Inductive Coupled Plasma) etching technique, and the mixed gas is chlorine gas/oxygen/nitrogen gas, chlorine gas flow rate is 10 ⁇ 100sccm, oxygen The flow rate is 5% to 80% of the chlorine gas flow rate, the nitrogen flow rate is 15% to 75% of the chlorine gas flow rate, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W to form an oxide layer (Al, Ga). The thickness of O x is about 0.5 to 3 nm. As shown in Figure 4.
  • ICP Inductive Coupled Plasma
  • Ion implantation is carried out by N ion implantation technique, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 12 to 10 14 /cm 2 , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG. 5 .
  • the tungsten (W) metal is deposited by magnetron sputtering to a thickness of 50 to 200 nm, as shown in FIG.
  • the SiN x passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, or LPCVD to a thickness of 50 to 500 nm, as shown in FIG.
  • Source and drain ohmic contact, source field plate preparation Preparation conditions: metal Ti / Al / Ni / Au, thickness of 20nm / 130nm / 50nm / 150nm, annealing conditions of 890 ° C, 30s, nitrogen atmosphere, as shown in Figure 9.
  • MOCVD epitaxial growth of an enhanced HEMT epitaxial structure based on p-GaN/AlGaN/GaN heterojunction based on p-GaN/AlGaN/GaN heterojunction.
  • the p-type layer p-GaN has a thickness of 5 to 300 nm
  • the magnesium doping concentration ranges from 10 18 to 10 21 /cm 3
  • the AlGaN barrier layer has an Al composition x of 10% to 35% and a thickness of 5 ⁇ . 25 nm
  • AlN insertion layer is about 1 nm
  • GaN channel layer is 50 to 200 nm
  • the HEMT epitaxial structure is shown in FIG.
  • P-GaN was etched by ICP etching using photoresist AZ5214 as a mask.
  • the etching gas is etched by chlorine gas/boron trichloride for rapid etching of p-GaN, the flow rate of chlorine gas is 10 to 100 sccm, the flow rate of boron trichloride is 20 to 250 sccm, the pressure of the cavity is 10 to 100 mTorr, and the RF power is 10 to 10. 100W, ICP power 300 ⁇ 2500 W, etching rate 80 ⁇ 400nm / min.
  • the etching gas is switched to chlorine gas/oxygen/nitrogen gas, and the remaining p-GaN is completely etched, the chlorine gas flow rate is 10 to 100 sccm, the oxygen flow rate is 5% to 80% of the chlorine gas flow rate, and the nitrogen gas flow rate is 15% of the chlorine gas flow rate. 75%, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W, and the oxide layer (Al, Ga) O x is formed to have a thickness of about 0.5 to 3 nm.
  • S3 to S8 S3 to S8 in the same manner as in the first embodiment.
  • the device after the completion of the entire chip process is shown in FIG.
  • the p-type layer p-AlGaN has a thickness of 5 to 100 nm
  • the magnesium doping concentration ranges from 10 18 to 10 21 /cm 3
  • the Al composition is 10% to 35%
  • the p-type layer has a p-GaN thickness of 5 ⁇ 300nm
  • magnesium doping concentration range is 10 18 ⁇ 10 21 /cm 3
  • AlGaN barrier layer Al composition x is 10% ⁇ 35%, thickness is 5 ⁇ 25nm
  • AlN insertion layer is about 1nm
  • GaN groove The channel layer is 50-200 nm, and the HEMT epitaxial structure is shown in FIG.
  • P-GaN was etched by ICP etching using photoresist AZ5214 as a mask.
  • the etching gas is etched with chlorine gas/boron trichloride/oxygen to p-AlGaN, the chlorine gas flow rate is 10 to 100 sccm, and the boron trichloride flow rate is 20 to 250 sccm, and the oxygen flow rate is adjusted to be 0. % ⁇ 5%, cavity pressure 10 ⁇ 100mTorr, RF power 10 ⁇ 100W, ICP power 300 ⁇ 2500W, etching rate 80 ⁇ 400nm / min.
  • the etching gas is switched to chlorine gas/oxygen/nitrogen gas, and the remaining p-GaN is completely etched, the chlorine gas flow rate is 10 to 100 sccm, the oxygen flow rate is 5% to 80% of the chlorine gas flow rate, and the nitrogen gas flow rate is 15% of the chlorine gas flow rate. 75%, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W, and the oxide layer (Al, Ga) O x is formed to have a thickness of about 0.5 to 3 nm.
  • S3 to S8 S3 to S8 in the same manner as in the first embodiment.
  • the device after completing the entire chip process is shown in Figure 12.
  • the device process flow is not limited to the process flow described in the foregoing embodiments 1 to 3, and includes a gate first process (gate first).
  • gate first is formed by self-aligned etching), Passivation First (passivation first, etching of p-GaN, passivation layer deposition).
  • Trench etch In the trench gate etch process, selective etching of epitaxial layers of different aluminum components is achieved by adjusting the oxygen content to achieve selective etch termination. Accordingly, the following embodiment 4 is proposed:
  • the AlGaN barrier layer has an Al composition content of 10% to 35%, a thickness of 10 to 35 nm, and an AlN insertion layer thickness of 1 to 2 nm.
  • the GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is as shown in FIG.
  • Source and drain ohmic contact The electron beam evaporation technique was used to prepare a metal Ti/Al/Ni/Au having a thickness of 20 nm/130 nm/50 nm/150 nm.
  • the annealing conditions are 800 to 890 ° C, 30 to 50 s, and a nitrogen atmosphere, as shown in FIG.
  • Ion implantation is performed by N ion implantation technique, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 12 to 10 14 /cm 2 , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG.
  • the SiN x passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, LPCVD, and has a thickness of 50 to 500 nm as shown in FIG.
  • the gate opens.
  • the SiN x was etched by RIE (Reactive Ion Etch) using the photoresist AZ5214 as a mask (1 to 2 ⁇ m) to realize gate opening, as shown in FIG.
  • the photoresist AZ5214 is used as a mask, and etching is performed by ICP etching technology.
  • the etched mixed gas is made of chlorine gas/boron trichloride/oxygen
  • the GaN cap layer and the AlGaN barrier layer are etched and etched and self-terminated in the AlN insertion layer, wherein the chlorine gas flow rate is 10 to 100 sccm, The flow rate of boron chloride is 20-250sccm, and the oxygen flow rate is adjusted to be 0%-3% of the chlorine gas flow rate
  • the cavity pressure is 10-100mTorr
  • the RF power is 50-150W
  • the ICP power is 300-2500W
  • the etching rate is 80-400nm/ Min
  • the oxide layer (Al, Ga) O x is formed to have a thickness of about 0.5 to 3 nm as shown in FIG.
  • gate dielectric layer deposition The photoresist is removed, and the gate dielectric layer Al 2 O 3 is deposited by an ALD (Atom Layer Deposition) technique to a thickness of 2 to 50 nm as shown in FIG.
  • ALD Atom Layer Deposition
  • the device process flow is not limited to the process of etching from the termination of the AlN insertion layer as described in the foregoing Embodiment 4, and may also include etching to terminate in the potential.
  • the trench gate etching is combined with the p-GaN etching: first etching the barrier layer of the gate region (without oxygen), then regenerating the long p-type layer, and finally performing oxygen-containing etching on the non-gate region.
  • the p-type layer of the non-gate region is removed to further increase the threshold voltage of the enhancement device. Accordingly, the following embodiment 5 is proposed:
  • the AlGaN barrier layer has an Al composition content of 10% to 35%, a thickness of 20 to 45 nm, and an AlN insertion layer thickness of 1 to 2 nm.
  • the GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is as shown in FIG.
  • the AlGaN barrier layer is etched by a chlorine gas/boron trichloride mixed gas, wherein the cavity pressure is 10 to 100 mTorr, the RF power is 5 to 150 W, the ICP power is 25 to 500 W, and the etching rate is 5 to 100 nm/min, leaving The gate region AlGaN barrier layer has a thickness of 2 to 16 nm as shown in FIG.
  • the p-type layer p-GaN has a thickness of 5 to 300 nm, and the magnesium doping concentration ranges from 10 18 to 10 21 /cm 3 as shown in FIG.
  • Non-gate region p-type layer etching Using photoresist AZ5214 as a mask, p-GaN is etched by ICP etching technology.
  • the mixed gas is chlorine/oxygen/nitrogen
  • the chlorine gas flow rate is 10 ⁇ 100sccm
  • the oxygen flow rate is 5%-80% of the chlorine gas flow rate.
  • the nitrogen flow rate is 15% to 75% of the chlorine gas flow rate
  • the cavity pressure is 10 to 100 mTorr
  • the RF power is 10 to 100 W
  • the ICP power is 300 to 2500 W.
  • the thickness of the oxide layer (Al, Ga) O x is about 0.5 to 3 nm, as shown in the figure. 25 is shown.
  • S5 to S10 are the same as S3 to S8 of the first embodiment.
  • the device after completing the entire chip fabrication process is shown in FIG.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un procédé de préparation d'un HEMT à base de GaN amélioré, consistant : à graver des régions sélectionnées d'une structure épitaxiale d'un HEMT en utilisant un gaz de gravure contenant de l'oxygène, etc. afin de faire réagir un matériau sélectionné (par exemple, une substance contenant de l'aluminium) dans les régions sélectionnées à l'aide de la substance contenant de l'oxygène jusqu'à ce qu'une substance résistante à la corrosion permettant de recouvrir une surface de gravure soit formée, ce qui permet d'empêcher un réactif de gravure de graver la structure épitaxiale et d'obtenir l'interruption automatique de la gravure et d'obtenir également une structure de dispositif HEMT requise. Au moyen de la présente invention, la commande précise d'une opération de gravure pendant la préparation d'un dispositif HEMT peut être obtenue, les propriétés électriques du dispositif peuvent être garanties, la difficulté de préparation d'un HEMT amélioré à l'aide de technologies telles que la technologie de grille de type p et la technologie de grille de tranchée peut être fortement réduite, et la répétabilité, l'uniformité et la stabilité du processus du dispositif peuvent être assurées. En même temps, pendant le processus de gravure, une couche de passivation peut également être formée naturellement in situ sur la surface de gravure, de telle sorte que des problèmes tels que l'endommagement de la surface provoqués par un processus de dépôt de couche de passivation ultérieur peuvent être efficacement éliminés, ce qui permet d'éliminer à leur tour des problèmes tels que la détérioration des propriétés électriques des matériaux et du dispositif.
PCT/CN2016/102697 2016-08-19 2016-10-20 Procédé de préparation d'un dispositif hemt à base de gan amélioré WO2018032601A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610693110.XA CN107768248A (zh) 2016-08-19 2016-08-19 GaN基增强型HEMT器件的制备方法
CN201610693110.X 2016-08-19

Publications (1)

Publication Number Publication Date
WO2018032601A1 true WO2018032601A1 (fr) 2018-02-22

Family

ID=61196272

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/102697 WO2018032601A1 (fr) 2016-08-19 2016-10-20 Procédé de préparation d'un dispositif hemt à base de gan amélioré

Country Status (2)

Country Link
CN (1) CN107768248A (fr)
WO (1) WO2018032601A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887872A (zh) * 2019-03-29 2019-06-14 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法
CN111653478A (zh) * 2020-03-13 2020-09-11 厦门市三安集成电路有限公司 一种制作增强型氮化镓功率器件的方法
CN113035938A (zh) * 2021-03-12 2021-06-25 浙江集迈科微电子有限公司 多栅GaN器件及制备方法
CN114220738A (zh) * 2021-12-22 2022-03-22 江苏第三代半导体研究院有限公司 一种GaN基半导体器件及其制备方法
CN114334650A (zh) * 2021-12-30 2022-04-12 桂林理工大学 一种p-GaN HEMT中的新结构
CN114361300A (zh) * 2022-01-05 2022-04-15 深圳市思坦科技有限公司 一种微发光二极管制备方法及微发光二极管

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817710A (zh) * 2018-12-29 2019-05-28 英诺赛科（珠海）科技有限公司 高电子迁移率晶体管及其制造方法
CN116391259A (zh) * 2020-11-13 2023-07-04 苏州晶湛半导体有限公司 半导体结构的制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103745922A (zh) * 2013-12-09 2014-04-23 中国电子科技集团公司第五十五研究所 GaN高电子迁移率晶体管复合介质绝缘栅的制造方法
CN104009035A (zh) * 2013-02-26 2014-08-27 飞思卡尔半导体公司 Mishfet及肖特基器件集成
CN104037221A (zh) * 2014-07-02 2014-09-10 西安电子科技大学 一种基于极化效应的复合场板高性能AlGaN/GaN HEMT器件结构及制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101604704B (zh) * 2008-06-13 2012-09-05 西安能讯微电子有限公司 Hemt器件及其制造方法
JP2013004750A (ja) * 2011-06-16 2013-01-07 Fujitsu Ltd 化合物半導体装置及びその製造方法
JP2013074179A (ja) * 2011-09-28 2013-04-22 Fujitsu Ltd 化合物半導体装置及びその製造方法
CN104011867B (zh) * 2011-12-23 2016-12-07 英特尔公司 用于栅极凹进晶体管的iii-n材料结构
JP6253886B2 (ja) * 2013-01-09 2017-12-27 トランスフォーム・ジャパン株式会社 半導体装置及び半導体装置の製造方法
JP6301640B2 (ja) * 2013-11-28 2018-03-28 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6055799B2 (ja) * 2014-07-29 2016-12-27 株式会社豊田中央研究所 半導体装置とその製造方法
CN106486363A (zh) * 2015-09-01 2017-03-08 中国科学院苏州纳米技术与纳米仿生研究所 基于p型层的III族氮化物增强型HEMT及其制备方法
CN106549048B (zh) * 2015-09-16 2019-08-02 中国科学院苏州纳米技术与纳米仿生研究所 基于槽栅技术的iii族氮化物增强型hemt及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009035A (zh) * 2013-02-26 2014-08-27 飞思卡尔半导体公司 Mishfet及肖特基器件集成
CN103745922A (zh) * 2013-12-09 2014-04-23 中国电子科技集团公司第五十五研究所 GaN高电子迁移率晶体管复合介质绝缘栅的制造方法
CN104037221A (zh) * 2014-07-02 2014-09-10 西安电子科技大学 一种基于极化效应的复合场板高性能AlGaN/GaN HEMT器件结构及制作方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887872A (zh) * 2019-03-29 2019-06-14 华南理工大学 用于制备凹槽栅增强型器件的精准刻蚀装置及其刻蚀方法
CN111653478A (zh) * 2020-03-13 2020-09-11 厦门市三安集成电路有限公司 一种制作增强型氮化镓功率器件的方法
CN111653478B (zh) * 2020-03-13 2022-06-28 厦门市三安集成电路有限公司 一种制作增强型氮化镓功率器件的方法
CN113035938A (zh) * 2021-03-12 2021-06-25 浙江集迈科微电子有限公司 多栅GaN器件及制备方法
CN114220738A (zh) * 2021-12-22 2022-03-22 江苏第三代半导体研究院有限公司 一种GaN基半导体器件及其制备方法
CN114220738B (zh) * 2021-12-22 2024-04-30 江苏第三代半导体研究院有限公司 一种GaN基半导体器件及其制备方法
CN114334650A (zh) * 2021-12-30 2022-04-12 桂林理工大学 一种p-GaN HEMT中的新结构
CN114334650B (zh) * 2021-12-30 2024-04-16 桂林理工大学 一种p-GaN HEMT中的新结构
CN114361300A (zh) * 2022-01-05 2022-04-15 深圳市思坦科技有限公司 一种微发光二极管制备方法及微发光二极管

Also Published As

Publication number Publication date
CN107768248A (zh) 2018-03-06

Similar Documents

Publication Publication Date Title
JP6999197B2 (ja) 複合バリア層構造に基づくｉｉｉ族窒化物エンハンスメント型ｈｅｍｔ及びその製造方法
WO2018032601A1 (fr) Procédé de préparation d'un dispositif hemt à base de gan amélioré
WO2020221222A1 (fr) Transistor à haute mobilité d'électrons du type normalement bloqué à tension à seuil élevé et son procédé de préparation
US11888052B2 (en) Semiconductor device and manufacturing method thereof employing an etching transition layer
WO2016141762A1 (fr) Hemt à enrichissement au nitrure iii et procédé de préparation associé
WO2017088253A1 (fr) Dispositif hemt à mode d'enrichissement empêchant l'effet de chute de courant et son procédé de préparation
US20150053921A1 (en) Enhanced switch device and manufacturing method therefor
US10998435B2 (en) Enhancement-mode device and method for manufacturing the same
JP5546104B2 (ja) ＧａＮ系電界効果トランジスタ
WO2017036025A1 (fr) Hemt du type amélioré au nitrure du groupe iii et son procédé de préparation
WO2021237901A1 (fr) Dispositif hemt à canal p de type normalement bloqué de grille rainurée de nitrure de groupe iii et son procédé de fabrication
CN113594036A (zh) Ⅲ族氮化物增强型hemt器件及其制造方法
WO2021035946A1 (fr) Transistor ayant une tension de tenue élevée et une mobilité d'électrons élevée et son procédé de préparation
CN116387246A (zh) p-GaN增强型MIS-HEMT器件及其制备方法
CA3093906C (fr) Dispositif a semiconducteur et son procede de fabrication
CN114121655A (zh) 一种基于增强型器件的自终止刻蚀方法及器件
CN113628962A (zh) Ⅲ族氮化物增强型hemt器件及其制造方法
CN115377215A (zh) 增强型iii-v族半导体元件与其制造方法
JP5460016B2 (ja) 半導体装置及びその製造方法
CN110875379A (zh) 一种半导体器件及其制造方法
CN117133806B (zh) 一种天然超结GaN HEMT器件及其制备方法
WO2022052001A1 (fr) Structure semi-conductrice améliorée et son procédé de fabrication
TWI784460B (zh) 常閉式電晶體與其製造方法
CN108695383B (zh) 实现高频mis-hemt的方法及mis-hemt器件
CN112563136A (zh) 一种氮化镓基功率器件的新型制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16913356

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16913356

Country of ref document: EP

Kind code of ref document: A1