CN109817710A - 高电子迁移率晶体管及其制造方法 - Google Patents

高电子迁移率晶体管及其制造方法 Download PDF

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CN109817710A
CN109817710A CN201811639089.0A CN201811639089A CN109817710A CN 109817710 A CN109817710 A CN 109817710A CN 201811639089 A CN201811639089 A CN 201811639089A CN 109817710 A CN109817710 A CN 109817710A
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semiconductor
grid
metal gates
electron mobility
high electron
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张铭宏
黄敬源
邱汉钦
廖航
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Innovo Secco (zhuhai) Technology Co Ltd
Innoscience Zhuhai Technology Co Ltd
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Innovo Secco (zhuhai) Technology Co Ltd
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Priority to CN201811639089.0A priority Critical patent/CN109817710A/zh
Publication of CN109817710A publication Critical patent/CN109817710A/zh
Priority to CN201980005926.0A priority patent/CN111492490A/zh
Priority to US16/955,091 priority patent/US11563097B2/en
Priority to PCT/CN2019/129379 priority patent/WO2020135770A1/zh
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Abstract

本发明提供一种高电子迁移率晶体管，所述高电子迁移率晶体管包括层叠设置的硅衬底、沟道层、势垒层和栅极，其中，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极顶面上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。本发明还提供一种高电子迁移率晶体管的制造方法。所述高电子迁移率晶体管具有较高的栅极击穿电压以及较低的栅极漏电流。

Description

高电子迁移率晶体管及其制造方法
技术领域
本发明涉及微电子领域，具体地，涉及一种高电子迁移率晶体管以及该高电子迁移率晶体管的制造方法。
背景技术
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)是一种场效应晶体管，如图1所示，高电子迁移率晶体管包括层叠设置的硅衬底110、沟道层120、势垒层130和栅极141，此外，所述高电子迁移率晶体管还包括源极142和漏极143，该源极142和漏极143均与势垒层130相连。其中，栅极141包括半导体栅极141a和金属栅极141b。
在实际应用中发现，高电子迁移率晶体管漏电流较大，且栅极击穿电压较低，从而限制了高电子迁移率晶体管的应用场合。
发明内容
本发明的目的在于提供一种高电子迁移率晶体管以及该高电子迁移率晶体管的制造方法，以至少解决上述技术问题之一。
为了实现上述目的，作为本发明的一个方面，提供一种高电子迁移率晶体管，所述高电子迁移率晶体管包括层叠设置的硅衬底、沟道层、势垒层和栅极，其中，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极顶面上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。
优选地，所述高电子迁移率晶体管还包括绝缘间隔块，所述绝缘间隔块设置在所述半导体栅极的顶面上超出所述金属栅极的底面的部分上，所述绝缘间隔块的底面外边缘与所述半导体栅极的顶面边缘对齐。
优选地，所述绝缘间隔块的材料选自硅的氧化物、硅的氮化物、氮化铝、三氧化二铝中的至少一者。
优选地，所述高电子迁移率晶体管还包括设置在所述金属栅极顶面上的硬掩膜。
优选地，所述沟道层的材料包括GaN，所述势垒层的材料包括AlGaN，所述半导体栅极的材料包括GaN。
优选地，所述高电子迁移率晶体管还包括覆盖所述栅极的钝化层以及设置在所述钝化层背离所述栅极的表面上的源极和漏极，所述源极通过贯穿所述钝化层的源极过孔与所述势垒层相连，所述漏极通过贯穿所述钝化层的漏极过孔与所述势垒层相连。
作为本发明的第二个方面，提供一种高电子迁移率晶体管的制造方法，其中，所述制造方法包括：
提供硅衬底；
形成沟道层；
形成势垒层；
形成栅极，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。
优选地，形成栅极的步骤包括：
形成半导体栅极材料层；
形成金属材料层；
对所述金属材料层进行构图，以获得所述金属栅极；
形成绝缘间隔块材料层；
对所述绝缘间隔块材料层进行构图，以获得环绕所述金属栅极的绝缘间隔块；
以所述金属栅极和所述绝缘间隔块为掩膜，对所述半导体材料层进行刻蚀，以获得所述半导体栅极，所述半导体栅极的顶面边缘与所述绝缘间隔块的底面外边缘对齐。
优选地，对所述金属材料层进行构图，以获得所述金属栅极的步骤包括：
在所述金属材料层上形成硬掩膜，所述硬掩膜的形状与所述金属栅极的形状一致；
对形成有所述硬掩膜的金属材料层进行刻蚀，以获得所述金属栅极。
优选地，对所述金属材料层进行构图，以获得所述金属栅极的步骤还包括：
去除所述金属栅极顶面上的所述硬掩膜。
优选地，所述制造方法还包括在以所述金属栅极和所述绝缘间隔块为掩膜，对所述半导体材料层进行刻蚀，以获得所述半导体栅极的步骤之后进行的以下步骤：
去除所述绝缘间隔块。
优选地，所述制造方法还包括在形成栅极的步骤之后进行的：
形成钝化层；
形成贯穿所述钝化层的源极过孔和漏极过孔；
形成源极和漏极，所述源极通过所述源极过孔与所述势垒层相连，所述漏极通过所述漏极过孔与所述势垒层相连。
在所述高电子迁移率晶体管中，由于金属栅极的底面边缘与半导体栅极的顶面边缘之间存在距离，因此，当金属栅极接收到正向偏压时，半导体栅极边缘的电场较小。并且，在产生漏电流时，漏电流的路径包括两部分，一部分是半导体栅极的顶面上未被金属栅极覆盖的部分，另一部分是半导体栅极的侧面的距离。与图1中所示的高电子迁移率晶体管相比，本发明所提供的高电子迁移率晶体管的栅极的漏电流路径更长。半导体栅极边缘的电场降低、栅极的漏电流路径延长，这就导致了与图1中的高电子迁移率晶体管相比，本发明所提供的高电子迁移率晶体管的栅极漏电流更小、栅极击穿电压更高。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是相关技术中的高电子迁移率晶体管的示意图；
图2是本发明所提供的高电子迁移率晶体管的第一种实施方式的示意图；
图3是本发明所提供的高电子迁移率晶体管的第二种实施方式的示意图；
图4是本发明所提供的高电子迁移率晶体管的第三种实施方式的示意图；
图5是本发明所提供的高电子迁移率晶体管的第四种实施方式的示意图；
图6是本发明所提供的高电子迁移率晶体管的制造方法的流程示意图；
图7是经过步骤S142后获得的结构的示意图；
图8是经过步骤S143后获得的结构的示意图；
图9是经过步骤S144后获得的结构的示意图；
图10是经过步骤S145后获得的结构的示意图；
图11是经过步骤S146后获得的结构的示意图；
图12是图11中的结构形成钝化层后的示意图；
图13是去除绝缘间隔块后再形成钝化层获得的结构的示意图；
图14是经过步骤S143a后获得的结构的示意图；
图15是经过步骤143b后获得的结构的示意图；
图16是经过步骤S143b的步骤后，执行步骤S144获得的结构的示意图；
图17是经过步骤S143b、步骤S144和步骤S145获得的结构的示意图；
图18是在图17中获得的结构上形成钝化层后获得的结构的示意图；
图19是去除图17中获得的结构上的绝缘间隔块后，再形成钝化层后获得的结构的示意图；
图20是本发明实施例与对比例的栅极电压Vg以及栅极漏电流Ig的对比曲线。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
需要解释的是，在对本发明进行描述和解释时，用到的方位词例如“上、下、左、右”、“顶”、“底”等，都是以图2至图5中的方位为参照进行描述的。
经本发明的发明人研究发现，图1中所示的高电子迁移率晶体管漏电流大、击穿电压低的原因在于，当向栅极141施加正向偏压时，会在金属栅极141b的边缘处会产生较高的电场，从而在半导体栅极141a的侧壁上形成漏电路径。发明人发现，漏电流的路径越短、则漏电流较大，也就意味着该高电子迁移率晶体管的栅极击穿电压越低。
有鉴于此，作为本发明的一个方面，提供一种高电子迁移率晶体管，如图2至图5中所示，所述高电子迁移率晶体管包括层叠设置的硅衬底110、沟道层120、势垒层130和栅极141，其中，栅极141包括设置在势垒层130上的半导体栅极141a和设置在半导体栅极141a顶面上的金属栅极141b，金属栅极141b底面的边缘位于半导体栅极141a的顶面的边缘内部。
需要解释的是，半导体栅极141a的顶面是指半导体栅极141a上背离势垒层130的表面。金属栅极141b的底面是指该金属栅极141b与半导体栅极141a相贴合的表面。
由于金属栅极141b的底面边缘与半导体栅极141a的顶面边缘之间存在距离，因此，当金属栅极141b接收到正向偏压时，半导体栅极141a边缘的电场较小。并且，在产生漏电流时，漏电流的路径包括两部分，一部分是半导体栅极141a的顶面上未被金属栅极141b覆盖的部分，另一部分是半导体栅极141a的侧面。与图1中所示的高电子迁移率晶体管相比，本发明所提供的高电子迁移率晶体管的栅极的漏电流路径(只包括半导体栅极的侧面)更长。半导体栅极141a边缘的电场降低、栅极的漏电流路径延长，这就使得与图1中的高电子迁移率晶体管相比，本发明所提供的高电子迁移率晶体管的漏电流更小、栅极击穿电压更高。
在本发明中，对高电子迁移率晶体管的其他结构不做特殊的规定，只要金属栅极141b的底面边缘与半导体栅极141a的顶面之间存在间隔即可。如图3中所示，所述高电子迁移率晶体管还包括绝缘间隔块160，该绝缘间隔块160设置在半导体栅极141a的顶面上超出金属栅极141b的底面的部分上，且绝缘块160的底面的外边缘与半导体栅极141a的顶面边缘对齐。
需要指出的是，绝缘间隔块160环绕金属栅极141b设置。为了形成具有图2至图5中所示的“金属栅极141b的底面边缘位于半导体栅极141a的顶面边缘之内”这种结构的栅极141，可以先在势垒层130的表面依次形成半导体栅极材料层和金属栅极材料层，然后对金属栅极材料层进行构图工艺，获得金属栅极141b，形成绝缘间隔材料层。对绝缘间隔材料层进行构图工艺，以获得绝缘间隔块160，此时，绝缘间隔块160环绕金属栅极141b设置。随后以绝缘间隔块160以及金属栅极141b的组合结构作为自对准的掩膜，对半导体栅极材料层进行构图，可以获得顶面边缘与绝缘间隔块160的底面外边缘对齐的半导体栅极141a。
在本发明中，对绝缘间隔块160的具体结构不做特殊的限定，作为一种实施方式，如图中所示，绝缘间隔块160的表面可以是曲面，在远离半导体栅极141a的方向上，所述绝缘间隔块的横截面积越来越小。绝缘间隔块160可以由无机材料制成，通过正常的刻蚀工艺可以获得表面为曲面的绝缘间隔块160，也就是说，形成绝缘间隔块160的工艺要求并不高，从而可以降低成本。
可以通过等离子刻蚀的方式获得金属栅极141b，具体地，对金属栅极材料层进行构图工艺的步骤可以包括：
在金属栅极材料层上形成硬掩膜；
对形成有所述硬掩膜的金属栅极材料层进行刻蚀，获得所述金属栅极。
为了减少制造所述高电子迁移率晶体管的步骤，可以不去除硬掩膜，直接形成绝缘间隔材料层。由于保留了金属栅极141b上方的硬掩膜170，因此，在对绝缘间隔材料层进行刻蚀的步骤中，硬掩膜170还可以对金属栅极141b进行保护，防止金属栅极141b受损。
在图4中所示的实施方式中，高电子迁移率晶体管中保留了绝缘间隔块160和硬掩膜170，在图5中所示的实施方式中，只保留了硬掩膜170而未保留绝缘间隔块160。
在本发明中，对沟道层120、势垒层130、半导体栅极141a的具体材料均不做特殊的限定。例如，沟道层120的材料可以包括GaN，势垒层130的材料可以包括AlGaN，半导体栅极141a的材料包括GaN。
在本发明中，对绝缘间隔块160的具体材料也不做特殊的限定，例如，可以利用硅的氧化物、硅的氮化物、氮化铝、三氧化二铝中的至少一者形成绝缘间隔块160。
在本发明中，对如何设置高电子迁移率晶体管的源极142以及漏极143并没有特殊的要求。例如，可以在栅极上方形成钝化层150，随后在钝化层150上形成贯穿该钝化层150的源极过孔以及漏极过孔，再形成源极142和漏极143，其中，源极142通过所述源极过孔与势垒层130相连，漏极143通过所述漏极过孔与势垒层130相连。
作为本发明的第二个方面，提供一种高电子迁移率晶体管的制造方法，其中，如图6所示，所述制造方法包括：
在步骤S110中，提供硅衬底；
在步骤S120中，形成沟道层；
在步骤S130中，形成势垒层；
在步骤S140中，形成栅极，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。
利用上述制造方法可以获得本发明所提供的上述高电子迁移率晶体管。需要解释的是，所述硅衬底、所述沟道层、所述势垒层和所述栅极是依次层叠的。
上文中已经详细地介绍了所述高电子迁移率晶体管的工作原理以及有益效果，这里不再赘述。
如上文中所述，栅极包括半导体栅极和金属栅极，相应地，形成栅极的步骤(即，步骤S140)包括：
在步骤S141中，形成半导体栅极材料层141a’(如图7所示)；
在步骤S142中，形成金属材料层141b’(如图7所示)；
在步骤S143中，对所述金属材料层进行构图，以获得所述金属栅极141a(如图8所示)；
在步骤S144中，形成绝缘间隔块材料层160’(如图9所示)；
在步骤S145中，对所述绝缘间隔块材料层进行构图，以获得环绕金属栅极141b的绝缘间隔块160(如图10所示)；
在步骤S146中，以金属栅极141b和绝缘间隔块160为掩膜，对半导体材料层141a’进行刻蚀，以获得半导体栅极141a，该半导体栅极141a的顶面边缘与绝缘间隔块160的底面外边缘对齐(如图11所示)。
通过上述步骤S141至步骤S146可以得到图3中所示的高电子迁移率晶体管。
在本发明中，对如何对金属材料层进行构图、获得金属栅极没有特殊的要求，例如，可以利用湿刻法对金属材料层进行构图，也可以利用干刻法对金属材料层进行构图。
无论是干刻法刻蚀还是湿刻法刻蚀，都需要在金属材料层上形成掩膜。掩膜可以是软掩膜，也可以是硬掩膜。在本发明的一种实施方式中，绝缘间隔块160由无机物制成，因此，需要利用等离子刻蚀方可以获得该绝缘间隔块160，为了对已经成型的金属栅极141b进行保护，优选地，可以在对金属材料层进行构图时，在金属材料层上形成硬掩膜，并且，在形成绝缘间隔块160的过程中，始终保留金属栅极141b顶面上的硬掩膜170。
具体地，步骤S143可以包括：
在步骤S143a中，在所述金属材料层上形成硬掩膜材料层170’(如图14所示)；
在步骤S143b中，对硬掩膜材料层进行构图，获得形状与所述金属栅极的形状一致的硬掩膜170(如图15所示)；
在步骤S143c中，对形成有所述硬掩膜的金属材料层进行刻蚀，以获得金属栅极141b(如图15所示)。
如图16所示，执行了步骤S143c之后，直接进行步骤S144。在执行步骤S145之后，绝缘间隔块160的顶边缘与硬掩膜170的顶表面边缘对齐。
当然，本发明并不限于此，为了获得图3中所示的高电子迁移率晶体管，步骤还S143还可以包括：
在步骤S143d中，去除所述金属栅极顶面上的所述硬掩膜。
执行了步骤S143d后，继续进行步骤S144、步骤S145。
为了形成图2中所示的高电子迁移率晶体管，优选地，所述制造方法还包括在S146之后进行的以下步骤：
在步骤S147中，去除所述绝缘间隔块(如图9所示)。
优选地，所述制造方法还包括在步骤S140之后进行的：
在步骤S150中，形成钝化层150(如图12、图13、图18和图19)；
在步骤S160中，形成贯穿所述钝化层的源极过孔和漏极过孔；
在步骤S170中，形成源极和漏极，所述源极通过所述源极过孔与所述势垒层相连，所述漏极通过所述漏极过孔与所述势垒层相连。
图20是本发明第一种实施方式的高电子迁移率晶体管(即，图2中所示的高电子迁移率晶体管，也是图20中的实施例)的栅极电压Vg与栅极漏电流Ig之间的关系曲线与图1中所示的高电子迁移率晶体管(即，图20中的对比例比)的栅极电压Vg与栅极漏电流Ig之间的关系曲线之间的比较。通过图20可以看出，本发明第一种实施方式的高电子迁移率晶体管栅极漏电流低，且栅极击穿电压也较高。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

1.一种高电子迁移率晶体管，所述高电子迁移率晶体管包括层叠设置的硅衬底、沟道层、势垒层和栅极，其特征在于，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极顶面上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。
2.根据权利要求1所述的高电子迁移率晶体管，其特征在于，所述高电子迁移率晶体管还包括绝缘间隔块，所述绝缘间隔块设置在所述半导体栅极的顶面上超出所述金属栅极的底面的部分上，所述绝缘间隔块的底面外边缘与所述半导体栅极的顶面边缘对齐。
3.根据权利要求2所述的高电子迁移率晶体管，其特征在于，所述绝缘间隔块的材料选自硅的氧化物、硅的氮化物、氮化铝、三氧化二铝中的至少一者。
4.根据权利要求1至3中任意一项所述的高电子迁移率晶体管，其特征在于，所述高电子迁移率晶体管还包括设置在所述金属栅极顶面上的硬掩膜。
5.根据权利要求1至3中任意一项所述的高电子迁移率晶体管，其特征在于，所述沟道层的材料包括GaN，所述势垒层的材料包括AlGaN，所述半导体栅极的材料包括GaN。
6.根据权利要求1至3中任意一项所述的高电子迁移率晶体管，其特征在于，所述高电子迁移率晶体管还包括覆盖所述栅极的钝化层以及设置在所述钝化层背离所述栅极的表面上的源极和漏极，所述源极通过贯穿所述钝化层的源极过孔与所述势垒层相连，所述漏极通过贯穿所述钝化层的漏极过孔与所述势垒层相连。
7.一种高电子迁移率晶体管的制造方法，其特征在于，所述制造方法包括：
提供硅衬底；
形成沟道层；
形成势垒层；
形成栅极，所述栅极包括设置在所述势垒层上的半导体栅极和设置在所述半导体栅极上的金属栅极，所述金属栅极底面的边缘位于所述半导体栅极的顶面的边缘内部。
8.根据权利要求7所述的制造方法，其特征在于，形成栅极的步骤包括：
形成半导体栅极材料层；
形成金属材料层；
对所述金属材料层进行构图，以获得所述金属栅极；
形成绝缘间隔块材料层；
对所述绝缘间隔块材料层进行构图，以获得环绕所述金属栅极的绝缘间隔块；
以所述金属栅极和所述绝缘间隔块为掩膜，对所述半导体材料层进行刻蚀，以获得所述半导体栅极，所述半导体栅极的顶面边缘与所述绝缘间隔块的底面外边缘对齐。
9.根据权利要求8所述的制造方法，其特征在于，对所述金属材料层进行构图，以获得所述金属栅极的步骤包括：
在所述金属材料层上形成硬掩膜，所述硬掩膜的形状与所述金属栅极的形状一致；
对形成有所述硬掩膜的金属材料层进行刻蚀，以获得所述金属栅极。
10.根据权利要求8所述的制造方法，其特征在于，对所述金属材料层进行构图，以获得所述金属栅极的步骤还包括：
去除所述金属栅极顶面上的所述硬掩膜。
11.根据权利要求8至10中任意一项所述的制造方法，其特征在于，所述制造方法还包括在以所述金属栅极和所述绝缘间隔块为掩膜，对所述半导体材料层进行刻蚀，以获得所述半导体栅极的步骤之后进行的以下步骤：
去除所述绝缘间隔块。
12.根据权利要求7至10中任意一项所述的制造方法，其特征在于，所述制造方法还包括在形成栅极的步骤之后进行的：
形成钝化层；
形成贯穿所述钝化层的源极过孔和漏极过孔；
形成源极和漏极，所述源极通过所述源极过孔与所述势垒层相连，所述漏极通过所述漏极过孔与所述势垒层相连。
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