WO2024026738A1

WO2024026738A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024026738A1
Application number: PCT/CN2022/110002
Authority: WO
Inventors: Junhui Ma; Jheng-Sheng You; Ming-Hong Chang
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2024-02-08

Abstract

The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a doped nitride-based semiconductor layer, a first gate electrode and a second gate electrode, and a third gate electrode. The source electrode and a drain electrode are disposed over the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The third gate electrode is disposed over the first and second gate electrodes and makes contact with a portion of the doped nitride-based semiconductor layer between the first and second gate electrodes.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Junhui MA, Jheng-Sheng YOU, Ming-Hong CHANG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having auxiliary gate electrodes.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a doped nitride-based semiconductor layer, a first gate electrode and a second gate electrode, and a third gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The source electrode and a drain electrode are disposed over the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The third gate electrode is disposed over the first and second gate electrodes and makes contact with a portion of the doped nitride-based semiconductor layer between the first and second gate electrodes.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A doped nitride-based semiconductor layer is formed over the second nitride-based semiconductor layer. A first gate electrode and a second gate electrode are formed over the doped nitride-based semiconductor layer. A protection layer is formed to cover the first gate electrode and the second gate electrode. A source electrode and a drain electrode are formed within the protection layer so as to make contact with the second nitride-based semiconductor layer. A portion of the protection layer is formed to expose the first gate electrode and the second gate electrode and to expose a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode. A third gate electrode is formed in contact with the first and second gate electrodes and the exposed portion of the doped nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a first gate electrode and a second gate electrode, a protection layer, and a third gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer. The first gate electrode and the second gate electrode are disposed on the doped nitride-based semiconductor layer and spaced apart from each other. The protection layer covers top surfaces of the second nitride-based semiconductor layer, the doped nitride-based semiconductor layer, and the first gate electrode and the second gate electrode. The third gate electrode is disposed over the first and second gate electrodes and extends from a top surface of the protection layer to a portion of the doped nitride-based semiconductor layer between the first and second gate electrodes.

By the above configuration, the structure of the present disclosure applies gate-first electrodes in combination with a gate-last electrode, so as to improved defects as compared to a gate-first electrode only or a gate-last electrode only.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16,

electrodes

20 and 22, a doped nitride-based semiconductor layer 30,

gate electrodes

32, 34, 36, passivation layers 40 and 42, contact vias 50, and a patterned conductive layer 52.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer 12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 16 can be disposed on/over/above the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

20 and 22 are disposed on the nitride-based semiconductor layer 16. The electrode 20 can make contact with the nitride-based semiconductor layer 16. The electrode 22 can make contact with the nitride-based semiconductor layer 16. Each of the

electrodes

20 and 22 can serve as a source electrode or a drain electrode.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20 and 22 form ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

In some embodiments, each of the

electrodes

20 and 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 30 is disposed over the nitride-based semiconductor layer 30. The doped nitride-based semiconductor layer 30 is located between the

electrodes

20 and 22. The doped nitride-based semiconductor layer 30 may be p-type. The doped nitride-based semiconductor layer 30 is configured to bring the device into enhancement mode. The doped nitride-based semiconductor layer 30 can be a p-type doped III-V semiconductor layer.

The exemplary materials of the doped nitride-based semiconductor layer 30 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.

The

gate electrodes

32 and 34 are disposed on the doped nitride-based semiconductor layer 30. The

gate electrodes

32 and 34 are spaced apart from each other. The doped nitride-based semiconductor layer 30 has a width greater than a distance from the gate electrode 32 to the gate electrode 34.

The

gate electrodes

32 and 34 can serve as gate-first electrodes. For example, the formation of the

gate electrodes

32 and 34 can be prior to the formation of the

electrodes

20 and 22. The

gate electrodes

32 and 34 can serve as etching mark for a gate-last opening.

The exemplary materials of the

electrodes

32 and 34 may include metals or metal compounds. The

electrodes

32 and 34 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the

gate electrodes

32 and 34 are formed by patterning the same conductive layer and thus the

gate electrodes

32 and 34 have the same material.

The gate electrode 36 is disposed over the doped nitride-based semiconductor layer 30. The gate electrode 36 is disposed over the

electrodes

32 and 34. The gate electrode 36 can make contact with a portion of the doped nitride-based semiconductor layer 30, which is located between the

gate electrodes

32 and 34.

The gate electrode 36 can extend along boundaries of the

gate electrodes

32 and 34 so as to form a stepwise profile. For example, the gate electrode 32 has a top surface and a side surface connected to each other so as to form a corner. In some embodiments, the corner has a right angle. The gate electrode 36 can extend along the top surface and the side surface of the gate electrode 32 to cover the corner.

The gate electrode 36 can serve as a gate-last electrode. For example, the formation of the gate electrode 36 can be after the formation of the

electrodes

20 and 22. The gate electrode 36 has a width greater than a distance from the gate electrode 32 to the gate electrode 34.

Generally, a gate-first electrode is a single layer in contact with a p-doped GaN layer, which will have a reduced work function difference resulting from an annealing process for improving ohmic contact of source and drain electrodes. Such the reduced work function difference makes breakdown voltage get less. Alternatively, for a structure applies a gate-last electrode, the gate-last electrode is formed after a removal process of a dielectric layer coving a p-doped GaN layer. During the removal process, the p-doped GaN layer is damaged once misalignment etching occurs.

As compared to a gate-first electrode or a gate-last electrode, the structure in the exemplary illustration of FIG. 1 applies gate-first electrodes in combination with a gate-last electrode, to improve the defects as afore-mentioned.

The

gate electrodes

32 and 34 are islands on the doped nitride-based semiconductor layer 30 rather than a layer which occupies the most area of the doped nitride-based semiconductor layer 30 so these islands can serve as an alignment symbol during a gate opening for the gate electrode 36. Further, as such the islands have the less area than a single layer, it can reduce the affection from the

gate electrodes

32 and 34 to the doped nitride-based semiconductor layer 30, such as element diffusion.

The exemplary materials of the electrode 36 may include metals or metal compounds. The electrode 36 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the gate electrode 36 has at least one material different than the materials of the

gate electrodes

32 and 34.

The passivation layer 40 is disposed over the nitride-based semiconductor layer 16. The passivation layer 40 can cover the doped nitride-based semiconductor layer and the

gate electrodes

32 and 34. The passivation layer 40 can be formed by protection purpose so the passivation layer 40 can be called a protection layer as well.

The passivation layer 40 is formed after the formation of the

gate electrodes

32 and 34 so the passivation layer 40 can further cover top surfaces of the

gate electrodes

32 and 34. The

gate electrodes

32 and 34 have side surfaces opposite each other and are covered by the passivation layer 40. The passivation layer 40 has sidewalls extending upward from the top surfaces of the

gate electrodes

32 and 34.

Since the

gate electrodes

32 and 34 can serve as an alignment symbol during a gate opening for the gate electrode 36, the gate opening can get aligned with the

gate electrodes

32 and 34. As such inner sidewalls of the passivation layer are oblique with respect to top surfaces of the

gate electrodes

32 and 34.

The gate electrode 36 is formed after the formation of the passivation layer 40 so the gate electrode 36 can extend horizontally along a top surface of the passivation layer 40. The gate electrode 36 penetrate the passivation layer 40. More specifically, the gate electrode 36 can extend from a portion of the doped nitride-based semiconductor layer 30 to the top surface of the passivation layer 40, in which the portion of the doped nitride-based semiconductor layer 30 is located between the

gate electrodes

32 and 34. The gate electrode 36 is in contact with the sidewall of the passivation layer 40.

The

electrodes

20 and 22 are formed after the formation of the passivation layer 40 so the

electrodes

20 and 22 can penetrate the passivation layer 40 to make contact with the nitride-based semiconductor layer 16.

The passivation layer 42 covers the

electrodes

20 and 22 and the gate electrode 36. In some embodiments, the passivation layer 42 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer 42 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 42 to remove the excess portions, thereby forming a level top surface. The material of the passivation layer 42 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 140 can include SiN _x, SiO _x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.

The contact vias 50 are disposed within the passivation layer 42. The contact vias 50 can penetrate the passivation layer 42. The contact vias 50 can extend longitudinally to connect to the

electrodes

20 and 22 and the gate electrode 36. The upper surfaces of the contact vias 50 are free from coverage of the passivation layer 42. The exemplary materials of the contact vias 50 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned conductive layer 52 is disposed on/over/above the passivation layer 140 and the contact vias 50. The patterned conductive layer 52 is in contact with the contact vias 50. The patterned conductive layer 52 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 52 can form at least one circuit. Hence, the patterned conductive layer 52 can be served as a patterned circuit layer. The patterned conductive layer 52 can connect with the

electrodes

20 and 22 and the gate electrode 36 by the contact vias 50. An external electronic device can send at least one electronic signal to the semiconductor device 1A by the patterned conductive layer 52, and vice versa. The exemplary materials of the patterned conductive layer 52 can include, for example but are not limited to, conductive materials. The patterned conductive layer 52 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG 2D, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10. A nitride-based semiconductor layer 14 is formed on the buffer layer 12. A nitride-based semiconductor layer 16 is formed on the nitride-based semiconductor layer 14. A doped nitride-based semiconductor layer 30 is formed on/over/above the nitride-based semiconductor layer 16.

Gate electrodes

32 and 34 are formed over the doped nitride-based semiconductor layer 30. In some embodiments, the

gate electrodes

32 and 34 can be formed from a single blanket conductive layer. The single blanket conductive layer can be patterned to obtain the

gate electrodes

32 and 34.

Referring to FIG. 2B, a passivation layer 40 can be formed over the nitride-based semiconductor layer 16. The passivation layer 40 can cover the doped nitride-based semiconductor layer 30 and the

gate electrodes

32 and 34.

Referring to FIG. 2C,

electrodes

20 and 22 are formed within the protection layer 40 so as to make contact with the nitride-based semiconductor layer 16. The forming the

electrode

20 and 22 includes performing an annealing process to improve ohmic contact between the electrode 20 and the nitride-based semiconductor layer 16 and between the electrode 22 and the nitride-based semiconductor layer 16. The annealing process may be performed in a high temperature condition. The

gate electrodes

30 and 32 are entirely covered by the passivation layer 40 at least until the

electrodes

20 and 22 are formed. Since the

gate electrodes

30 and 32 serve as islands rather than a single layer having a greater area, affection to the doped nitride-based semiconductor layer 30 from the

gate electrodes

30 and 32 can get reduced, such as element diffusion.

Referring to FIG. 2D, a portion of the passivation layer 40 between the

gate electrodes

32 and 34 is removed. As such, a portion of the doped nitride-based semiconductor layer 30 between the

gate electrodes

30 and 32 is exposed. Portions of the

gate electrodes

32 and 34 are exposed. In some embodiments, removing the portion of the passivation layer 40 is performed by using an ion etching process. During the ion etching process, the

gate electrodes

32 and 34 can serve as alignment mark, so removal of the target portion of the passivation layer 40 to be removed can get more accurate.

Thereafter, a gate electrode can be formed to make contact with the

gate electrodes

32 and 34 and the exposed portion of the doped nitride-based semiconductor layer 30, thereby completing the gate last formation. Then, a passivation layer, contact vias, and a patterned conductive layer are formed to obtaining the structure as afore above.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that

gate electrodes

32 and 34 of the semiconductor device 1A are replaced by

gate electrodes

32B and 34B. The gate electrode 32B has side surfaces oblique with respect to the top surface of the doped nitride-based semiconductor layer 30. The gate electrode 34B has side surfaces oblique with respect to the top surface of the doped nitride-based semiconductor layer 30.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that

gate electrodes

32, 34, 36 of the semiconductor device 1A are replaced by

gate electrodes

32C, 34C, 36C. The gate electrode 32 has side surfaces oblique with respect to the top surface of the doped nitride-based semiconductor layer 30. The gate electrode 34B has side surfaces oblique with respect to the top surface of the doped nitride-based semiconductor layer 30.

The doped nitride-based semiconductor layer 30 has sidewalls opposite each other (i.e., left and right sidewalls) . A distance from the left sidewall to the gate electrode 32C is different than a distance from the right sidewall to the gate electrode 36B. Such the configuration is related to operation of the semiconductor device 1A as high voltage applied to drain. The gate-drain side faces high electric field so the distance difference can improve the issue. Moreover, potential leakage current at the gate-drain side can be reduced as well.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a source electrode and a drain electrode disposed over the second nitride-based semiconductor layer;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode;

a first gate electrode and a second gate electrode disposed on the doped nitride-based semiconductor layer and spaced apart from each other; and

a third gate electrode disposed over the first and second gate electrodes and making contact with a portion of the doped nitride-based semiconductor layer between the first and second gate electrodes.
The nitride-based semiconductor device any one of the preceding claims, wherein the third gate electrode extends along a top surface and a side surface of the first gate electrode.
The nitride-based semiconductor device any one of the preceding claims, wherein the top surface and the side surface of the first gate electrode are connected to form a corner.
The nitride-based semiconductor device any one of the preceding claims, wherein the side surface of the first gate electrode is oblique with respect to a top surface of the doped nitride-based semiconductor layer.
The nitride-based semiconductor device any one of the preceding claims, further comprising:

a protection layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer, wherein the protection layer further covers top surfaces of the first and second gate electrodes.
The nitride-based semiconductor device of any one of the preceding claims, wherein the protection layer has a sidewall extending upward from the top surface of the first gate electrode.
The nitride-based semiconductor device of any one of the preceding claims, wherein the sidewall of the protection layer is oblique with respect to the top surface of the first gate electrode.
The nitride-based semiconductor device of any one of the preceding claims, wherein the third gate electrode is in contact with the sidewall of the protection layer.
The nitride-based semiconductor device any one of the preceding claims, wherein the doped nitride-based semiconductor layer has first and second sidewalls opposite each other, and a distance from a first sidewall to the first gate electrode is different than a distance from a second sidewall to the second gate electrode.
The nitride-based semiconductor device any one of the preceding claims, wherein the third gate electrode has a width greater than a distance from the first gate electrode to the second gate electrode.
The nitride-based semiconductor device any one of the preceding claims, wherein the doped nitride-based semiconductor layer has a width greater than a distance from the first gate electrode to the second gate electrode.
The nitride-based semiconductor device any one of the preceding claims, wherein the first and second gate electrodes have the same material.
The nitride-based semiconductor device any one of the preceding claims, wherein the third gate electrode has at least one material different than the materials of the first and second gate electrodes.
The nitride-based semiconductor device any one of the preceding claims, further comprising:

a protection layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer, wherein the third gate electrode extends horizontally along a top surface of the protection layer.
The nitride-based semiconductor device any one of the preceding claims, wherein the source electrode and the drain electrode layer penetrate the protection layer to make contact with the second nitride-based semiconductor layer.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a doped nitride-based semiconductor layer over the second nitride-based semiconductor layer;

forming a first gate electrode and a second gate electrode over the doped nitride-based semiconductor layer;

forming a protection layer covering the first gate electrode and the second gate electrode;

forming a source electrode and a drain electrode within the protection layer so as to make contact with the second nitride-based semiconductor layer;

removing a portion of the protection layer to expose the first gate electrode and the second gate electrode and expose a portion of the doped nitride-based semiconductor layer between the first gate electrode and the second gate electrode; and

forming a third gate electrode in contact with the first and second gate electrodes and the exposed portion of the doped nitride-based semiconductor layer.
The method any one of the preceding claims, wherein forming the source electrode and the drain electrode comprises performing an annealing process to improve ohmic contact between the source electrode and the second nitride-based semiconductor layer and between the drain electrode and the second nitride-based semiconductor layer.
The method any one of the preceding claims, wherein the first gate electrode and the second gate electrode are entirely covered by the protection layer at least until the source electrode and the drain electrode are formed.
The method any one of the preceding claims, wherein removing the portion of the protection layer is performed by using an ion etching process.
The method any one of the preceding claims, wherein the first gate electrode and the second gate electrode are formed from a single blanket conductive layer.
A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer;

a first gate electrode and a second gate electrode disposed on the doped nitride-based semiconductor layer and spaced apart from each other;

a protection layer covering top surfaces of the second nitride-based semiconductor layer, the doped nitride-based semiconductor layer, and the first gate electrode and the second gate electrode; and

a third gate electrode disposed over the first and second gate electrodes and extending from a top surface of the protection layer to a portion of the doped nitride-based semiconductor layer between the first and second gate electrodes.
The nitride-based semiconductor device any one of the preceding claims, wherein the first gate electrode and the second gate electrode have side surfaces opposite each other and covered by the protection layer.
The nitride-based semiconductor device any one of the preceding claims, wherein the doped nitride-based semiconductor layer has a width greater than a distance from the first gate electrode to the second gate electrode.
The nitride-based semiconductor device any one of the preceding claims, wherein the third gate electrode extends horizontally along the top surface of the protection layer.
The nitride-based semiconductor device any one of the preceding claims, further comprising:

a source electrode and a drain electrode layer disposed over the second nitride-based semiconductor layer and penetrating the protection layer to make contact with the second nitride-based semiconductor layer.