WO2024092720A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- WO2024092720A1 WO2024092720A1 PCT/CN2022/129876 CN2022129876W WO2024092720A1 WO 2024092720 A1 WO2024092720 A1 WO 2024092720A1 CN 2022129876 W CN2022129876 W CN 2022129876W WO 2024092720 A1 WO2024092720 A1 WO 2024092720A1
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- 238000000034 method Methods 0.000 title claims description 22
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a continuous field plate.
- III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
- devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
- a semiconductor device in accordance with one aspect of the present disclosure, includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, and a field plate.
- the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- the dielectric layer covers the second nitride-based semiconductor layer.
- the field plate is conformally disposed on the dielectric layer and includes a plurality of horizontal portions at different heights and a plurality of connecting portions, in which any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device.
- a method for manufacturing a semiconductor device includes steps as follows.
- a first nitride-based semiconductor layer is formed over a substrate.
- a second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer.
- a dielectric layer is formed to cover the second nitride-based semiconductor layer, in which the dielectric layer is formed to have portions with different widths and heights, respectively.
- a field plate is formed to cover the portions of the dielectric layer, such that the field plate has a plurality of first portions on top surfaces of the portions of the dielectric layer respectively and a plurality of second portions on side surfaces of the dielectric sub-layers, in which any two of the adjacent first portions are connected by the corresponding second portion, such that an entirety of the formed field plate is continuous in a vertical cross-sectional view of the semiconductor device.
- a semiconductor device in accordance with one aspect of the present disclosure, includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source and a drain electrodes, a gate electrode, a dielectric layer, and a field plate.
- the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- the source and the drain electrodes are disposed over the second nitride-based semiconductor layer.
- the gate electrode is disposed over the second nitride-based semiconductor layer and located between the source and the drain electrodes.
- the dielectric layer is disposed over the second nitride-based semiconductor layer and has portions with different heights.
- the field plate extends continuously along a profile of the portions of the dielectric layer along a direction from the gate electrode toward the drain electrode.
- a field plate having horizontal portions and connecting portions can be formed.
- the horizontal portions of the field plates can be disposed at different heights to modulate an electric field distribution in the device. Any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device. Discontinuity inside the field plate can be eliminated due to configuration of the connecting portion; and therefore, probability of occurring breakdown phenomenon can be greatly reduced. Hence, the semiconductor device can have a high breakdown voltage.
- FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
- FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, and FIG. 2H show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure
- FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 1 is a vertical cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure.
- the semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, electrodes 20, 22, a doped nitride-based semiconductor layer 30, a gate electrode 32, a dielectric layer 40, and a field plate 50A.
- the substrate 10 may be a semiconductor substrate.
- the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
- the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
- the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
- the semiconductor device 1A may further include a buffer layer (not shown) .
- the buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12.
- the buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference.
- the buffer layer may include a III-V compound.
- the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
- the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
- the semiconductor device 1A may further include a nucleation layer (not shown) .
- the nucleation layer may be formed between the substrate 10 and a buffer layer.
- the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer.
- the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
- the nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer 12.
- the nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12.
- the exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
- the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
- the exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
- the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV
- the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
- the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively.
- a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
- HEMT high-electron-mobility transistor
- the electrodes 20, 22 are disposed on/over/above the nitride-based semiconductor layer 14.
- the electrodes 20, 22 make contact with the nitride-based semiconductor layer 14.
- the electrode 20 can serve as a source electrode.
- the electrode 22 can serve as a drain electrode.
- the electrode 20 can serve as a source electrode.
- the electrode 22 can serve as a drain electrode.
- the role of the electrodes 20 and 22 depends on the device design.
- the electrodes 20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
- the exemplary materials of the electrodes 20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
- Each of the electrodes 20 and 22 may be a single layer, or plural layers of the same or different composition.
- the electrodes 20 and 22 form ohmic contacts with the nitride-based semiconductor layer 14. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the electrodes 20 and 22.
- the doped nitride-based semiconductor layer 30 is disposed on/over/above the nitride-based semiconductor layer 14.
- the doped nitride-based semiconductor layer 30 makes contact with a top surface of the nitride-based semiconductor layer 14.
- the doped nitride-based semiconductor layer 30 is located between the electrodes 20 and 22.
- the gate electrode 32 is disposed on/over/above the doped nitride-based semiconductor layer 30 and the nitride-based semiconductor layer 14.
- the gate electrode 32 makes contact with the doped nitride-based semiconductor layer 30.
- the doped nitride-based semiconductor layer 30 is located between the gate electrode 32 and the nitride-based semiconductor layer 14.
- the doped nitride-based semiconductor layer 30 and the gate electrode 32 can collectively serve as a gate structure.
- the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 32 is at approximately zero bias.
- the doped nitride-based semiconductor layer 30 may create at least one p-n junction with the nitride-based semiconductor layer 14 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 32 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.
- the semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 32 or a voltage applied to the gate electrode 32 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 114) , the zone of the 2DEG region below the gate electrode 32 is kept blocked, and thus no current flows therethrough.
- a threshold voltage i.e., a minimum voltage required to form an inversion layer below the gate electrode 114
- the doped nitride-based semiconductor layer 30 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.
- the doped nitride-based semiconductor layer 30 can be a p-type doped III-V semiconductor layer.
- the exemplary materials of the doped nitride-based semiconductor layer 30 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
- the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
- the nitride-based semiconductor layer 12 includes undoped GaN and the nitride-based semiconductor layer 14 includes AlGaN, and the doped nitride-based semiconductor layer 30 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.
- the exemplary materials of the gate electrode 32 may include metals or metal compounds.
- the gate electrode 32 may be formed as a single layer, or plural layers of the same or different compositions.
- the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
- field plates are disposed at different positions to modulate an electric field distribution of the device.
- the configuration of the field plates can reduce peak values of an electric field in the device, electric field peak may appear at a corner/end of the field plate. Thus, the breakdown voltage of the device cannot be effectively improved.
- the present disclosure provides a novel structure/manufacturing process.
- Electric field distribution in the device is related to a morphology of the field plate.
- morphology of the field plate 50A is determined by morphology of the dielectric layer 40.
- a dielectric layer 40 is formed under the field plate to-be-formed, in which the dielectric layer 40 can serve as a base layer to determine morphology of the field plate.
- the field plate is prepared to be formed as, for example, a stepped field plate, and thus the dielectric layer 40 should have a stepped profile. Then, the formation of the dielectric layer 40A and the field plate 50A is described as follows.
- an intermediate dielectric layer is formed to cover the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14. Then, in some embodiments, a plurality of etching processes are performed on the intermediate dielectric layer in sequence to remove portions of the intermediate dielectric layer, such that a dielectric layer 40 having portions with different heights is formed. As such, the formed dielectric layer 40 has a stepped profile.
- a blanket conductive layer is formed to covered the dielectric layer 40, such that at least a portion of the blanket conductive layer is conformal with the dielectric layer 40. Then, a patterning process is performed on the blanket conductive layer to remove excess portion of the blanket conductive layer, such that the stepped field plate 50A can be formed.
- the detailed configuration will be fully described as follows.
- the formed dielectric layer 40 can include a plurality of stacked dielectric sub-layers SL1 ⁇ SL5, and each of the dielectric sub-layers SL1 ⁇ SL5, for example, has different widths. Widths of the dielectric sub-layers SL1 ⁇ SL5 decrease along a vertical direction VD.
- the bottom-most dielectric sub-layer SL1 has the widest width in the dielectric sub-layers SL1 ⁇ SL5.
- the bottom-most dielectric sub-layer SL1 makes contact with the nitride-based semiconductor layer 14.
- the dielectric sub-layer SL2 covers a portion of the dielectric sub-layer SL1, and a portion of the dielectric sub-layer SL1 is free from coverage of the dielectric sub-layer SL2.
- a side surface of the dielectric sub-layer SL2 connects a top surface of the dielectric sub- layer SL2 to a top surface of the dielectric sub-layer SL1.
- the dielectric sub-layer SL3 covers a portion of the dielectric sub-layer SL2, and a portion of the dielectric sub-layer SL2 is free from coverage of the dielectric sub-layer SL3.
- a side surface of the dielectric sub-layer SL3 connects a top surface of the dielectric sub-layer SL3 to a top surface of the dielectric sub-layer SL2.
- the dielectric sub-layer SL4 covers a portion of the dielectric sub-layer SL3, and a portion of the dielectric sub-layer SL3 is free from coverage of the dielectric sub-layer SL4.
- a side surface of the dielectric sub-layer SL4 connects a top surface of the dielectric sub-layer SL4 to a top surface of the dielectric sub-layer SL3.
- the dielectric sub-layer SL5 covers a portion of the dielectric sub-layer SL4, and a portion of the dielectric sub-layer SL4 is free from coverage of the dielectric sub-layer SL5.
- a side surface of the dielectric sub-layer SL5 connects a top surface of the dielectric sub-layer SL5 to a top surface of the dielectric sub-layer SL4.
- the top surfaces of the dielectric sub-layers SL1 ⁇ SL5, for example, are horizontal surfaces extending along a horizontal direction HD, and the side surfaces of the dielectric sub-layers SL1 ⁇ SL5 are vertical side surfaces extending along the vertical direction VD.
- the dielectric layer 40 can have portions with different heights. heights of the portions of the dielectric layer are increased along the direction from the gate electrode 32 toward the electrode 22.
- the formed field plate 50A is conformally disposed on the dielectric layer 40.
- the formed field plate 50A includes a plurality of horizontal portions HP1 ⁇ HP4 at different heights and a plurality of connecting portions CP1 ⁇ CP3. Any two of the adjacent horizontal portions are connected by the corresponding connecting portion. Two of the adjacent horizontal portions HP1 ⁇ HP2 are connected by the corresponding connecting portion CP1. Two of the adjacent horizontal portions HP2 ⁇ HP3 are connected by the corresponding connecting portion CP2. Two of the adjacent horizontal portions HP3 ⁇ HP4 are connected by the corresponding connecting portion CP3.
- the horizontal portions HP1 ⁇ HP4 and the connecting portions CP1 ⁇ CP3 are alternatively arranged. As such, an entirety of the formed field plate 50A is continuous in a vertical cross-sectional view of the semiconductor device 1A.
- the formed field plate 50A extends continuously along a profile of the portions of the dielectric layer 40 along a direction from the gate electrode 32 toward the electrode 22.
- the horizontal portions HP1 ⁇ HP4 are located at different positions/heights to modulate electric distribution in the semiconductor device 1A.
- the configuration of the connecting portion CP1 ⁇ CP3 can connect ends portions of two of adjacent horizontal portions, such that discontinuity inside the field plate can be eliminated.
- the electric field near the end portions of the horizontal portions HP1 ⁇ HP4 inside the field plate 50A can be evenly distributed, so as to achieve a more uniform electric field distribution.
- the horizontal portions HP1 ⁇ HP4 of the field plates 50A cover top surfaces of the dielectric sub-layers SL1 ⁇ SL4, respectively.
- the horizontal portions HP1 ⁇ HP4 of the field plates 50A extends horizontally over the portions of the dielectric layer 40, respectively.
- the bottom-most horizontal portion HP1 is the closest horizontal portion in the horizontal portions HP1 ⁇ HP4.
- the bottom-most horizontal portion HP1 is separated from the gate electrode 32 by the dielectric layer 40.
- the connecting portions CP1 ⁇ CP3 of the field plate cover side surfaces of the dielectric sub-layers SL2 ⁇ SL4, respectively.
- Each of the connecting portions CP1 ⁇ CP3 extends between and connects two of the adjacent horizontal portions.
- the connecting portion CP1 extends vertically between and connects two of the adjacent horizontal portions HP1, HP2.
- the connecting portion CP1 extends vertically between and connects two of the adjacent horizontal portions HP1, HP2.
- the connecting portion CP2 extends vertically between and connects two of the adjacent horizontal portions HP2, HP3.
- the connecting portion CP3 extends vertically between and connects two of the adjacent horizontal portions HP3, HP4.
- the material of the dielectric layer 40 can include, for example but are not limited to, dielectric materials.
- the dielectric layer 40 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
- the dielectric layer 40 can include an oxide.
- the dielectric layer 40 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
- the optional dielectric layer can be formed by a single layer or more layers of dielectric materials.
- the exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO x layer, a SiN x layer, a high-k dielectric material (e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc) , or combinations thereof.
- a high-k dielectric material e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc
- the exemplary materials of the field plate 50 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.
- deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
- ALD atomic layer deposition
- PVD physical vapor deposition
- CVD chemical vapor deposition
- MOCVD metal organic CVD
- PECVD plasma enhanced CVD
- LPCVD low-pressure CVD
- plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
- a substrate 10 is provided.
- Nitride-based semiconductor layers 12 and 14 can be formed on/over/above the substrate 10 in sequence by using deposition techniques.
- a doped nitride-based semiconductor layer 30 is formed on/over/above the nitride-based semiconductor layer 14.
- a gate electrode 32 is formed on/over/above the doped nitride-based semiconductor layer 30.
- Electrodes 20, 22 are formed on/over/above the nitride-based semiconductor layer 14. Electrodes 20, 22 are formed at two opposite sides of the gate electrode 32/the doped nitride-based semiconductor layer 30.
- An intermediate dielectric layer IDL is formed on/over/above the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14.
- the intermediate dielectric layer IDL is formed to cover the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14.
- a mask layer ML1 having an opening OG1 is provided on the intermediate dielectric layer IDL, and a portion of the intermediate dielectric layer IDL is exposed by the opening OG1.
- an etching process is performed on the intermediate dielectric layer IDL with the mask layer ML1; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML1 is etched/removed, thereby forming an intermediate dielectric layer IDL’.
- a mask layer ML2 having an opening OG2 is provided on the intermediate dielectric layer IDL’, and a portion of the intermediate dielectric layer IDL’ is exposed by the opening OG2, in which the opening OG2 has a greater width than the opening OG1.
- an etching process is performed on the intermediate dielectric layer IDL’ with the mask layer ML2; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML2 is etched/removed, thereby forming an intermediate dielectric layer IDL”.
- a mask layer ML3 having an opening OG3 is provided on the intermediate dielectric layer IDL’, and a portion of the intermediate dielectric layer IDL” is exposed by the opening OG3, in which the opening OG3 has a greater width than the opening OG2.
- an etching process is performed on the intermediate dielectric layer IDL”’ with the mask layer ML3; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML3 is etched/removed.
- the aforesaid manufacturing processes are carried out one or more times to obtain a lower portion LP of the dielectric layer 40 as shown in the FIG. 1.
- the lower portion LP of the dielectric layer 40 is formed to have portions with different widths and heights, respectively.
- a blanket conductive layer BCL is formed to cover the lower portion LP of the dielectric layer 40, such that the blanket conductive layer BCL is conformally disposed on the lower portion LP of the dielectric layer 40. Then, a portion of the blanket conductive layer BCL is removed, such that a field plate 50A in the FIG. 1 is formed.
- the field plate 50A is formed to cover portions of the lower portion LP of the dielectric layer 40, such that the field plate 50A has a plurality of horizontal portions HP1 ⁇ HP4 on top surfaces of the portions of the dielectric layer respectively and a plurality of connecting portions CP1 ⁇ CP3 on side surfaces of the portions of the lower portion LP of the dielectric layer 40. After that, an upper portion of the dielectric layer 40 is formed to cover the resulted structure, such that the field plate 50A is embedded in the dielectric layer 40.
- the semiconductor device 1A as shown in FIG. 1 can be obtained.
- FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure.
- the semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50B has horizontal portions HP1 ⁇ HP4, and thicknesses of the horizontal portions HP1 ⁇ HP4 are variable.
- thicknesses of the horizontal portions HP1 ⁇ HP4 increase in sequence (i.e., increasing along a direction from the gate electrode 32 toward the electrode 22) .
- the bottom-most horizontal portion HP1 has the smallest thickness.
- the horizontal portion HP2 has a thickness greater than that of the horizontal portion HP1.
- the horizontal portion HP3 has a thickness greater than that of the horizontal portion HP2.
- the horizontal portion HP4 has a thickness greater than that of the horizontal portion HP3.
- FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure.
- the semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that side surfaces of the dielectric sub-layers SL2 ⁇ SL4 of the dielectric layer 40C can be curved surfaces.
- the field plate 50C formed on the dielectric layer 40C can have connecting portions CP1 ⁇ CP3 conformal with curved side surfaces of the dielectric sub-layers SL2 ⁇ SL4 of the dielectric layer 40C, respectively. That is to say, the connecting portions CP1 ⁇ CP3 of the field plate 50C are curved connecting portions.
- the curved connecting portions CP1 ⁇ CP3 can evenly distribute the stress from an upper portion of the dielectric layer 40C.
- the curved profile can make the electric field distribution free from sharp changing, so as to avoid potential peaks in the distribution.
- FIG. 5 is a vertical cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure.
- the semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50D has a plurality of round corner structures RS.
- An end portion of the connecting portion is connected to an end portion of the horizontal portion, such that a round corner structure RS is formed therebetween.
- Such a configuration can help the electric field near the round corner structure RS to be more evenly distributed.
- FIG. 6 is a vertical cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure.
- the semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the semiconductor device 1E can have electrode structures 20E, 22E.
- the electrode structure 20E has an electrode 202 and an electrode pad 204.
- the electrode 202 is disposed on/over/above the nitride-based semiconductor layer 14.
- the electrode 202 makes contact with the nitride-based semiconductor layer 14.
- the electrode pad 204 is disposed on/over/above the electrode 202.
- the electrode contact/pad 204 makes contact with the electrode 202.
- the electrode contact/pad 204 has a width greater than that of the electrode 202.
- the electrode structure 22E can have the similar configuration with the electrode structure 20E.
- a bottom surface BS of the electrode contact/pad 204 is substantially coplanar with a bottom surface of one of the horizontal portions, for example, horizontal portion HP2 of the field plate 50. Heights of the electrode contact/pad 204 and the electrode contact/pad 224 are substantially the same. By such a configuration, the horizontal portion HP2 of the field plate 50, the electrode contact/pad 204 and the electrode contact/pad 224 can be manufactured in the same manufacturing process, which is advantageous to further reduce the manufacturing cost.
- the material of the electrode contacts/pads 204/224 can be similar or identical with the material of the electrodes 20 and 22.
- FIG. 7 is a vertical cross-sectional view of a semiconductor device 1F according to some embodiments of the present disclosure.
- the semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50F has a plurality of horizontal portions HP1 ⁇ HP3 and a plurality of connecting portions CP1 ⁇ CP2.
- Each of the connecting portions CP1, CP2 extends inclinedly to connect corresponding two of adjacent the horizontal portions.
- the connecting portions CP1 extends inclinedly to connect two of adjacent the horizontal portions HP1, HP2, and the connecting portions CP2 extends inclinedly to connect two of adjacent the horizontal portions HP2, HP3.
- Such a configuration can alleviate the stress from an upper portion of the dielectric layer 40F.
- the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
- the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
- a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
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Abstract
The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The dielectric layer covers the second nitride-based semiconductor layer. The field plate is conformally disposed on the dielectric layer and includes a plurality of horizontal portions at different heights and a plurality of connecting portions, in which any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device.
Description
Inventors: Xiao ZHANG; Lijie ZHANG
Field of the Disclosure:
The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a continuous field plate.
Background of the Disclosure:
In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
Summary of the Disclosure:
In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The dielectric layer covers the second nitride-based semiconductor layer. The field plate is conformally disposed on the dielectric layer and includes a plurality of horizontal portions at different heights and a plurality of connecting portions, in which any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device.
In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A dielectric layer is formed to cover the second nitride-based semiconductor layer, in which the dielectric layer is formed to have portions with different widths and heights, respectively. A field plate is formed to cover the portions of the dielectric layer, such that the field plate has a plurality of first portions on top surfaces of the portions of the dielectric layer respectively and a plurality of second portions on side surfaces of the dielectric sub-layers, in which any two of the adjacent first portions are connected by the corresponding second portion, such that an entirety of the formed field plate is continuous in a vertical cross-sectional view of the semiconductor device.
In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source and a drain electrodes, a gate electrode, a dielectric layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The source and the drain electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and located between the source and the drain electrodes. The dielectric layer is disposed over the second nitride-based semiconductor layer and has portions with different heights. The field plate extends continuously along a profile of the portions of the dielectric layer along a direction from the gate electrode toward the drain electrode.
By the above configuration, in the present disclosure, a field plate having horizontal portions and connecting portions can be formed. The horizontal portions of the field plates can be disposed at different heights to modulate an electric field distribution in the device. Any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device. Discontinuity inside the field plate can be eliminated due to configuration of the connecting portion; and therefore, probability of occurring breakdown phenomenon can be greatly reduced. Hence, the semiconductor device can have a high breakdown voltage.
Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, and FIG. 2H show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and
FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
FIG. 1 is a vertical cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, electrodes 20, 22, a doped nitride-based semiconductor layer 30, a gate electrode 32, a dielectric layer 40, and a field plate 50A.
The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a buffer layer (not shown) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In
xAl
yGa
(1–x–y) N where x+y ≤ 1, Al
xGa
(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In
xAl
yGa
(1–x–y) N where x+y ≤ 1, Al
yGa
(1–y) N where y ≤ 1.
The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
The electrodes 20, 22 are disposed on/over/above the nitride-based semiconductor layer 14. The electrodes 20, 22 make contact with the nitride-based semiconductor layer 14. In some embodiments, the electrode 20 can serve as a source electrode. In some embodiments, the electrode 22 can serve as a drain electrode. In some embodiments, the electrode 20 can serve as a source electrode. In some embodiments, the electrode 22 can serve as a drain electrode. The role of the electrodes 20 and 22 depends on the device design.
In some embodiments, the electrodes 20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes 20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the electrodes 20 and 22 may be a single layer, or plural layers of the same or different composition. The electrodes 20 and 22 form ohmic contacts with the nitride-based semiconductor layer 14. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the electrodes 20 and 22.
The doped nitride-based semiconductor layer 30 is disposed on/over/above the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 30 makes contact with a top surface of the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 30 is located between the electrodes 20 and 22.
The gate electrode 32 is disposed on/over/above the doped nitride-based semiconductor layer 30 and the nitride-based semiconductor layer 14. The gate electrode 32 makes contact with the doped nitride-based semiconductor layer 30. The doped nitride-based semiconductor layer 30 is located between the gate electrode 32 and the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 30 and the gate electrode 32 can collectively serve as a gate structure.
In the exemplary illustration of FIG. 1, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 32 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 30 may create at least one p-n junction with the nitride-based semiconductor layer 14 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 32 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.
Due to such mechanism, the semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 32 or a voltage applied to the gate electrode 32 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 114) , the zone of the 2DEG region below the gate electrode 32 is kept blocked, and thus no current flows therethrough.
In some embodiments, the doped nitride-based semiconductor layer 30 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.
The doped nitride-based semiconductor layer 30 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 30 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 12 includes undoped GaN and the nitride-based semiconductor layer 14 includes AlGaN, and the doped nitride-based semiconductor layer 30 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.
The exemplary materials of the gate electrode 32 may include metals or metal compounds. The gate electrode 32 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
In order to avoid breakdown phenomenon induced by a strong peak electrical field in the device, field plates are disposed at different positions to modulate an electric field distribution of the device. Although the configuration of the field plates can reduce peak values of an electric field in the device, electric field peak may appear at a corner/end of the field plate. Thus, the breakdown voltage of the device cannot be effectively improved.
At least to solve the aforesaid issues, the present disclosure provides a novel structure/manufacturing process.
Electric field distribution in the device is related to a morphology of the field plate. In order to achieve a desired electric field distribution, there is a need to form field plates at different positions. In the present disclosure, morphology of the field plate 50A is determined by morphology of the dielectric layer 40. In order to achieve a desired electric field distribution, there is a need to form field plates at different positions/heights. Prior a step of forming such the field plate, a dielectric layer 40 is formed under the field plate to-be-formed, in which the dielectric layer 40 can serve as a base layer to determine morphology of the field plate. In order to achieve a specific electric field distribution in the semiconductor device 1A, in the embodiment, the field plate is prepared to be formed as, for example, a stepped field plate, and thus the dielectric layer 40 should have a stepped profile. Then, the formation of the dielectric layer 40A and the field plate 50A is described as follows.
In detail, an intermediate dielectric layer is formed to cover the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14. Then, in some embodiments, a plurality of etching processes are performed on the intermediate dielectric layer in sequence to remove portions of the intermediate dielectric layer, such that a dielectric layer 40 having portions with different heights is formed. As such, the formed dielectric layer 40 has a stepped profile.
After that, a blanket conductive layer is formed to covered the dielectric layer 40, such that at least a portion of the blanket conductive layer is conformal with the dielectric layer 40. Then, a patterning process is performed on the blanket conductive layer to remove excess portion of the blanket conductive layer, such that the stepped field plate 50A can be formed. The detailed configuration will be fully described as follows.
Specifically, the formed dielectric layer 40 can include a plurality of stacked dielectric sub-layers SL1~SL5, and each of the dielectric sub-layers SL1~SL5, for example, has different widths. Widths of the dielectric sub-layers SL1~SL5 decrease along a vertical direction VD. The bottom-most dielectric sub-layer SL1 has the widest width in the dielectric sub-layers SL1~SL5. The bottom-most dielectric sub-layer SL1 makes contact with the nitride-based semiconductor layer 14. The dielectric sub-layer SL2 covers a portion of the dielectric sub-layer SL1, and a portion of the dielectric sub-layer SL1 is free from coverage of the dielectric sub-layer SL2. A side surface of the dielectric sub-layer SL2 connects a top surface of the dielectric sub- layer SL2 to a top surface of the dielectric sub-layer SL1. The dielectric sub-layer SL3 covers a portion of the dielectric sub-layer SL2, and a portion of the dielectric sub-layer SL2 is free from coverage of the dielectric sub-layer SL3. A side surface of the dielectric sub-layer SL3 connects a top surface of the dielectric sub-layer SL3 to a top surface of the dielectric sub-layer SL2. The dielectric sub-layer SL4 covers a portion of the dielectric sub-layer SL3, and a portion of the dielectric sub-layer SL3 is free from coverage of the dielectric sub-layer SL4. A side surface of the dielectric sub-layer SL4 connects a top surface of the dielectric sub-layer SL4 to a top surface of the dielectric sub-layer SL3. The dielectric sub-layer SL5 covers a portion of the dielectric sub-layer SL4, and a portion of the dielectric sub-layer SL4 is free from coverage of the dielectric sub-layer SL5. A side surface of the dielectric sub-layer SL5 connects a top surface of the dielectric sub-layer SL5 to a top surface of the dielectric sub-layer SL4. The top surfaces of the dielectric sub-layers SL1~SL5, for example, are horizontal surfaces extending along a horizontal direction HD, and the side surfaces of the dielectric sub-layers SL1~SL5 are vertical side surfaces extending along the vertical direction VD.
In the other point of view, the dielectric layer 40 can have portions with different heights. heights of the portions of the dielectric layer are increased along the direction from the gate electrode 32 toward the electrode 22.
The formed field plate 50A is conformally disposed on the dielectric layer 40. The formed field plate 50A includes a plurality of horizontal portions HP1~HP4 at different heights and a plurality of connecting portions CP1~CP3. Any two of the adjacent horizontal portions are connected by the corresponding connecting portion. Two of the adjacent horizontal portions HP1~HP2 are connected by the corresponding connecting portion CP1. Two of the adjacent horizontal portions HP2~HP3 are connected by the corresponding connecting portion CP2. Two of the adjacent horizontal portions HP3~HP4 are connected by the corresponding connecting portion CP3. The horizontal portions HP1~HP4 and the connecting portions CP1~CP3 are alternatively arranged. As such, an entirety of the formed field plate 50A is continuous in a vertical cross-sectional view of the semiconductor device 1A. The formed field plate 50A extends continuously along a profile of the portions of the dielectric layer 40 along a direction from the gate electrode 32 toward the electrode 22.
In the present disclosure, the horizontal portions HP1~HP4 are located at different positions/heights to modulate electric distribution in the semiconductor device 1A. The configuration of the connecting portion CP1~CP3 can connect ends portions of two of adjacent horizontal portions, such that discontinuity inside the field plate can be eliminated. Thus, the electric field near the end portions of the horizontal portions HP1~HP4 inside the field plate 50A can be evenly distributed, so as to achieve a more uniform electric field distribution.
The horizontal portions HP1~HP4 of the field plates 50A cover top surfaces of the dielectric sub-layers SL1~SL4, respectively. The horizontal portions HP1~HP4 of the field plates 50A extends horizontally over the portions of the dielectric layer 40, respectively. The bottom-most horizontal portion HP1 is the closest horizontal portion in the horizontal portions HP1~HP4. The bottom-most horizontal portion HP1 is separated from the gate electrode 32 by the dielectric layer 40. The connecting portions CP1~CP3 of the field plate cover side surfaces of the dielectric sub-layers SL2~SL4, respectively. Each of the connecting portions CP1~CP3 extends between and connects two of the adjacent horizontal portions. For example, the connecting portion CP1 extends vertically between and connects two of the adjacent horizontal portions HP1, HP2. The connecting portion CP1 extends vertically between and connects two of the adjacent horizontal portions HP1, HP2. The connecting portion CP2 extends vertically between and connects two of the adjacent horizontal portions HP2, HP3. The connecting portion CP3 extends vertically between and connects two of the adjacent horizontal portions HP3, HP4.
The material of the dielectric layer 40 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 40 can include, for example but are not limited to, SiN
x, SiO
x, Si
3N
4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 40 can include an oxide. In some embodiments, the dielectric layer 40 can be a multi-layered structure, such as a composite dielectric layer of Al
2O
3/SiN, Al
2O
3/SiO
2, AlN/SiN, AlN/SiO
2, or combinations thereof.
In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO
x layer, a SiN
x layer, a high-k dielectric material (e.g., HfO
2, Al
2O
3, TiO
2, HfZrO, Ta
2O
3, HfSiO
4, ZrO
2, ZrSiO
2, etc) , or combinations thereof.
The exemplary materials of the field plate 50 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.
Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, and FIG. 2H as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to FIG. 2A, a substrate 10 is provided. Nitride-based semiconductor layers 12 and 14 can be formed on/over/above the substrate 10 in sequence by using deposition techniques. A doped nitride-based semiconductor layer 30 is formed on/over/above the nitride-based semiconductor layer 14. A gate electrode 32 is formed on/over/above the doped nitride-based semiconductor layer 30. Electrodes 20, 22 are formed on/over/above the nitride-based semiconductor layer 14. Electrodes 20, 22 are formed at two opposite sides of the gate electrode 32/the doped nitride-based semiconductor layer 30. An intermediate dielectric layer IDL is formed on/over/above the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14. The intermediate dielectric layer IDL is formed to cover the electrodes 20, 22, the gate electrode 32, the doped nitride-based semiconductor layer 30, and the nitride-based semiconductor layer 14.
Referring to FIG. 2B, a mask layer ML1 having an opening OG1 is provided on the intermediate dielectric layer IDL, and a portion of the intermediate dielectric layer IDL is exposed by the opening OG1.
Referring to FIG. 2C, an etching process is performed on the intermediate dielectric layer IDL with the mask layer ML1; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML1 is etched/removed, thereby forming an intermediate dielectric layer IDL’.
Referring to FIG. 2D, a mask layer ML2 having an opening OG2 is provided on the intermediate dielectric layer IDL’, and a portion of the intermediate dielectric layer IDL’ is exposed by the opening OG2, in which the opening OG2 has a greater width than the opening OG1.
Referring to FIG. 2E, an etching process is performed on the intermediate dielectric layer IDL’ with the mask layer ML2; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML2 is etched/removed, thereby forming an intermediate dielectric layer IDL”.
Referring to FIG. 2F, a mask layer ML3 having an opening OG3 is provided on the intermediate dielectric layer IDL’, and a portion of the intermediate dielectric layer IDL” is exposed by the opening OG3, in which the opening OG3 has a greater width than the opening OG2.
Referring to FIG. 2G, an etching process is performed on the intermediate dielectric layer IDL”’ with the mask layer ML3; and thus, the exposed portion of the intermediate dielectric layer IDL by the mask layer ML3 is etched/removed. After that, the aforesaid manufacturing processes are carried out one or more times to obtain a lower portion LP of the dielectric layer 40 as shown in the FIG. 1. The lower portion LP of the dielectric layer 40 is formed to have portions with different widths and heights, respectively.
Referring to FIG. 2H, a blanket conductive layer BCL is formed to cover the lower portion LP of the dielectric layer 40, such that the blanket conductive layer BCL is conformally disposed on the lower portion LP of the dielectric layer 40. Then, a portion of the blanket conductive layer BCL is removed, such that a field plate 50A in the FIG. 1 is formed. The field plate 50A is formed to cover portions of the lower portion LP of the dielectric layer 40, such that the field plate 50A has a plurality of horizontal portions HP1~HP4 on top surfaces of the portions of the dielectric layer respectively and a plurality of connecting portions CP1~CP3 on side surfaces of the portions of the lower portion LP of the dielectric layer 40. After that, an upper portion of the dielectric layer 40 is formed to cover the resulted structure, such that the field plate 50A is embedded in the dielectric layer 40. Thus, the semiconductor device 1A as shown in FIG. 1 can be obtained.
FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50B has horizontal portions HP1~HP4, and thicknesses of the horizontal portions HP1~HP4 are variable. For example, thicknesses of the horizontal portions HP1~HP4 increase in sequence (i.e., increasing along a direction from the gate electrode 32 toward the electrode 22) . To be more specific, the bottom-most horizontal portion HP1 has the smallest thickness. The horizontal portion HP2 has a thickness greater than that of the horizontal portion HP1. The horizontal portion HP3 has a thickness greater than that of the horizontal portion HP2. The horizontal portion HP4 has a thickness greater than that of the horizontal portion HP3. By such a configuration, the electric field in the device 1B can be well modulated and the negative impacts of the parasitic capacitance between the horizontal portion and the 2DEG region in the nitride-based semiconductor layer 12 can be reduced as much as possible.
FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that side surfaces of the dielectric sub-layers SL2~SL4 of the dielectric layer 40C can be curved surfaces. The field plate 50C formed on the dielectric layer 40C can have connecting portions CP1~CP3 conformal with curved side surfaces of the dielectric sub-layers SL2~SL4 of the dielectric layer 40C, respectively. That is to say, the connecting portions CP1~CP3 of the field plate 50C are curved connecting portions. The curved connecting portions CP1~CP3 can evenly distribute the stress from an upper portion of the dielectric layer 40C. The curved profile can make the electric field distribution free from sharp changing, so as to avoid potential peaks in the distribution.
FIG. 5 is a vertical cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50D has a plurality of round corner structures RS. An end portion of the connecting portion is connected to an end portion of the horizontal portion, such that a round corner structure RS is formed therebetween. Such a configuration can help the electric field near the round corner structure RS to be more evenly distributed.
FIG. 6 is a vertical cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the semiconductor device 1E can have electrode structures 20E, 22E. The electrode structure 20E has an electrode 202 and an electrode pad 204. The electrode 202 is disposed on/over/above the nitride-based semiconductor layer 14. The electrode 202 makes contact with the nitride-based semiconductor layer 14. The electrode pad 204 is disposed on/over/above the electrode 202. The electrode contact/pad 204 makes contact with the electrode 202. The electrode contact/pad 204 has a width greater than that of the electrode 202. Similarly, the electrode structure 22E can have the similar configuration with the electrode structure 20E.
To be more specific, a bottom surface BS of the electrode contact/pad 204 is substantially coplanar with a bottom surface of one of the horizontal portions, for example, horizontal portion HP2 of the field plate 50. Heights of the electrode contact/pad 204 and the electrode contact/pad 224 are substantially the same. By such a configuration, the horizontal portion HP2 of the field plate 50, the electrode contact/pad 204 and the electrode contact/pad 224 can be manufactured in the same manufacturing process, which is advantageous to further reduce the manufacturing cost.
The material of the electrode contacts/pads 204/224 can be similar or identical with the material of the electrodes 20 and 22.
FIG. 7 is a vertical cross-sectional view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the field plate 50F has a plurality of horizontal portions HP1~HP3 and a plurality of connecting portions CP1~CP2. Each of the connecting portions CP1, CP2 extends inclinedly to connect corresponding two of adjacent the horizontal portions. For example, the connecting portions CP1 extends inclinedly to connect two of adjacent the horizontal portions HP1, HP2, and the connecting portions CP2 extends inclinedly to connect two of adjacent the horizontal portions HP2, HP3. Such a configuration can alleviate the stress from an upper portion of the dielectric layer 40F.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.
Claims (25)
- A semiconductor device comprising:a first nitride-based semiconductor layer;a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;a dielectric layer covering the second nitride-based semiconductor layer; anda field plate conformally disposed on the dielectric layer and comprising a plurality of horizontal portions at different heights and a plurality of connecting portions, wherein any two of the adjacent horizontal portions are connected by the corresponding connecting portion, such that an entirety of the field plate is continuous in a vertical cross-sectional view of the semiconductor device.
- The semiconductor device of any one of the proceeding claims, wherein the horizontal portions and the connecting portions are alternatively arranged.
- The semiconductor device of any one of the proceeding claims, wherein thicknesses of the horizontal portions are gradually increased along a first direction.
- The semiconductor device of any one of the proceeding claims, wherein heights of the horizontal portions are increased along a horizontal direction.
- The semiconductor device of any one of the proceeding claims, wherein each of the connecting portions extends vertically to connect corresponding two of adjacent the horizontal portions.
- The semiconductor device of any one of the proceeding claims, wherein each of the connecting portions extends inclinedly to connect corresponding two of adjacent the horizontal portions.
- The semiconductor device of any one of the proceeding claims, wherein an end portion of the connecting portion is connected to an end portion of the horizontal portion, such that a round corner structure is formed therebetween.
- The semiconductor device of any one of the proceeding claims, further comprising a gate electrode disposed on the second nitride-based semiconductor layer,wherein in the horizontal portions, the bottom-most horizontal portion is separated from the gate electrode.
- The semiconductor device of any one of the proceeding claims, wherein the dielectric layer comprises a plurality of stacked dielectric sub-layers, whereinthe horizontal portions of the field plate cover on top surfaces of the dielectric sub-layers, respectively; andthe connecting portions of the field plate cover on side surfaces of the dielectric sub-layers, respectively.
- The semiconductor device of any one of the proceeding claims, wherein the dielectric sub-layers have different widths.
- The semiconductor device of any one of the proceeding claims, wherein widths of the dielectric sub-layers decrease along a vertical direction.
- The semiconductor device of any one of the proceeding claims, wherein in the dielectric sub-layers, the bottom-most dielectric sub-layer is the widest dielectric sub-layer and makes contact with the second nitride-based semiconductor layer.
- The semiconductor device of any one of the proceeding claims, further comprising an electrode structure disposed on the second nitride-based semiconductor layer.
- The semiconductor device of any one of the proceeding claims, wherein the electrode structure comprises an electrode making contact with the second nitride-based semiconductor layer and an electrode contact disposed on the electrode,wherein a bottom surface of the electrode contact is substantially coplanar with a bottom surface of one of the horizontal portions of the field plate.
- The semiconductor device of any one of the proceeding claims, wherein the field plate is a stepped field plate.
- A method for manufacturing a semiconductor device, comprising:forming a first nitride-based semiconductor layer over a substrate;forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;forming a dielectric layer to cover the second nitride-based semiconductor layer, wherein the dielectric layer is formed to have portions with different widths and heights, respectively; andforming a field plate to cover the portions of the dielectric layer, such that the field plate has a plurality of first portions on top surfaces of the portions of the dielectric layer respectively and a plurality of second portions on side surfaces of the portions of the dielectric layer, wherein any two of the adjacent first portions are connected by the corresponding second portion, such that an entirety of the formed field plate is continuous in a vertical cross-sectional view of the semiconductor device.
- The method of any one of the proceeding claims, wherein the side surfaces of the blanket dielectric sub-layers are inclined surfaces, curved surfaces, plane surfaces or a combination thereof.
- The method of any one of the proceeding claims, wherein the second portions of the field plate are conformally disposed with the side surfaces of the blanket dielectric sub-layers.
- The method of any one of the proceeding claims, wherein thicknesses of the first portions are gradually increased along a first direction.
- The method of any one of the proceeding claims, wherein the formed field plate is a stepped field plate.
- A semiconductor device comprising:a first nitride-based semiconductor layer;a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;a source and a drain electrodes disposed over the second nitride-based semiconductor layer;a gate electrode disposed over the second nitride-based semiconductor layer and located between the source and the drain electrodes;a dielectric layer disposed over the second nitride-based semiconductor layer and having portions with different heights; anda field plate extending continuously along a profile of the portions of the dielectric layer along a direction from the gate electrode toward the drain electrode.
- The semiconductor device of any one of the proceeding claims, wherein heights of the portions of the dielectric layer are increased along the direction from the gate electrode toward the drain electrode.
- The semiconductor device of any one of the proceeding claims, wherein the field plate has a plurality of first portions extending over the portions of the dielectric layer, respectively.
- The semiconductor device of any one of the proceeding claims, wherein thicknesses of the first portions of the field plate increase along the direction from the gate electrode toward the drain electrode.
- The semiconductor device of any one of the proceeding claims, wherein the field plate has a plurality of second portions, wherein each of the second portions extends between and connects two adjacent first portions.
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Citations (5)
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CN1639875A (en) * | 2003-01-29 | 2005-07-13 | 株式会社东芝 | Power semiconductor device |
CN101976686A (en) * | 2005-06-10 | 2011-02-16 | 日本电气株式会社 | Field effect transistor |
JP2014222724A (en) * | 2013-05-14 | 2014-11-27 | 三菱電機株式会社 | Transistor using nitride semiconductor and manufacturing method of the same |
CN113519064A (en) * | 2021-06-02 | 2021-10-19 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
CN114144891A (en) * | 2021-07-16 | 2022-03-04 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
-
2022
- 2022-11-04 WO PCT/CN2022/129876 patent/WO2024092720A1/en unknown
- 2022-11-04 CN CN202280080639.8A patent/CN118369769A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1639875A (en) * | 2003-01-29 | 2005-07-13 | 株式会社东芝 | Power semiconductor device |
CN101976686A (en) * | 2005-06-10 | 2011-02-16 | 日本电气株式会社 | Field effect transistor |
JP2014222724A (en) * | 2013-05-14 | 2014-11-27 | 三菱電機株式会社 | Transistor using nitride semiconductor and manufacturing method of the same |
CN113519064A (en) * | 2021-06-02 | 2021-10-19 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
CN114144891A (en) * | 2021-07-16 | 2022-03-04 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
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