WO2024108490A1

WO2024108490A1 - Nitride-based semiconductor device and method for manufacturing thereof

Info

Publication number: WO2024108490A1
Application number: PCT/CN2022/134083
Authority: WO
Inventors: Ronghui Hao
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2024-05-30

Abstract

The semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, and a gate electrode. The first barrier layer is disposed over the channel layer. The second barrier layer with separated portions covers the first barrier layer, such that a discontinuous channel is formed in the channel layer and directly under the separated portions. The gate electrode extends into a region between the separated portions of the second barrier layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventor: Ronghui HAO

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to an enhancement mode nitride-based semiconductor device having a two-step formed barrier layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The second nitride-based semiconductor layer includes a first nitride-based semiconductor sub-layer making contact with the first nitride-based semiconductor layer and a second nitride-based semiconductor sub-layer disposed over the first nitride-based semiconductor sub-layer to form an interface therebetween. The dielectric layer covers the second nitride-based semiconductor layer and has at least a portion, wherein the portion penetrates the second nitride-based semiconductor sub-layer to make contact with the first nitride-based semiconductor sub-layer. The gate electrode is disposed over the portion of the dielectric layer. The first nitride-based semiconductor sub-layer is thin enough, such that electron density of a zone of the 2DEG region directly under the gate electrode is insufficient, thereby forbidding electrons to freely move parallel in the 2DEG region.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A first nitride-based semiconductor sub-layer of a second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer, in which the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, and a thickness of the first nitride-based semiconductor sub-layer is insufficient to induce a 2DEG region. A mask layer is disposed on the first nitride-based semiconductor sub-layer. A second nitride-based semiconductor sub-layer of the second nitride-based semiconductor layer is formed over the first nitride-based semiconductor sub-layer, such that the mask layer and the second nitride-based semiconductor sub-layer collectively cover the first nitride-based semiconductor sub-layer, wherein thicknesses of the first and second nitride-based semiconductor sub-layers are sufficient to induce a 2DEG region thereunder. The mask layer is removed to expose the first nitride-based semiconductor sub-layer. A dielectric layer is formed to cover the second nitride-based semiconductor layer, such that at least a portion of the dielectric layer makes contact with the first nitride-based semiconductor sub-layer. A gate electrode is formed on the portion of the dielectric layer.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, and a gate electrode. The first barrier layer is disposed over the channel layer. The second barrier layer with separated portions covers the first barrier layer, such that a discontinuous channel is formed in the channel layer and directly under the separated portions. The gate electrode extends into a region between the separated portions of the second barrier layer.

By the above configuration, in the present disclosure, the barrier layer is two-step formed. Firstly, a bottom barrier sub-layer of the barrier layer is formed to cover the channel layer. The bottom barrier sub-layer is formed to be thin enough, such that no 2DEG region is formed in this manufacturing stage due to weak polarization effect therein. Then, a top barrier sub-layer of the barrier layer is regrown on the bottom barrier sub-layer, in which the top barrier sub-layer includes separated portions. Such a manufacturing method can regionally thicken thickness of the barrier layer to enhance the extent of polarization effect directly under the separated portions; and therefore, a discontinuous channel can be induced in the channel layer. Hence, an enhancement mode semiconductor device can be realized. The manufacturing process of the semiconductor device is simple and avoids using additional etching step to etch the nitride-based semiconductor layer. Thus, the semiconductor device of the present disclosure can have a good reliability, good electrical properties, and a good yield rate.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 4D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.

Referring to FIG. 1, the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16,

electrodes

20, 22, a dielectric layer 30, a gate electrode 40, and a passivation layer 50.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer 12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer 12. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

One way to achieve a normally-off n-channel semiconductor device is to form a recess structure into the AlGaN barrier layer and fill the gate electrode therein, thereby extinguishing a zone of the 2DEG region directly under the gate electrode. Accordingly, there is a need to perform a destructive step, such as an etching step, to the AlGaN layer. However, the etching step may cause unexpected sidewall/surface damages, and the recessed/corrugated surface of the AlGaN layer may result in carrier scattering, thereby reducing the carrier mobility and enhancing the on-resistance of the semiconductor device. Furthermore, the etching step is need to be precisely controlled, and thus the yield rate is hard to be promoted.

In order to overcome the aforesaid issue, the present disclosure provides a novel structure.

The nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12. After that, a thin nitride-based semiconductor layer 162 is formed to cover an entirety of the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 162 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x– _y)N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layer 14 and the nitride-based semiconductor layer 162 are selected such that the nitride-based semiconductor layer 162 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.

For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 162 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layer 14 and the nitride-based semiconductor layer 162 can serve as a channel layer and a barrier layer, respectively.

A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well. It should be noted that the formation of the 2DEG region is positively related to the extent of the polarization effect between the channel and barrier layers, which is determined by the thickness ratio of the channel and barrier layers. In the present disclosure, the thickness of the nitride-based semiconductor layer 162 is intentionally controlled to be thin enough, such that the 2DEG region is hard to be inherently induced/generated in the nitride-based semiconductor layer 14. That is to say, at this manufacturing stage, there are no sufficient electrons to form 2DEG region.

In order to externally induce/generate at least one 2DEG region, there is a need to enhance the polarization effect of the nitride-based semiconductor layers 14 and 162. Thereafter, a nitride-based semiconductor layer 164 is formed (or regrown) on/over/above the nitride-based semiconductor layer 162, and thus an interface IF is formed therebetween, in which the interface IF is a horizontal interface. In some embodiments, the nitride-based semiconductor layer 162 and the nitride-based semiconductor layer 164 are merged so no visible interface present between the nitride-based semiconductor layer 162 and the nitride-based semiconductor layer 164.

The nitride-based semiconductor layer 164 is thicker than that of the nitride-based semiconductor layer 162. In some embodiments, the thickness of the nitride-based semiconductor layer 162 is in a range from about 3 nm to about 5 nm. In some embodiments, the thickness of the nitride-based semiconductor layer 164 is in a range from about 5 nm to about 40 nm.

The nitride-based semiconductor layer 164 has portions P1, P2 separated from each other. A recess R is naturally formed between separated portions P1, P2, in which the recess R is defined by two inner side walls IS1, IS2 of the nitride-based semiconductor layer 164 and a top surface of the nitride-based semiconductor layer 162. The inner side walls IS1, IS2 of the nitride-based semiconductor layer 164 are vertical with a top surface of the nitride-based semiconductor layer 162. The exemplary material of the nitride-based semiconductor layer 164 is selected, such that the nitride-based semiconductor layer 164 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14. By such a material selection, the nitride-based semiconductor layer 164 can also serve as a barrier layer. Thus, the two nitride-based semiconductor layers 162, 164 can collectively serve as a thicker barrier layer (or a thicker nitride-based semiconductor layer 16) , and each of the nitride-based semiconductor layers 162, 164 can serve as a nitride-based semiconductor sub-layer of the nitride-based semiconductor layer 16. In summary, the nitride-based semiconductor layer 16 of the present disclosure is two-step formed.

As such, in the present disclosure, by forming separated portions P1, P2 of the nitride-based semiconductor layer 164 on/over/above the thin nitride-based semiconductor layer 162 to regionally thicken a thickness of the barrier layer, so that zones Z1, Z2 of the 2DEG region directly under the separated portions P1, P2 are induced, in which the zones Z1, Z2 of the 2DEG region are separated from each other. That is to say, the nitride-based semiconductor layer 162 and the nitride-based semiconductor layer 164 are thick enough, such that electrons in zones Z1, Z2 of 2DEG region thereunder form a channel. A portion P of the nitride-based semiconductor layer 162 is free from coverage of the portions P1, P2 of the nitride-based semiconductor layer 164, and thus a zone ZG between the zones Z1, Z2 and directly under the portion P is insufficient to form a channel due to the thin nitride-based semiconductor layer 162, thereby forbidding electrons to freely move parallel in the 2DEG region. The zones Z1, Z2 of the 2DEG region are naturally interrupted due to the absence of 2DEG region therebetween. The zones Z1, Z2 of the 2DEG region can be viewed as a discontinuous 2DEG region (i.e., a discontinuous channel in the nitride-based semiconductor layer 14) . Hence, the n-channel enhancement mode semiconductor device 1A can be realized without performing a destructive way on the electrical property layers such as nitride-based semiconductor layers 14, 16.

In some embodiments, the exemplary material of the nitride-based semiconductor layer 164 can be AlN, AlGaN, AlInN, AlInGaN or combinations thereof. In some embodiments, the exemplary material of the nitride-based semiconductor layer 164 can be the same as that of the nitride-based semiconductor layer 162. In some embodiments, the exemplary material of the nitride-based semiconductor layer 164 can be different from that of the nitride-based semiconductor layer 162. For example, the nitride-based semiconductor layer 162 can include AlGaN, and the nitride-based semiconductor layer 164 can include AlInGaN.

In some embodiments, the nitride-based semiconductor layer 162 and the nitride-based semiconductor layer 164 have the same III-V compound but different compositions. For example, the nitride-based semiconductor layer 162 include Al _aGa _(1–a) N where a ≤ 1, and the nitride-based semiconductor layer 164 include Al _bGa _(1–b) N where b ≤ 1 and a<b. The reason is to let the thicker barrier layer tend to induce a 2DEG region much more. The thickness in combination of the composition can enhance the concentration difference between only the nitride-based semiconductor layer 162 and the thicker barrier layer (i.e., the combination of the nitride-based semiconductor layer 162 and the nitride-based semiconductor layer 164) . In some embodiments, the nitride-based semiconductor layer 162 include Al _aGa _(1–a) N where 0.02 ≤ a ≤ 0.1, and the nitride-based semiconductor layer 164 include Al _bGa _(1–b) N where 0.12 ≤ b ≤ 0.3. In some embodiment, the nitride-based semiconductor layer 164 is formed by regrowth from the nitride-based semiconductor layer 162. The advantageous of the regrowth is to make the nitride-based semiconductor layer 164 have at least one character different than that of the nitride-based semiconductor layer 162.

In some embodiments, the nitride-based semiconductor layer 162 include Al _aGa _(1–a) N where a ≤ 1, and the nitride-based semiconductor layer 164 includes AlN, AlInN, AlGaN, or combinations thereof. In some embodiments, the nitride-based semiconductor layer 162 include u-doped AlGaN, and the nitride-based semiconductor layer 164 includes n-doped AlGaN. The regrowth can make such the difference achievable. The

electrodes

20, 22 are disposed on/over/above the portions P1, P2 of the nitride-based semiconductor layer 164, respectively. The

electrodes

20, 22 make contact with the portions P1, P2 of the nitride-based semiconductor layer 164, respectively. In some embodiments, the electrode 20 can serve as a source electrode. In some embodiments, the electrode 20 can serve as a drain electrode. In some embodiments, the electrode 22 can serve as a source electrode. In some embodiments, the electrode 22 can serve as a drain electrode. The role of the

electrodes

20 and 22 depends on the device design.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. The

electrodes

20 and 22 form ohmic contacts with the nitride-based semiconductor layer 16A. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

The dielectric layer 30 is disposed on/over/above the nitride-based semiconductor layer 16. The dielectric layer 30 makes contact with a top surface of the nitride-based semiconductor layer 16. The dielectric layer 30 has a portion 30P to penetrate the nitride-based semiconductor layer 164 to make contact with the nitride-based semiconductor sub-layer 162. The portion 30P extends along the two inner side walls IS1, IS2 to make contact with the nitride-based semiconductor sub-layer 162. The portion 30P is conformal with the recess R, and thus another recess R’ defined by the portion 30P of the dielectric layer 30 is naturally formed in the recess R (or on the portion P of the nitride-based semiconductor layer 162.

The material of the dielectric layer 30 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 30 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 30 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The gate electrode 40 is disposed on/over/above the portion 30P of the dielectric layer 30. The gate electrode 40 is separated from the nitride-based semiconductor layer 162 by the portion 30P of the dielectric layer 30. The gate electrode 40 is received by the recess R’ defined by the dielectric layer 30. The gate electrode 40 extends into a region between the portions P1, P2 of the nitride-based semiconductor layer 164. The gate electrode 40 has a bottom portion wrapped by the dielectric layer 30. A bottom surface BS of the gate electrode 40 is within a thickness range of the nitride-based semiconductor layer 164. The gate electrode 40 is located between the

electrodes

20, 22. The gate electrode 40 is, for example, a T-shaped gate electrode.

The exemplary materials of the gate electrode 40 may include metals or metal compounds. The gate electrode 40 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The passivation layer 50 covers the

electrode

20, 22, and the dielectric layer 30. The gate electrode 40 penetrate the passivation layer 50 and the dielectric layer 30. The exemplary material of the passivation layer 50 can be identical with or similar with that of the dielectric layer 40. Moreover, the passivation layer 50 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer 50 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 50 to remove the excess portions, thereby forming a level top surface.

Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10 by using deposition techniques. A nitride-based semiconductor layer 14 is formed on/over/above the buffer layer 12. A nitride-based semiconductor layer 162 is formed on/over/above the nitride-based semiconductor layer 14, in which the nitride-based semiconductor layer 162 has a bandgap greater than that of the nitride-based semiconductor layer 14. A thickness of the formed nitride-based semiconductor layer 162 is well controlled, such that the thickness thereof is insufficient to induce a 2DEG region. Thus, no 2DEG region is formed in this manufacturing stage.

Referring to FIG. 2B, a mask layer ML is disposed on/over/above the nitride-based semiconductor sub-layer 162. In the embodiment, the mask layer ML can have a rectangular profile. The material of the mask layer ML can be, for example, silicon oxide, silicon nitride, or combinations thereof.

Referring to FIG. 2C, a nitride-based semiconductor layer 164 is formed on/over/above the nitride-based semiconductor layer 162, such that the mask layer ML and the nitride-based semiconductor layer 164 collectively cover the nitride-based semiconductor layer 162. The thicknesses of the nitride-based semiconductor layers 162, 164 are sufficient to induce a 2DEG region thereunder. Thus, the nitride-based semiconductor layer 16 including the nitride-based semiconductor layers 162, 164 is formed.

Referring to FIG. 2D, the mask layer ML is removed to expose the nitride-based semiconductor layer 162, and the inner side walls IS1, IS2 of the nitride-based semiconductor layer 164. Shape of each of the inner side walls IS1, IS2 is determined by the mask layer ML.

Referring to FIG. 2E, a dielectric layer 30 is formed to cover the nitride-based semiconductor layer 164, such that at least a portion 30P of the dielectric layer 30 makes contact with the nitride-based semiconductor layer 162. The dielectric layer 30 is formed to conformally cover the nitride-based semiconductor layer 16, such that the dielectric layer 30 is formed to have a recess R’ directly over the portion 30P thereof making contact with the nitride-based semiconductor layer 162.

Referring to FIG. 2F, portions of the dielectric layer 30 are removed to expose a top surface of the nitride-based semiconductor layer 164.

Electrodes

20, 22 are formed on/over/above the top surface of the nitride-based semiconductor layer 164. A passivation layer 50 is formed to cover the

electrodes

20, 22, and the dielectric layer 30. Then, a gate electrode 40 is formed on the portion 30P of the dielectric layer 30. Thus, the nitride-based semiconductor device 1A in the FIG. 1 can be obtained.

FIG. 3 is a vertical view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the inner side walls IS1, IS2 of the nitride-based semiconductor layer 164B are inclined with respect to a top surface of the nitride-based semiconductor layer 162. A bottom portion of the gate electrode 40B makes contact with the inner side walls IS1, IS2, such that the bottom portion thereof has a gradually changed width.

By such a configuration, since the nitride-based semiconductor layer 164B has a portion with inclined inner side wall IS1 or IS2, a zone of the 2DEG region thereunder can have a variable electron density, so as to avoid excessive electric field variation (e.g., peak in electric field distribution) . In some embodiments, the variable electron density can serve as buffer in the difference between the high density and the low density. Furthermore, the configuration of inclined inner side wall of the nitride-based semiconductor layer 164B can assist the gate electrode to fill in the recess, which is advantageous to improve reliability.

Different stages of a method for manufacturing the nitride-based semiconductor device 1B are shown in FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, and FIG. 4F as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 4A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10 by using deposition techniques. A nitride-based semiconductor layer 14 is formed on/over/above the buffer layer 12. A nitride-based semiconductor layer 162 is formed on/over/above the nitride-based semiconductor layer 14, in which the nitride-based semiconductor layer 162 has a bandgap greater than that of the nitride-based semiconductor layer 14. A thickness of the formed nitride-based semiconductor layer 162 is well controlled, such that the thickness thereof is insufficient to induce a 2DEG region. Thus, no 2DEG region is formed in this manufacturing stage.

Referring to FIG. 4B, a mask layer ML is disposed on/over/above the nitride-based semiconductor sub-layer 162. In the embodiment, the mask layer ML can have an inverse trapezoid profile.

Referring to FIG. 4C, a nitride-based semiconductor layer 164B is formed on/over/above the nitride-based semiconductor layer 162, such that the mask layer ML and the nitride-based semiconductor layer 164B collectively cover the nitride-based semiconductor layer 162. Thus, the formed nitride-based semiconductor layer 164B can have two inclined inner side walls IS1, IS2.

Referring to FIG. 4D, the mask layer ML is removed to expose the nitride-based semiconductor layer 162, and the inner side walls IS1, IS2 of the nitride-based semiconductor layer 164. Thereafter, a dielectric layer 30,

electrodes

20, 22, a gate electrode 40B, and a passivation layer 50 are formed in sequence, obtaining the nitride-based semiconductor device 1B in the FIG. 3.

FIG. 5 is a vertical view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the portion P1 under the electrode 20 has a thickness different from that of the portion P2 under the electrode 22. In detail, the portion P1 has a thickness greater than that of the portion P2, such that the zone Z1 directly under the portion P1 has an electron density greater than that of the zone Z2 directly under the portion P2. Such a configuration can meet a specific device requirement.

FIG. 6 is a top view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the portion 30P of the dielectric layer 30 fills up the recess R defined by the nitride-based semiconductor layer 16, such that a top surface of the portion 30P is higher than that of the portion P1 (or the portion P2) . Thus, a bottom surface BS of the gate electrode 40D, which makes contact with the top surface of the portion 30P, is located beyond a thickness range of the nitride-based semiconductor layer 16. Such a configuration can meet a specific device requirement.

Based on above, in the present disclosure, a thin barrier layer is formed on the channel layer firstly. Then, a thicker barrier layer having separated portions is regrown on the thin barrier layer, and thus an interface can be formed therebetween, thereby inducing a discontinuous channel in the channel layer. That is to say, in the present disclosure, the discontinuous channel in the channel layer is induced in a constructive way. The semiconductor device manufactured by such method can prevent unwanted damages caused by a destructive step (e.g., etching step) , and thus the semiconductor device of the present disclosure can have a good reliability.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction, wherein the second nitride-based semiconductor layer comprises a first nitride-based semiconductor sub-layer making contact with the first nitride-based semiconductor layer and a second nitride-based semiconductor sub-layer disposed over the first nitride-based semiconductor sub-layer to form an interface therebetween;

a dielectric layer covering the second nitride-based semiconductor layer and having at least a portion, wherein the portion penetrates the second nitride-based semiconductor sub-layer to make contact with the first nitride-based semiconductor sub-layer; and

a gate electrode disposed over the portion of the dielectric layer,

wherein the first nitride-based semiconductor sub-layer is thin enough, such that electron density of a zone of the 2DEG region directly under the gate electrode is insufficient, thereby forbidding electrons to freely move parallel in the 2DEG region.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the second nitride-based semiconductor sub-layer is thicker than that of the first nitride-based semiconductor sub-layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the second nitride-based semiconductor sub-layer has two inner side walls, wherein the portion of the dielectric layer extends along the inner side walls to make contact with the first nitride-based semiconductor sub-layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the inner side walls of the second nitride-based semiconductor sub-layer are vertical with respect to a top surface of the first nitride-based semiconductor sub-layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the inner side walls of the second nitride-based semiconductor sub-layer are inclined with respect to a top surface of the first nitride-based semiconductor sub-layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein a bottom surface of the gate electrode is within a thickness range of the second nitride-based semiconductor sub-layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the gate electrode is separated from the first nitride-based semiconductor sub-layer by the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the gate electrode has a bottom portion wrapped by the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the gate electrode is a T-shaped gate electrode.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the dielectric layer has a recess to receive the gate electrode.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the first nitride-based semiconductor layer and the second nitride-based semiconductor sub-layer are thick enough, such that electrons in a zone of 2DEG region thereunder form a channel.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the 2DEG region is a discontinuous 2DEG region.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the interface is a horizontal interface.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising a passivation layer covering the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising:

a pair of electrodes disposed over the second nitride-based semiconductor sub-layer, wherein the gate electrode is located therebetween.
A manufacturing method of a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a first nitride-based semiconductor sub-layer of a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, and a thickness of the first nitride-based semiconductor sub-layer is insufficient to induce a two-dimensional electron gas (2DEG) region;

disposing a mask layer on the first nitride-based semiconductor sub-layer;

forming a second nitride-based semiconductor sub-layer of the second nitride-based semiconductor layer over the first nitride-based semiconductor sub-layer, such that the mask layer and the second nitride-based semiconductor sub-layer collectively cover the first nitride-based semiconductor sub-layer, wherein thicknesses of the first and second nitride-based semiconductor sub-layers are sufficient to induce 2DEG region thereunder;

removing the mask layer to expose the first nitride-based semiconductor sub-layer;

forming a dielectric layer to cover the second nitride-based semiconductor layer, such that at least a portion of the dielectric layer makes contact with the first nitride-based semiconductor sub-layer; and

forming a gate electrode on the portion of the dielectric layer.
The manufacturing method of any one of the proceeding claims, wherein the dielectric layer is formed to conformally cover the second nitride-based semiconductor layer, such that the dielectric layer is formed to have a recess directly over the portion thereof making contact with the first nitride-based semiconductor sub-layer.
The manufacturing method of any one of the proceeding claims, wherein the gate electrode is formed in the recess.
The manufacturing method of any one of the proceeding claims, wherein the mask layer has a rectangular profile or an inverse trapezoid profile.
The manufacturing method of any one of the proceeding claims, wherein the mask layer comprises silicon oxide, silicon nitride, or combinations thereof.
A semiconductor device, comprising:

a channel layer;

a first barrier layer disposed over the channel layer;

a second barrier layer having separated portions to cover the first barrier layer, such that a discontinuous channel is formed in the channel layer and directly under the separated portions; and

a gate electrode extending into a region between the separated portions of the second barrier layer.
The semiconductor device of any one of the proceeding claims, wherein material of the first barrier layer is different from that of the second barrier layer.
The semiconductor device of any one of the proceeding claims, further comprising a source and a drain electrodes disposed over the separated portions of the second barrier layer, respectively.
The semiconductor device of any one of the proceeding claims, wherein the separated portion of the second barrier layer under the source electrode has a thickness different from that of the separated portion of the second barrier layer under the drain electrode.
The semiconductor device of any one of the proceeding claims, wherein the second barrier layer comprises AlN, AlGaN, AlInN, AlInGaN, or combinations thereof.