WO2024092419A1

WO2024092419A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024092419A1
Application number: PCT/CN2022/128677
Authority: WO
Inventors: Ronghui Hao
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2024-05-10

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a source field plate, a drain field plate, and a reduced surface field (RESURF) structure. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The source field plate extends over and electrically coupled to the source electrode. The drain field plate extends over and electrically coupled to the drain electrode. The RESURF structure is disposed over the second nitride-based semiconductor layer and located between the source and drain field plates, in which the RESURF structure further includes a first doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a first conductive layer disposed on the first doped nitride-based semiconductor layer and electrically coupled to the source field plate.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventor: Hao Ronghui

Field of the Disclosure:

The present invention generally relates to a nitride-based semiconductor device. More specifically, the present invention relates to a III-nitride-based semiconductor device having a p-type doped nitride-based semiconductor layer to constitute a reduced surface field (RESURF) structure.

Background:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a source field plate, a drain field plate, and a reduced surface field (RESURF) structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The source field plate extends over and electrically coupled to the source electrode. The drain field plate extends over and electrically coupled to the drain electrode. The RESURF structure is disposed over the second nitride-based semiconductor layer and located between the source and drain field plates, in which the RESURF structure further includes a first doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a first conductive layer disposed on the first doped nitride-based semiconductor layer and electrically coupled to the source field plate.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A blanket doped nitride-based semiconductor layer is formed over the second nitride-based semiconductor layer. The blanket doped nitride-based semiconductor layer is thinned, such that the blanket doped nitride-based semiconductor layer has a first portion and a second portion thinner than the first portion. A blanket conductive layer is formed on the thinned blanket doped nitride-based semiconductor layer. Portions of the blanket doped nitride-based semiconductor layer and the blanket conductive layer are removed, such that a gate structure and a reduced surface field (RESURF) structure are formed, wherein the gate structure has the first portion and the RESURF structure has the remaining portion of the second portion. A source and a drain electrodes are formed over the second nitride-based semiconductor layer, such that the gate structure and the RESURF structure located between the source and the drain electrodes. A source and a drain field plates are formed to be electrically coupled to the source and the drain electrodes, respectively, in which the RESURF structure is located between the source and the drain field plates.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a source field plate, a drain field plate, a reduced surface field (RESURF) structure, a gate structure, and at least a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The source field plate is electrically coupled to the source electrode. The drain field plate is electrically coupled to the drain electrode. The RESURF structure is disposed over the second nitride-based semiconductor layer, in which the RESURF structure extends horizontally, such that at least an end portion of the RESURF structure is located between the source and drain field plates. The gate structure is disposed over the second nitride-based semiconductor layer and located between the RESURF structure and the source electrode. The at least a field plate is located directly under the source field plate, in which an entirety of the field plate is located between the RESURF structure and the gate structure.

Based on the above description, in the present disclosure, at least one RESURF structure is formed in a region between the source and drain field plates, such that the electric field in the device can be more evenly distributed. Accordingly, withstand voltage of the device can be greatly improved.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is an enlarged vertical cross-sectional view of a region in FIG. 1A;

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 8 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "on, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a vertical cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14 and 16,

electrodes

20 and 22, a plurality of conductive/contact vias CV, a field plate 30, a field plate 32, a gate structure 40, a reduced surface field (RESURF) structure 50, field plates FP1, FP2, and a dielectric layer 60.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 can be disposed on/over/above the substrate 10. The buffer layer 12 can be disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer 12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 14 is disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 16 is disposed on/over/above the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, and the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

20 and 22 can be disposed on/over/above the nitride-based semiconductor layer 16. The

electrodes

20 and 22 can make contact with the nitride-based semiconductor layer 16. In some embodiments, the electrode 20 can serve as a source electrode. In some embodiments, the electrode 20 can serve as a drain electrode. In some embodiments, the electrode 22 can serve as a source electrode. In some embodiments, the electrode 22 can serve as a drain electrode. The role of the

electrodes

20 and 22 depends on the device design.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20 and 22 form ohmic contacts with the nitride-based semiconductor layer 16. The ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22. In some embodiments, each of the

electrodes

20 and 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

At least a portion of contact vias CV are disposed on/over/above the

electrodes

20, 22, respectively. The contact vias CV makes contact with the corresponding

electrodes

20, 22, respectively. The exemplary materials of the contact vias CV can include, for example but are not limited to, conductive materials, such as metals or alloys.

The field plate 30 is disposed on/over/above the electrode 20. The field plate 30 extends over the electrode 20. The field plate 30 is electrically coupled/connected to the electrode 20 through the contact via CV. In some embodiments, the electrode 20 can be a source electrode, and thus the field plate 30 electrically coupled to the electrode 20 can serve as a source field plate.

The field plate 32 is disposed on/over/above the electrode 22. The field plate 32 extends over the electrode 22. The field plate 32 is electrically coupled/connected to the electrode 22 through the contact via CV. In some embodiments, the electrode 22 can be a drain electrode, and thus the field plate 30 electrically coupled to the electrode 22 can serve as a drain field plate.

The exemplary materials of the

field plates

30, 32 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.

The gate structure 40 is disposed on/over/above the nitride-based semiconductor layer 16. The gate structure 40 is located/disposed between the

electrodes

20, 22. The gate structure 40 includes a doped nitride-based semiconductor layer 402 and a gate electrode 404. The doped nitride-based semiconductor layer 402 can be disposed on/over/above the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 402 can make contact with the nitride-based semiconductor layer 16. The gate electrode 404 is disposed on/over/above the doped nitride-based semiconductor layer 402.

Referring to FIG. 1A, the doped nitride-based semiconductor layer 402 has portions with different thicknesses. The doped nitride-based semiconductor layer 402 a main body portion and two side portions (e.g., extending portion/protruding portion) extending from the main body portion. The main body portion of the doped nitride-based semiconductor layer 402 is located between the two side portions thereof. The main body portion of the doped nitride-based semiconductor layer 402 has a thickness greater than that of the side portion. The two side portions of the doped nitride-based semiconductor layer 402 extend toward the

electrode

20, 22, respectively.

The exemplary materials of the doped nitride-based semiconductor layer 402 can be p-type doped. The doped nitride-based semiconductor layer 402 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 14 includes undoped GaN and the nitride-based semiconductor layer 16 includes AlGaN, and the doped nitride-based semiconductor layer 402 is p-type GaN layer which can bend the underlying band structure upwards and to deplete or partially deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.

FIG. 1B is an enlarged vertical cross-sectional view of a region in FIG. 1A. Referring to FIG. 1B, the main body portion of the doped nitride-based semiconductor layer 402 can fully deplete the corresponding zone Za of the 2DEG region thereunder. That is to say, the main body portion of the doped nitride-based semiconductor layer 402 of the gate structure 40 is thick enough to fully deplete a zone Za of the 2DEG region directly under the main body portion of the doped nitride-based semiconductor layer 402, which means that electron density is approaches to zero in the zone Za. On the other hand, each of the side portion of the doped nitride-based semiconductor layer 402 can partially deplete the corresponding zone Zb of the 2DEG region thereunder, and a part of 2DEG may remain in the zone Zb. That is to say, the side portions of the doped nitride-based semiconductor layer 402 of the gate structure 40 are thin enough, such that zones Zb of the 2DEG region directly under the doped nitride-based semiconductor layer 402 has a smaller or equal to electron density than that of the remaining zone of the 2DEG region. With respect to the doped nitride-based semiconductor layer 402, since the thickness thereof is correlated with the quantity of p-type impurities stored in the doped nitride-based semiconductor layer 402, portions of the p-type doped nitride-based semiconductor layer 30A with different thicknesses can achieve depletion in different degrees for the 2DEG region. Through the aforesaid thickness design, a zone Z’ of the 2DEG region including zones Za and Zb directly under the doped nitride-based semiconductor layer 402 is discontinuous.

In some embodiments, the gate electrode 404 may include metals or metal compounds. The gate electrode 404 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes 404 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

In the exemplary illustration of FIG. 1B, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 404 is at approximately zero bias. Specifically, the p-type doped nitride-based semiconductor layer 40 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete or partially deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the p-type doped nitride-based semiconductor layer 402 has different characteristics (e.g., different electron concentrations) than the remaining of the 2DEG region and thus is blocked.

In the nitride-based devices, how to reduce/alleviate the breakdown phenomenon induced by a strong peak electric field in the device has become an important issue. When the device is operated under a high voltage condition, the breakdown phenomenon easily occurs, thereby deteriorating the electrical properties and the reliability. The configuration of the field plates can alleviate the breakdown phenomenon. However, a proper clearance should be left between the field plates considering a factor of capacitance. Such a configuration may lead a zone of the 2DEG region directly under the clearance is free from coverage of the field plates; and therefore, a peak electric field may still occur the zone of the 2DEG region between the field plates. As a result, the quality of the nitride-based device cannot be further improved, which limits the application of the nitride-based devices.

At least to solve the aforesaid issue, the present disclosure provides a novel structure.

In the present disclosure, a RESURF structure 50 is disposed on/over/above the nitride-based semiconductor layer 16. The field plate 30 extends horizontally from a position over the electrode 20 to a position directly above the RESURF structure 50. The gate structure 40 is disposed between the RESURF structure 50 and the electrode 20. The RESURF structure 50 extends from a position directly under the field plate 30 to a position between the

field plates

30, 32. The RESURF structure 50 extends horizontally, such that at least an end portion of the RESURF structure 50 is located between the

field plates

30, 32. The RESURF structure 50 is formed/disposed/located in a region between the

field plates

30, 32.

Specifically, the RESURF structure 50 includes a doped nitride-based semiconductor layer 502 and a conductive layer 504. The doped nitride-based semiconductor layer 502 makes contact with the nitride-based semiconductor layer 16. The conductive layer 504 is disposed on/over/above the doped nitride-based semiconductor layer 502. The conductive layer 504 makes contact with the doped nitride-based semiconductor layer 502. A contact via CV extends vertically to make contact with the conductive layer 504 and the field plate 30, such that the conductive layer 504 and the field plate 30 have substantially the same voltage level. The field plate 30 can be electrically coupled to the conductive layer 504 through the contact via CV.

Referring to FIG. 1B again, in the embodiment, the doped nitride-based semiconductor layer 502 of the RESURF structure 50 is compositionally the same as the doped nitride-based semiconductor layer 402 of the gate structure 40; and therefore, the doped nitride-based semiconductor layer 502 can deplete at least a portion of the 2DEG region like the doped nitride-based semiconductor layer 402 of the gate structure 40.

In the embodiment, the thickness of the doped nitride-based semiconductor layer 502 is substantially the same as that of the side portion of doped nitride-based semiconductor layer 402 of the gate structure 40. The thickness of the doped nitride-based semiconductor layer 502 is less than that of the main body portion of doped nitride-based semiconductor layer 402 of the gate structure 40. An average thickness of the doped nitride-based semiconductor layer 402 of the gate structure 40 is greater than that of the doped nitride-based semiconductor layer 502 of the RESURF structure 50. That is to say, the doped nitride-based semiconductor layer 502 can partially deplete the corresponding zone Zc of the 2DEG region thereunder, and a part of 2DEG may remain in the zone Zc. Since the doped nitride-based semiconductor layer 502 has a constant thickness and a constant doping concentration, a constant 2DEG concentration drop/gap can occur under the doped nitride-based semiconductor layer 502.

With respect to the RESURF structure 50, the doped nitride-based semiconductor layer 502 of the RESURF structure 50 is thin enough, such that zone Zc of the 2DEG region directly under the doped nitride-based semiconductor layer 502 has a smaller or equal to electron density than that of the remaining zone of the 2DEG region. In other words, the configuration of the RESURF structure 50 can partially deplete electrons in the zone Zc thereunder, but still keep a zone Z of the 2DEG region from the gate structure 40 to the electrode 22 to be continuous.

In addition, since the doped nitride-based semiconductor layer 502 has a constant thickness and a constant doping concentration, a constant 2DEG concentration drop/gap can occur under the doped nitride-based semiconductor layer 502.

Based on the above, by the configuration of the RESURF structure 50 between the

field plates

30, 32, electron density of at least a zone Zc of the 2DEG region is reduced therebetween. Referring back to FIG. 1B again, the doped nitride-based semiconductor layer 504 and the 2DEG region collectively form a p-n diode PN. In some cases, the field plate 30 can serve as a source field plate. Since the field plate 30 is electrically coupled to the conductive layer 504 of the RESURF structure 50 through the contact via CV, the p-n diode PN is reverse biased as the nitride-based semiconductor device 1A is in an off-state. Thus, a peak electric field between the

field plates

30, 32 can be reduced by the RESURF structure 50, and withstand voltage of the semiconductor device 1A can be improved.

Furthermore, the configuration of the RESURF structure 50 can enhance depletion rate of the 2DEG region in the off-state, and thus output capacitance (C _oss) of the semiconductor device 1A can be reduced. The depletion in different degrees for the 2DEG region is advantageous to improvement of voltage withstanding during off state as well as modulation on-state-resistance (Rds-on) of the device.

In addition, in some embodiments, the doped nitride-based semiconductor layer 502 of the RESURF structure 50 is compositionally the same as the doped nitride-based semiconductor layer 402 of the gate structure 40, and the conductive layer 504 of the RESURF structure 50 is compositionally the same as the conductive layer 402 of the gate structure 40. By such a material selection, the RESURF structure 50 and the gate structure 40 can be manufactured in the same manufacturing stage.

The field plates FP1, FP2 are disposed/located between the gate structure 40 and the RESURF structure 50. An entirety of the field plate FP1/FP2 is located between the RESURF structure 50 and the gate structure 41. The field plates FP1, FP2 are located directly under the field plate 30. The field plates FP1, FP2 are located at different heights, respectively. The field plate FP1 is located between the gate structure 40 and the field plate FP2. The field plate FP2 is located between the field plate FP1 and the RESURF structure 50. The field plate FP1 is lower than the field plate FP2. At least a portion of contact vias CV are disposed on/over/above the field plates FP1, FP2, respectively. The contact via CV extends vertically between the field plate 30 and the field plate FP1, such that the field plate FP1 is electrically coupled to the field plate 30. The contact via CV extends between the field plate 30 and the field plate FP2, such that the field plate FP2 is electrically coupled to the field plate 30. By a configuration of the field plates FP1, FP2, an electric field distribution between the gate structure 40 and the RESURF structure 50 can be further modulated.

The exemplary materials of the field plates FP1, FP2 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.

The dielectric layer 60 is disposed on/over/above the nitride-based semiconductor layer 16. The dielectric layer 60 covers the

electrodes

20, 22, the gate structure 40, and the RESURF structure 50. The contact vias CV are disposed within the dielectric layer 60. The contact vias CV can penetrate the dielectric layer 60. The material of the dielectric layer 60 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 120 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 60 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

Furthermore, the dielectric layer 60 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the dielectric layer 60 can be formed as being thicker, and a planarization process, such as a chemical mechanical polish (CMP) process, is performed on the dielectric layer 60 to remove the excess portions, thereby forming a level top surface.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a buffer layer 12 can be formed on/over/above the substrate 10 by using the above-mentioned deposition techniques. A nitride-based semiconductor layer 14 can be formed on/over/above the buffer layer 12 by using the above-mentioned deposition techniques. A nitride-based semiconductor layer 16 can be formed on/over/above the nitride-based semiconductor layer 14 by using the above-mentioned deposition techniques. A blanket doped nitride-based semiconductor layer 70 can be formed on/over/above the nitride-based semiconductor layer 16.

Referring to FIG. 2B, a thinning process is performed on the blanket doped nitride-based semiconductor layer 70, such that an intermediate blanket doped nitride-based semiconductor layer 70’ (i.e., thinned blanket doped nitride-based semiconductor layer 70’) is formed, in which the intermediate blanket doped nitride-based semiconductor layer 70’ is formed to have portions P1, P2 with different thicknesses. The portion P1 has a thickness greater than that of the portion P2.

Referring to FIG. 2C, a blanket conductive layer 80 is formed on/over/above the intermediate blanket doped nitride-based semiconductor layer 70’.

Referring to FIG. 2D, an etching process is performed on the blanket conductive layer 80 and the intermediate blanket doped nitride-based semiconductor layer 70’, such that a gate structure 40 and a reduced surface field (RESURF) structure 50 are formed. The gate structure 40 has the portion P1 and the remaining portion RP1 (i.e., the conductive layer 404) of the blanket conductive layer 80. The RESURF structure 50 has the remaining portion of the portion P2 and the remaining portion RP2 (i.e., the conductive layer 504) of the blanket conductive layer 80.

Referring to FIG. 2E,

electrodes

20, 22 are formed on/over/above the nitride-based semiconductor layer 16, such that the gate structure 40 and the RESURF structure 50 are located between the

electrodes

20, 22. A plurality of field plates FP1, FP2 are formed between the gate structure 40 and the RESURF structure 50. A dielectric layer 60 is formed to cover the

electrodes

20, 22, the gate structure 40, the RESURF structure 50, and the field plates FP1, FP2, in which the dielectric layer 60 is formed to have a plurality through holes to expose the

electrodes

20, 22, the field plates FP1, FP2 and the RESURF structure 50.

Referring to FIG. 2F, a plurality of contact vias CV are formed to fill up the through holes of the dielectric layer 60.

Electrodes

electrodes

20, 22. A plurality of

field plates

30, 32 are formed to be coupled to the

electrodes

20, 22, respectively through the contact vias CV, in which the RESURF structure 50 is located between the

field plates

30, 32. The

field plates

30, 32 are formed on/over/above a top surface of the dielectric layer 60. Thus, the semiconductor device 1A in the FIG. 1A can be obtained.

FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the doped nitride-based semiconductor layer 502B has a width greater than that of the conductive layer 504B. Two end portions E1, E2 of the doped nitride-based semiconductor layer 502B protrude out two end portions of the conductive layer 504B. One of the end portions E1 of the doped nitride-based semiconductor layer 502B extends toward the electrode 20, and the other one of the end portions E2 extends toward the electrode 22. An extending length of the end portion E1 is different from that of the end portion E2. An extending length of the end portion E1 is less than that of the end portion E2. A side surface of the doped nitride-based semiconductor layer 502B is a vertical surface with respect to a top surface of the nitride-based semiconductor layer 16. Such a configuration can meet a specific device requirement.

FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1B as described and illustrated with reference to FIG. 3, except that each of the end portions E1, E2 of the doped nitride-based semiconductor layer 502C has a variable thickness. Specifically, the end portions E1, E2 of the doped nitride-based semiconductor layer 502C have two opposite side surfaces SS1, SS2, respectively, in which each of the side surfaces SS1, SS2 is an inclined side surface with respect to a top surface of the nitride-based semiconductor layer 16. The side surfaces SS1, SS2 of the doped nitride-based semiconductor layer 502C facing the

electrodes

20 and 22 have different oblique angles, respectively. Due to the configuration of inclined surface SS1/SS2, a linearly reduced 2DEG concentration drop/gap can occur under the inclined surface SS1/SS2, which means that extent of change/variation of the 2DEG concentration can be reduced. Thus, the semiconductor device 1C can have a better performance.

FIG. 5 is a vertical cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1B as described and illustrated with reference to FIG. 3, except that the doped nitride-based semiconductor layer 502D has two opposite side surfaces SS1, SS2, in which each of the side surfaces SS1, SS2 is a curved side surface. Such a configuration can meet a specific device requirement.

FIG. 6 is a vertical cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1B as described and illustrated with reference to FIG. 3, except that the side surface doped nitride-based semiconductor layer 50E has two opposite side surfaces SS1, SS2, in which the side surface SS1 is a curved surface, and the side surface SS2 is an inclined surface. Such a configuration can meet a specific device requirement.

FIG. 7 is a vertical cross-sectional view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1B as described and illustrated with reference to FIG. 3, except that the number of the

RESURF structures

501, 502 can be plural, for example, two. These

RESURF structures

501, 502 are physically separated. The RESURF structure 501 including a doped nitride-based semiconductor layer 5021 and a conductive layer 5041 is located directly under the field plate 30. The RESURF structure 502 including a doped nitride-based semiconductor layer 5022 and a conductive layer 5042 is located between the field plate 30 and the field plate 32. Such a configuration can meet a specific device requirement.

FIG. 8 is a vertical cross-sectional view of a semiconductor device 1G according to some embodiments of the present disclosure. The semiconductor device 1G is similar to the semiconductor device 1B as described and illustrated with reference to FIG. 3, except that the doped nitride-based semiconductor layer 502G has an end portion extending toward the electrode 22, and a side surface thereof forms a stepwise profile with multi-steps. Such a configuration can meet a specific device requirement.

Based on the above, in the present disclosure, a RESURF structure is formed in a region between the source and the drain field plates, and a conductive layer of the RESURF structure is electrically coupled to the source field plate. By such a configuration, a p-n diode formed between a doped nitride-based semiconductor layer of the RESURF structure and the 2DEG region is reverse biased as the device is in an off state, and thus a peak intensity of the electric field in such the region can be suppressed. Furthermore, the 2DEG concentration distribution can be controlled by the profile of the doped nitride-based semiconductor layer of the RESURF structure, so as to meet different device requirements

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap higher than a bandgap of the first nitride-based semiconductor layer;

a source electrode and a drain electrode disposed above the second nitride-based semiconductor layer;

a source field plate extending over and electrically coupled to the source electrode;

a drain field plate extending over and electrically coupled to the drain electrode; and

a reduced surface field (RESURF) structure disposed over the second nitride-based semiconductor layer and located between the source and drain field plates, wherein the RESURF structure further comprises a first doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a first conductive layer disposed on the first doped nitride-based semiconductor layer and electrically coupled to the source field plate.
The nitride-based semiconductor device any one of proceeding claims, further comprising a gate structure disposed between the RESURF structure and the source electrode, wherein the gate structure further comprises a second doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a second conductive layer disposed on the second doped nitride-based semiconductor layer.
The nitride-based semiconductor device any one of proceeding claims, wherein the second doped nitride-based semiconductor layer of the gate structure is thick enough to deplete a zone of the 2DEG region directly under the second doped nitride-based semiconductor layer.
The nitride-based semiconductor device any one of proceeding claims, wherein the first doped nitride-based semiconductor layer of the RESURF structure is thin enough, such that a zone of the 2DEG region directly under the first doped nitride-based semiconductor layer has a smaller or equal to electron density than that of the remaining zone of the 2DEG region.
The nitride-based semiconductor device any one of proceeding claims, wherein a zone of the 2DEG region from the gate structure to the drain electrode is continuous.
The nitride-based semiconductor device any one of proceeding claims, wherein the first doped nitride-based semiconductor layer of the RESURF structure is compositionally the same as the second doped nitride-based semiconductor layer of the gate structure, and the first conductive layer of the RESURF structure is compositionally the same as the second conductive layer of the gate structure.
The nitride-based semiconductor device any one of proceeding claims, wherein an average thickness of the second doped nitride-based semiconductor layer of the gate structure is greater than that of the second doped nitride-based semiconductor layer of the RESURF structure.
The nitride-based semiconductor device any one of proceeding claims, further comprising at least one field plate disposed between the gate structure and the RESURF structure.
The nitride-based semiconductor device any one of proceeding claims, wherein the at least one field plate is electrically coupled to the source field plate.
The nitride-based semiconductor device any one of proceeding claims, wherein the at least one field plate comprises a plurality of field plates, and the field plates are located at different heights, respectively.
The nitride-based semiconductor device any one of proceeding claims, further comprising a contact via extending vertically to make contact with the first conductive layer and the source field plate, such that the first conductive layer and the source field plate have substantially the same voltage level.
The nitride-based semiconductor device any one of proceeding claims, wherein the source field plate extends horizontally from a position over the source electrode to a position directly above the RESURF structure.
The nitride-based semiconductor device any one of proceeding claims, wherein the first doped nitride-based semiconductor layer has a first end portion extending toward the source electrode and a second end portion extending toward the drain electrode.
The nitride-based semiconductor device any one of proceeding claims, wherein at least one of the first and second portion has a variable thickness.
The nitride-based semiconductor device any one of proceeding claims, wherein an extending length of the first portion is different from an extending length of the second portion.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer over a substrate;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a blanket doped nitride-based semiconductor layer over the second nitride-based semiconductor layer;

thinning the blanket doped nitride-based semiconductor layer, such that the blanket doped nitride-based semiconductor layer has a first portion and a second portion thinner than the first portion;

forming a blanket conductive layer on the thinned blanket doped nitride-based semiconductor layer;

removing portions of the blanket doped nitride-based semiconductor layer and the blanket conductive layer, such that a gate structure and a reduced surface field (RESURF) structure are formed, wherein the gate structure has the first portion and the RESURF structure has the remaining portion of the second portion;

forming a source and a drain electrodes over the second nitride-based semiconductor layer, such that the gate structure and the RESURF structure are located between the source and the drain electrodes; and

forming a source and a drain field plates electrically coupled to the source and the drain electrodes, respectively, wherein the RESURF structure is located between the source and the drain field plates.
The method of any one of proceeding claims, wherein remaining portions of the blanket conductive layer are remained on top surfaces of the first portion and the remaining portion of the second portion to serve as a first conducive layer of the RESURF structure and a second conductive layer of the gate structure.
The method of any one of proceeding claims, further comprising:

forming at least one field plate between the gate structure and the RESURF structure.
The method of any one of proceeding claims, further comprising:

forming a dielectric layer to cover the source, drain electrodes, the gate structure, and the RESURF structure.
The method of any one of proceeding claims, wherein the source and the drain field plates are formed on a top surface of the dielectric layer.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap higher than a bandgap of the first nitride-based semiconductor layer;

a source electrode and a drain electrode disposed above the second nitride-based semiconductor layer;

a source field plate electrically coupled to the source electrode;

a drain field plate electrically coupled to the drain electrode;

a reduced surface field (RESURF) structure disposed over the second nitride-based semiconductor layer, wherein the RESURF structure extends horizontally, such that at least an end portion of the RESURF structure is located between the source and drain field plates;

a gate structure disposed over the second nitride-based semiconductor layer and located between the RESURF structure and the source electrode; and

at least a field plate located directly under the source field plate, wherein an entirety of the field plate is located between the RESURF structure and the gate structure.
The nitride-based semiconductor device of any one of proceeding claims, wherein the RESURF structure further comprises a first p-type doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a first conductive layer making contact with a top surface of the first p-type doped nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of proceeding claims, wherein the first p-type doped nitride-based semiconductor layer and the 2DEG region collectively form a p-n diode, wherein the p-n diode is reverse biased as the nitride-based semiconductor device is in an off-state.
The nitride-based semiconductor device of any one of proceeding claims, wherein the first p-type doped nitride-based semiconductor layer has a side surface, wherein the side surface is a curved surface, a vertical surface, or an inclined surface.
The nitride-based semiconductor device of any one of proceeding claims, wherein the gate structure further comprises a second p-type doped nitride-based semiconductor layer making contact with the second nitride-based semiconductor layer and a second conductive layer making contact with a top surface of the second p-type doped nitride-based semiconductor layer, wherein an average thickness of the second p-type doped nitride-based semiconductor layer is greater than that of the first p-type doped nitride-based semiconductor layer.