WO2024016219A1 - Nitride-based semiconductor device and method for manufacturing the same - Google Patents

Nitride-based semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2024016219A1
WO2024016219A1 PCT/CN2022/106785 CN2022106785W WO2024016219A1 WO 2024016219 A1 WO2024016219 A1 WO 2024016219A1 CN 2022106785 W CN2022106785 W CN 2022106785W WO 2024016219 A1 WO2024016219 A1 WO 2024016219A1
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Prior art keywords
nitride
based semiconductor
layer
dielectric
field plate
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PCT/CN2022/106785
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French (fr)
Inventor
Han-Chin Chiu
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Innoscience (suzhou) Semiconductor Co., Ltd.
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Priority to PCT/CN2022/106785 priority Critical patent/WO2024016219A1/en
Publication of WO2024016219A1 publication Critical patent/WO2024016219A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having dielectric layers to modulate equivalent dielectric constant distribution over a barrier layer.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a passivation layer, a first dielectric layer, a second dielectric layer, and a first field plate.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the doped nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer.
  • the passivation layer covers the third nitride-based semiconductor layer.
  • the first dielectric layer is disposed within the passivation layer and abuts against the passivation layer.
  • the second dielectric layer is disposed within the passivation layer and abuts against the passivation layer, in which the first and second dielectric layers are separated from each other.
  • the first field plate laterally extends over the second nitride-based semiconductor layer and the first dielectric layer.
  • a method for manufacturing a nitride-based device includes steps as follows.
  • a first nitride-based semiconductor layer is formed.
  • a second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer.
  • a doped nitride-based semiconductor layer is formed on the second nitride-based semiconductor layer.
  • a passivation layer is formed on the second nitride-based semiconductor layer to cover the third nitride-based semiconductor layer.
  • a first portion and a second portion of the passivation layer are removed to form two trenches.
  • a first dielectric layer and a second dielectric layer are formed to fill the trenches of the passivation layer.
  • a first field plate is formed to at least laterally extend over the first dielectric layer.
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a passivation layer, a first field plate, and a first dielectric layer.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the doped nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer.
  • the passivation layer covers the third nitride-based semiconductor layer.
  • the first field plate laterally extends over the second nitride-based semiconductor layer.
  • the first dielectric layer is disposed between the second nitride-based semiconductor layer and the first field plate and in contact with the second nitride-based semiconductor layer.
  • the first field plate at least can be operated stably and function well as complying with the device design.
  • FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 1B is a top view of the nitride-based semiconductor device of FIG. 1A;
  • FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing the nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 7 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 8 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, an electron blocking layer 14, nitride-based semiconductor layers 16 and 18, a doped III-V semiconductor layer 20, passivation layers 30 and 60, electrodes 32, 34, 36, dielectric layers 40 and 42, field plates 50 and 52.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the buffer layer 12 can be disposed between the substrate 10 and the electron blocking layer 14.
  • the buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the electron blocking layer 14, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the nitride-based semiconductor device 1A further includes a nucleation layer (not illustrated) .
  • the nucleation layer may be formed between the substrate 10 and the buffer layer 12.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the electron blocking layer 14 can be disposed between the buffer layer 12 and the nitride-based semiconductor layer 16.
  • the electron blocking layer 14 may include Al x Ga (1-x) N, where 0 ⁇ x ⁇ 1.
  • the electron blocking layer 14 may have a high bandgap.
  • the electron blocking layer 14 may be doped as being p-type.
  • the electron blocking layer 14 may have an AlGaN/GaN super-lattice structure, including alternating layers of AlGaN and GaN.
  • the nitride-based semiconductor layer 16 is disposed over the substrate 10.
  • the nitride-based semiconductor layer 18 is disposed on the nitride-based semiconductor layer 16.
  • the exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 18 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 16 and 18 are selected such that the nitride-based semiconductor layer 18 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 16, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 16 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 18 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 16 and 18 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the doped III-V semiconductor layer 20 is disposed on/over/above the nitride-based semiconductor layer 18.
  • the doped III-V semiconductor layer 20 may be p-type.
  • the doped III-V semiconductor layer 20 is configured to bring the device into enhancement mode.
  • the doped III-V semiconductor layer 20 can be a p-type doped III-V semiconductor layer.
  • the exemplary materials of the doped III-V semiconductor layer 20 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the passivation layer 30 is disposed over the nitride-based semiconductor layer 18.
  • the passivation layer 30 covers the doped III-V semiconductor layer 20.
  • the passivation layer 30 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) .
  • the exemplary materials of the passivation layer 30 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof.
  • the passivation layer 30 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the electrodes 32 and 34 are disposed on the nitride-based semiconductor layer 18.
  • the electrodes 32 and 34 can upward extend to a position higher than the passivation 30.
  • Each of the electrodes 32 and 34 can serve as a source electrode or a drain electrode.
  • Each of the electrodes 32 and 34 can serve as a source contact via or a drain contact via.
  • the electrodes 32 and 34 can penetrate the passivation layer to make contact with the nitride-based semiconductor layer 18.
  • a distance between the electrode 32 and the doped III-V semiconductor layer 20 is less than a distance between the electrode 34 and the doped III-V semiconductor layer 20. Accordingly, the electrode 32 is closer to the doped III-V semiconductor layer 20 than the electrode 34. Such the configuration is made to match high-voltage requirement.
  • the electrodes 32 and 34 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 32 and 34 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 32 and 34 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 32 and 34 form ohmic contact with the nitride-based semiconductor layer 18. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 32 and 34.
  • each of the electrodes 32 and 34 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • the electrode 36 is disposed on/above/over the nitride-based semiconductor layer 18.
  • the electrode 36 is disposed on/above/over the doped III-V semiconductor layer 20.
  • the electrode 36 can serve as a gate electrode.
  • the electrode 36 can serve as a gate contact via.
  • the electrode 36 can upward extend to a position higher than the passivation layer 30.
  • the electrode 36 can penetrate the passivation layer 30 to make contact with the nitride-based semiconductor layer 20.
  • the exemplary materials of the electrode 36 may include metals or metal compounds.
  • the electrode 36 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the dielectric layers 40 and 42 are disposed on/above/over the nitride-based semiconductor layer 18.
  • the dielectric layers 40 and 42 are in contact with the nitride-based semiconductor layer 18.
  • the dielectric layers 40 and 42 are disposed within the passivation layer 30.
  • the dielectric layers 40 and 42 are separated from each other.
  • the dielectric layer 42 is located between the dielectric layer 40 and the electrode 34.
  • the dielectric layer 40 is in contact with the passivation layer 30.
  • the dielectric layer 40 abuts against the passivation layer 30.
  • the dielectric layer 40 is substantially coplanar with a top surface of the passivation layer 30.
  • the dielectric layer 40 may have dielectric constant different than dielectric constant of the passivation 30.
  • the dielectric layer 40 may have a dielectric material different than that of the passivation 30.
  • the dielectric layer 42 is in contact with the passivation layer 30.
  • the dielectric layer 42 abuts against the passivation layer 30.
  • the dielectric layer 42 is substantially coplanar with the top surface of the passivation layer 30.
  • the dielectric layer 42 may have dielectric constant different than dielectric constant of the passivation 30.
  • the dielectric layer 42 may have a dielectric material different than that of the passivation 30.
  • a gate-drain side may require modulation to electric field there. Accordingly, at least one field plate is to be formed near the gate-drain side.
  • equivalent dielectric constant distribution over the nitride-based semiconductor layer 18 serves as a factor for avoiding breakdown.
  • the dielectric constant of the dielectric layers 40 and 42 can be tuned for complying with design requirements.
  • the passivation layer 30 can be formed in low cost and high deposition speed, the dielectric constant of the passivation layer 30 may not match conductive field plates enough. Therefore, regions aligning field plate to be formed can be filled with dielectric layers which have different dielectric constant than the passivation layer 30, so as to tune equivalent dielectric constant distribution over the nitride-based semiconductor layer 18.
  • the dielectric layer 40 may have the dielectric constant different than the dielectric constant of the dielectric layer 42.
  • a distance from the doped III-V semiconductor layer 20 to the dielectric layer 40 is less than a distance from the dielectric layer 40 to the electrode 34.
  • the location of the dielectric layers 40 and 42 is designed to comply with field plates to be formed for modulation to electric field distribution. Accordingly, the doped III-V semiconductor layer 20 can be closer to the dielectric layer 40 than the electrode 34.
  • the field plate 50 is disposed over the nitride-based semiconductor layer 18 and the dielectric layer 40.
  • the field plate 50 laterally extends over the nitride-based semiconductor layer 18 and the dielectric layer 40.
  • the field plate 52 is disposed over the nitride-based semiconductor layer 18 and the dielectric layer 42.
  • the field plate 50 laterally extends over the nitride-based semiconductor layer 18 and the dielectric layer 42.
  • the field plates 50 and 52 are spaced apart from each other. At least one gap is present between the field plates 50 and 52.
  • the dielectric layers 40 and 42 By the dielectric layers 40 and 42, the equivalent dielectric constant distribution over the nitride-based semiconductor layer 18 is tuned so unwanted defect can be avoided, such as unexpected parasitic capacitance, breakdown across dielectric medium. Therefore, the field plates 50 and 52 can be operated stably and function well as complying with the device design. Furthermore, in some embodiments, the materials of the dielectric layers 40 and 42 can be different than that of the passivation layer 30 and are selected to make the field plates 50 and 52 adhered to the dielectric layers 40 and 42 well, so at to avoid peeling.
  • the field plates 50 and 52 can be formed from the same single layer. In some embodiments, the field plates 50 and 52 have the same thickness. In some embodiments, the field plates 50 and 52 are horizontally overlapped with each other, which can simplify a manufacturing process of the field plates 50 and 52.
  • FIG. 1B is a top view of the nitride-based semiconductor device 1A of FIG. 1A.
  • the electrodes 32, 34, and 36 can be formed to have strip shape.
  • the electrodes 32, 34, and 36 are parallel with each other.
  • the field plates 50 and 52 can be formed to have strip shape.
  • the field plates 50 and 52 are parallel with each other.
  • the electrodes 32, 34, and 36 and the field plates 50 and 52 are parallel with each other.
  • the field plates 50 and 52 may include metals or metal compounds.
  • the field plates 50 and 52 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the passivation layer 60 is disposed over the passivation layer 30.
  • the passivation layer 60 covers the passivation layer 30.
  • the passivation layer 60 covers the field plates 50 and 52.
  • the electrodes 32, 34, and 36 penetrate the passivation layer 60.
  • the passivation layer 60 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) .
  • the exemplary materials of the passivation layers 40 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof.
  • the passivation layers 40 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a substrate 10 is provided.
  • a buffer layer 12 is formed on the substrate 10.
  • An electron blocking layer 14 is formed on the substrate 10.
  • Nitride-based semiconductor layers 16 and 18 are formed over the substrate 10, the buffer layer 12, and the electron blocking layer 14 in sequence.
  • a doped III-V semiconductor layer 20 is formed over the nitride-based semiconductor layers 16 and 18.
  • a nitride-based semiconductor layer 22 can be formed on the nitride-based semiconductor layer 18. In some embodiments, the nitride-based semiconductor layer 22 can be formed from patterning a blanket nitride-based semiconductor layer.
  • a passivation layer 30 is formed on the nitride-based semiconductor layer 18 to cover the doped III-V semiconductor layer 20.
  • a removing process is performed on the passivation layer 30. Some portions of the passivation layer 30 are removed so trenches 302 and 304 are formed. Some of the nitride-based semiconductor layer 18 can be exposed from the trenches 302 and 304.
  • dielectric layers 40 and 42 are formed within the trenches 302 and 304 of the passivation layer 30.
  • the dielectric layers 40 and 42 are formed to fill the trenches 302 and 304 of the passivation layer 30.
  • the dielectric layers 40 and 42 can be formed by patterning a single dielectric bulk.
  • a dielectric structure can be formed to cover the passivation layer 30 and to fill the trenches 302 and 304 of the passivation layer 30. Thereafter, the dielectric structure is thinned such that the passivation layer 30 is exposed and the dielectric layers 40 and 42 remain in the trenches 302 and 304 of the passivation layer 30.
  • a blanket conductive layer 70 is formed on the nitride-based semiconductor layer 18 and the passivation layer 30. The blanket conductive layer 70 covers the dielectric layers 40 and 42.
  • the blanket conductive layer 70 is patterned to form field plates 50 and 52.
  • the filed plate 50 is formed to at least laterally extend over the dielectric layer 40.
  • the filed plate 52 is formed to at least laterally extend over the dielectric layer 42.
  • patterning the blanket conductive layer 70 includes at least one etch process. The etch process is performed so as to make the field plates 50 and 52 separated from each other. After the field plates 50 and 52 are formed, electrodes or contact vias can be formed to obtain the structure as shown in FIG. 1A.
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the field plates 50 and 52 are replaced by the field plates 50B and 52B.
  • the filed plate 50B is wider than the dielectric layer 40; and the filed plate 52B is wider than the dielectric layer 42. Therefore, a distance between the field plates 50B and 52B is less than a distance between the dielectric layers 40 and 42.
  • the extending lengths of the field plates 50B and 52B can be flexible, which will be advantageous to complying with more device design requirements.
  • the field plates 50B and 52B may have different extending lengths, which can make the field plates 50B and 52B aim at peaks of electric line distribution. Since the field plate 50B is closer the gate-drain side than the field plate 52B, the field plate can have the extending length greater than the extending length of the field plate 52B.
  • the field plates 50B and 52B wider than the dielectric layers 40 and 42 can extend to make contact with the passivation layer 30.
  • the field plate 50B can extend from the dielectric layer 40 to the passivation layer 30.
  • the field plate 52B can extend from the dielectric layer 42 to the passivation layer 30.
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the field plates 50 and 52 are replaced by field plates 50C and 52C and the nitride-based semiconductor device 1C further includes a field plate 54C.
  • the field plates 50C and 52C are disposed on the dielectric layers 40 and 42, respectively. As afore-mentioned, the field plates 50C and 52C can have different extending lengths.
  • the field plate 54C is disposed on the passivation layer 30.
  • the field plate 54C is in contact with the passivation layer 30.
  • the field plate 54C is located between the field plates 50C and 52C.
  • the field plate 54C is narrower than the field plates 50C and 52C. The reason is dialectic constant of medium beneath the field plate 54C is provided by the passivation layer 30 so the field plate 54C is narrower to avoid too strong parasitic capacitance.
  • the field plates 50C, 52C, 54C may have substantially the same thickness.
  • the field plates 50C, 52C, 54C may be formed from the same blanket conductive layer.
  • the field plate number can be flexible, which will be advantageous to complying with more device design requirements.
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the field plate 50 is replaced by field plate 50D and the field plate 52 is omitted.
  • the field plate 50D is disposed on the passivation layer 30 and the dielectric layers 40 and 42.
  • the field plate 50D continuously extends to cover the passivation layer 30 and the dielectric layers 40 and 42.
  • FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the dielectric layers 40 and 42 are replaced by dielectric layers 40E and 42E and the field plates 50 and 52 are replaced by the field plates 50E and 52E.
  • the dielectric layers 40E and 42E are thinner than the passivation layer 30. During the formation of the dielectric layers 40E and 42E, the dielectric structure as afore mentioned can be thinned to make the dielectric layers 40E and 42E have thickness less than that of the passivation layer 30.
  • the field plate 50E can form an interface with the dielectric layer 40E in a position lower than a top surface of the passivation layer 30.
  • the field plate 52E can form an interface with the dielectric layer 42E in a position lower than a top surface of the passivation layer 30.
  • Such the configuration is advantageous to alignment of the field plates 50E and 52E with respect to the dielectric layers 40E and 42E, respectively.
  • the yield rate of the nitride-based semiconductor device 1E can get improved since misalignment of the field plates 50E and 52E with respect to the top surfaces of the dielectric layers 40E and 42 is reduced.
  • FIG. 7 is a top view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1B, except that the field plates 50 and 52 are replaced by the field plates 50F and 52F.
  • the field plates 50F and 52F viewed along a direction normal to the passivation layer 30 have different edge profiles. Specifically, the right edge profile of the field plate 50F has projections; and the left edge profile of the field plate 52F has concaves which align the projections. Such the configuration is made based on the consideration of the on-state resistance and the direction of current flow at on-state.
  • FIG. 8 is a top view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1B, except that the field plates 50 and 52 are replaced by the field plates 50G and 52G.
  • the field plates 50G and 52G viewed along a direction normal to the passivation layer 30 are connected to each other. Hollow areas are located between the field plates 50G and 52G.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer (16), a second nitride-based semiconductor layer (18), a doped nitride-based semiconductor layer (20), a passivation layer (30), a first dielectric layer (40), a second dielectric layer (42), and a first field plate (50). The second nitride-based semiconductor layer (18) is disposed on the first nitride-based semiconductor layer (16) and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer (16). The doped nitride-based semiconductor layer (20) is disposed on the second nitride-based semiconductor layer (18). The passivation layer (30) covers the second nitride-based semiconductor layer (18). The first dielectric layer (40) is disposed within the passivation layer (30) and abuts against the passivation layer (30). The second dielectric layer (42) is disposed within the passivation layer (30) and abuts against the passivation layer (30), in which the first and second dielectric layers (40,42) are separated from each other. The first field plate (50) laterally extends over the second nitride-based semiconductor layer (18) and the first dielectric layer (40).

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Inventors: Han-Chin CHIU
Field of the Disclosure:
The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having dielectric layers to modulate equivalent dielectric constant distribution over a barrier layer.
Background of the Disclosure:
In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
Summary of the Disclosure:
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a passivation layer, a first dielectric layer, a second dielectric layer, and a first field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer. The passivation layer covers the third nitride-based semiconductor layer. The first dielectric layer is disposed within the passivation layer and abuts against the passivation layer. The second dielectric layer is disposed within the passivation layer and abuts against the passivation layer, in which the first and second dielectric layers are separated from each other. The first field plate laterally extends over the second nitride-based semiconductor layer and the first dielectric layer.
In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first  nitride-based semiconductor layer. A doped nitride-based semiconductor layer is formed on the second nitride-based semiconductor layer. A passivation layer is formed on the second nitride-based semiconductor layer to cover the third nitride-based semiconductor layer. A first portion and a second portion of the passivation layer are removed to form two trenches. A first dielectric layer and a second dielectric layer are formed to fill the trenches of the passivation layer. A first field plate is formed to at least laterally extend over the first dielectric layer.
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a passivation layer, a first field plate, and a first dielectric layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer. The passivation layer covers the third nitride-based semiconductor layer. The first field plate laterally extends over the second nitride-based semiconductor layer. The first dielectric layer is disposed between the second nitride-based semiconductor layer and the first field plate and in contact with the second nitride-based semiconductor layer.
By applying the above configuration, which is provided by the first and second dielectric layers, equivalent dielectric constant distribution over the second nitride-based semiconductor layer is tuned so unwanted defect can be avoided, such as unexpected parasitic capacitance, breakdown across dielectric medium. Therefore, the first field plate at least can be operated stably and function well as complying with the device design.
Brief Description of the Drawings:
Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 1B is a top view of the nitride-based semiconductor device of FIG. 1A;
FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing the nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;
FIG. 7 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and
FIG. 8 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
Detailed Description:
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be  omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, an electron blocking layer 14, nitride-based semiconductor layers 16 and 18, a doped III-V semiconductor layer 20, passivation layers 30 and 60,  electrodes  32, 34, 36,  dielectric layers  40 and 42,  field plates  50 and 52.
The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
The buffer layer 12 can be disposed between the substrate 10 and the electron blocking layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the electron blocking layer 14, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
In some embodiments, the nitride-based semiconductor device 1A further includes a nucleation layer (not illustrated) . The nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
The electron blocking layer 14 can be disposed between the buffer layer 12 and the nitride-based semiconductor layer 16. The electron blocking layer 14 may include Al xGa  (1-x) N, where 0≤ x ≤1. In some embodiments, the electron blocking layer 14 may have a high bandgap. In some embodiments, the electron blocking layer 14 may be doped as being p-type. In some embodiments, the electron blocking layer 14 may have an AlGaN/GaN super-lattice structure, including alternating layers of AlGaN and GaN.
The nitride-based semiconductor layer 16 is disposed over the substrate 10. The nitride-based semiconductor layer 18 is disposed on the nitride-based semiconductor layer 16. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1. The exemplary materials of the nitride-based semiconductor layer 18 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1.
The exemplary materials of the nitride-based semiconductor layers 16 and 18 are selected such that the nitride-based semiconductor layer 18 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 16, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 16 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 18 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 16 and 18 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
The doped III-V semiconductor layer 20 is disposed on/over/above the nitride-based semiconductor layer 18. The doped III-V semiconductor layer 20 may be p-type. The doped III-V semiconductor layer 20 is configured to bring the device into enhancement mode. The doped III-V semiconductor layer 20 can be a p-type doped III-V semiconductor layer.
The exemplary materials of the doped III-V semiconductor layer 20 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
The passivation layer 30 is disposed over the nitride-based semiconductor layer 18. The passivation layer 30 covers the doped III-V semiconductor layer 20. The passivation layer 30 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) . The exemplary materials of the passivation layer 30 can include, for example but are not limited to, SiN x, SiO x, Si 3N 4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof. In some  embodiments, the passivation layer 30 can be a multi-layered structure, such as a composite dielectric layer of Al 2O 3/SiN, Al 2O 3/SiO 2, AlN/SiN, AlN/SiO 2, or combinations thereof.
The  electrodes  32 and 34 are disposed on the nitride-based semiconductor layer 18. The  electrodes  32 and 34 can upward extend to a position higher than the passivation 30. Each of the  electrodes  32 and 34 can serve as a source electrode or a drain electrode. Each of the  electrodes  32 and 34 can serve as a source contact via or a drain contact via. The  electrodes  32 and 34 can penetrate the passivation layer to make contact with the nitride-based semiconductor layer 18.
In the exemplary illustration of FIG. 1A, a distance between the electrode 32 and the doped III-V semiconductor layer 20 is less than a distance between the electrode 34 and the doped III-V semiconductor layer 20. Accordingly, the electrode 32 is closer to the doped III-V semiconductor layer 20 than the electrode 34. Such the configuration is made to match high-voltage requirement.
In some embodiments, the  electrodes  32 and 34 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the  electrodes  32 and 34 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The  electrodes  32 and 34 may be a single layer, or plural layers of the same or different composition. In some embodiments, the  electrodes  32 and 34 form ohmic contact with the nitride-based semiconductor layer 18. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the  electrodes  32 and 34.
In some embodiments, each of the  electrodes  32 and 34 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
The electrode 36 is disposed on/above/over the nitride-based semiconductor layer 18. The electrode 36 is disposed on/above/over the doped III-V semiconductor layer 20. The electrode 36 can serve as a gate electrode. The electrode 36 can serve as a gate contact via. The electrode 36 can upward extend to a position higher than the passivation layer 30. The electrode 36 can penetrate the passivation layer 30 to make contact with the nitride-based semiconductor layer 20.
The exemplary materials of the electrode 36 may include metals or metal compounds. The electrode 36 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for  example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
The dielectric layers 40 and 42 are disposed on/above/over the nitride-based semiconductor layer 18. The dielectric layers 40 and 42 are in contact with the nitride-based semiconductor layer 18. The dielectric layers 40 and 42 are disposed within the passivation layer 30. The dielectric layers 40 and 42 are separated from each other. The dielectric layer 42 is located between the dielectric layer 40 and the electrode 34.
The dielectric layer 40 is in contact with the passivation layer 30. The dielectric layer 40 abuts against the passivation layer 30. The dielectric layer 40 is substantially coplanar with a top surface of the passivation layer 30. The dielectric layer 40 may have dielectric constant different than dielectric constant of the passivation 30. The dielectric layer 40 may have a dielectric material different than that of the passivation 30.
The dielectric layer 42 is in contact with the passivation layer 30. The dielectric layer 42 abuts against the passivation layer 30. The dielectric layer 42 is substantially coplanar with the top surface of the passivation layer 30. The dielectric layer 42 may have dielectric constant different than dielectric constant of the passivation 30. The dielectric layer 42 may have a dielectric material different than that of the passivation 30.
With respect to a nitride device, a gate-drain side may require modulation to electric field there. Accordingly, at least one field plate is to be formed near the gate-drain side. In addition to the modulation by field plates, equivalent dielectric constant distribution over the nitride-based semiconductor layer 18 serves as a factor for avoiding breakdown.
The dielectric constant of the  dielectric layers  40 and 42 can be tuned for complying with design requirements. For example, although the passivation layer 30 can be formed in low cost and high deposition speed, the dielectric constant of the passivation layer 30 may not match conductive field plates enough. Therefore, regions aligning field plate to be formed can be filled with dielectric layers which have different dielectric constant than the passivation layer 30, so as to tune equivalent dielectric constant distribution over the nitride-based semiconductor layer 18. In some the dielectric layer 40 may have the dielectric constant different than the dielectric constant of the dielectric layer 42.
A distance from the doped III-V semiconductor layer 20 to the dielectric layer 40 is less than a distance from the dielectric layer 40 to the electrode 34. The location of the  dielectric layers  40 and 42 is designed to comply with field plates to be formed for modulation to electric field distribution. Accordingly, the doped III-V semiconductor layer 20 can be closer to the dielectric layer 40 than the electrode 34.
The field plate 50 is disposed over the nitride-based semiconductor layer 18 and the dielectric layer 40. The field plate 50 laterally extends over the nitride-based semiconductor layer 18 and the dielectric layer 40. The field plate 52 is disposed over the nitride-based semiconductor layer 18 and the dielectric layer 42. The field plate 50 laterally extends over the nitride-based semiconductor layer 18 and the dielectric layer 42. The  field plates  50 and 52 are spaced apart from each other. At least one gap is present between the  field plates  50 and 52.
By the  dielectric layers  40 and 42, the equivalent dielectric constant distribution over the nitride-based semiconductor layer 18 is tuned so unwanted defect can be avoided, such as unexpected parasitic capacitance, breakdown across dielectric medium. Therefore, the  field plates  50 and 52 can be operated stably and function well as complying with the device design. Furthermore, in some embodiments, the materials of the  dielectric layers  40 and 42 can be different than that of the passivation layer 30 and are selected to make the  field plates  50 and 52 adhered to the  dielectric layers  40 and 42 well, so at to avoid peeling.
In some embodiments, the  field plates  50 and 52 can be formed from the same single layer. In some embodiments, the  field plates  50 and 52 have the same thickness. In some embodiments, the  field plates  50 and 52 are horizontally overlapped with each other, which can simplify a manufacturing process of the  field plates  50 and 52.
FIG. 1B is a top view of the nitride-based semiconductor device 1A of FIG. 1A. The  electrodes  32, 34, and 36 can be formed to have strip shape. The  electrodes  32, 34, and 36 are parallel with each other. The  field plates  50 and 52 can be formed to have strip shape. The  field plates  50 and 52 are parallel with each other. The  electrodes  32, 34, and 36 and the  field plates  50 and 52 are parallel with each other.
Referring to FIG. 1A again, the  field plates  50 and 52 may include metals or metal compounds. The  field plates  50 and 52 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
The passivation layer 60 is disposed over the passivation layer 30. The passivation layer 60 covers the passivation layer 30. The passivation layer 60 covers the  field plates  50 and 52. The  electrodes  32, 34, and 36 penetrate the passivation layer 60. The passivation layer 60 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) . The exemplary materials of the passivation layers 40 can include, for example but are not limited to, SiN x, SiO x, Si 3N 4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, or combinations thereof. In some  embodiments, the passivation layers 40 can be a multi-layered structure, such as a composite dielectric layer of Al 2O 3/SiN, Al 2O 3/SiO 2, AlN/SiN, AlN/SiO 2, or combinations thereof.
Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on the substrate 10. An electron blocking layer 14 is formed on the substrate 10. Nitride-based semiconductor layers 16 and 18 are formed over the substrate 10, the buffer layer 12, and the electron blocking layer 14 in sequence. A doped III-V semiconductor layer 20 is formed over the nitride-based semiconductor layers 16 and 18. A nitride-based semiconductor layer 22 can be formed on the nitride-based semiconductor layer 18. In some embodiments, the nitride-based semiconductor layer 22 can be formed from patterning a blanket nitride-based semiconductor layer. A passivation layer 30 is formed on the nitride-based semiconductor layer 18 to cover the doped III-V semiconductor layer 20.
Referring to FIG. 2B, a removing process is performed on the passivation layer 30. Some portions of the passivation layer 30 are removed so  trenches  302 and 304 are formed. Some of the nitride-based semiconductor layer 18 can be exposed from the  trenches  302 and 304. The
Referring to FIG. 2C,  dielectric layers  40 and 42 are formed within the  trenches  302 and 304 of the passivation layer 30. The dielectric layers 40 and 42 are formed to fill the  trenches  302 and 304 of the passivation layer 30. The dielectric layers 40 and 42 can be formed by patterning a single dielectric bulk. For example, a dielectric structure can be formed to cover the passivation layer 30 and to fill the  trenches  302 and 304 of the passivation layer 30. Thereafter, the dielectric structure is thinned such that the passivation layer 30 is exposed and the  dielectric layers  40 and 42 remain in the  trenches  302 and 304 of the passivation layer 30. A blanket conductive layer 70 is formed on the nitride-based semiconductor layer 18 and the passivation layer 30. The blanket conductive layer 70 covers the  dielectric layers  40 and 42.
Referring to FIG. 2D, the blanket conductive layer 70 is patterned to form  field plates  50 and 52. The filed plate 50 is formed to at least laterally extend over the dielectric layer 40. The filed plate 52 is formed to at least laterally extend over the dielectric layer 42. In some embodiments, patterning the blanket conductive layer 70 includes at least one etch process. The etch process is performed so as to make the  field plates  50 and 52 separated from each other. After the  field  plates  50 and 52 are formed, electrodes or contact vias can be formed to obtain the structure as shown in FIG. 1A.
FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the  field plates  50 and 52 are replaced by the  field plates  50B and 52B.
In the exemplary illustration of FIG. 3, the filed plate 50B is wider than the dielectric layer 40; and the filed plate 52B is wider than the dielectric layer 42. Therefore, a distance between the  field plates  50B and 52B is less than a distance between the  dielectric layers  40 and 42.
As the equivalent dielectric constant distribution over the nitride-based semiconductor layer 18 is tuned, the extending lengths of the  field plates  50B and 52B can be flexible, which will be advantageous to complying with more device design requirements.
The  field plates  50B and 52B may have different extending lengths, which can make the  field plates  50B and 52B aim at peaks of electric line distribution. Since the field plate 50B is closer the gate-drain side than the field plate 52B, the field plate can have the extending length greater than the extending length of the field plate 52B. The  field plates  50B and 52B wider than the  dielectric layers  40 and 42 can extend to make contact with the passivation layer 30. The field plate 50B can extend from the dielectric layer 40 to the passivation layer 30. The field plate 52B can extend from the dielectric layer 42 to the passivation layer 30.
FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the  field plates  50 and 52 are replaced by  field plates  50C and 52C and the nitride-based semiconductor device 1C further includes a field plate 54C.
The  field plates  50C and 52C are disposed on the  dielectric layers  40 and 42, respectively. As afore-mentioned, the  field plates  50C and 52C can have different extending lengths. The field plate 54C is disposed on the passivation layer 30. The field plate 54C is in contact with the passivation layer 30. The field plate 54C is located between the  field plates  50C and 52C. The field plate 54C is narrower than the  field plates  50C and 52C. The reason is dialectic constant of medium beneath the field plate 54C is provided by the passivation layer 30 so the field plate 54C is narrower to avoid too strong parasitic capacitance.
The  field plates  50C, 52C, 54C may have substantially the same thickness. The  field plates  50C, 52C, 54C may be formed from the same blanket conductive layer. As the equivalent  dielectric constant distribution over the nitride-based semiconductor layer 18 is tuned, the field plate number can be flexible, which will be advantageous to complying with more device design requirements.
FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the field plate 50 is replaced by field plate 50D and the field plate 52 is omitted. The field plate 50D is disposed on the passivation layer 30 and the  dielectric layers  40 and 42. The field plate 50D continuously extends to cover the passivation layer 30 and the  dielectric layers  40 and 42.
FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the  dielectric layers  40 and 42 are replaced by  dielectric layers  40E and 42E and the  field plates  50 and 52 are replaced by the  field plates  50E and 52E.
The  dielectric layers  40E and 42E are thinner than the passivation layer 30. During the formation of the  dielectric layers  40E and 42E, the dielectric structure as afore mentioned can be thinned to make the  dielectric layers  40E and 42E have thickness less than that of the passivation layer 30.
Accordingly, the field plate 50E can form an interface with the dielectric layer 40E in a position lower than a top surface of the passivation layer 30. Similarly, the field plate 52E can form an interface with the dielectric layer 42E in a position lower than a top surface of the passivation layer 30. Such the configuration is advantageous to alignment of the  field plates  50E and 52E with respect to the  dielectric layers  40E and 42E, respectively. By the configuration, the yield rate of the nitride-based semiconductor device 1E can get improved since misalignment of the  field plates  50E and 52E with respect to the top surfaces of the  dielectric layers  40E and 42 is reduced.
FIG. 7 is a top view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1B, except that the  field plates  50 and 52 are replaced by the  field plates  50F and 52F.
In the exemplary illustration of FIG. 7, the  field plates  50F and 52F viewed along a direction normal to the passivation layer 30 have different edge profiles. Specifically, the right edge profile of the field plate 50F has projections; and the left edge profile of the field plate 52F  has concaves which align the projections. Such the configuration is made based on the consideration of the on-state resistance and the direction of current flow at on-state.
FIG. 8 is a top view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1B, except that the  field plates  50 and 52 are replaced by the  field plates  50G and 52G. In the exemplary illustration of FIG. 8, the  field plates  50G and 52G viewed along a direction normal to the passivation layer 30 are connected to each other. Hollow areas are located between the  field plates  50G and 52G.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be  distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims (25)

  1. A nitride-based semiconductor device, comprising:
    a first nitride-based semiconductor layer;
    a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    a doped nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer;
    a passivation layer covering the third nitride-based semiconductor layer;
    a first dielectric layer disposed within the passivation layer and abutting against the passivation layer;
    a second dielectric layer disposed within the passivation layer and abutting against the passivation layer, wherein the first and second dielectric layers are separated from each other; and
    a first field plate laterally extending over the second nitride-based semiconductor layer and the first dielectric layer.
  2. The nitride-based semiconductor device of any one of the preceding claims, further comprising:
    a drain electrode disposed on the first nitride-based semiconductor layer, wherein the first and second dielectric layers are located between the doped nitride-based semiconductor layer and the drain electrode.
  3. The nitride-based semiconductor device of any one of the preceding claims, wherein the second dielectric layer is located between the first dielectric layer and the drain electrode.
  4. The nitride-based semiconductor device of any one of the preceding claims, wherein a distance between the doped nitride-based semiconductor layer to the first dielectric layer is less than a distance between the drain electrode and the second dielectric layer.
  5. The nitride-based semiconductor device of any one of the preceding claims, further comprising:
    a second field plate laterally extending over the second dielectric layer and spaced apart from the first field plate.
  6. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate and the second field plate are horizontally overlapped with each other.
  7. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate and the second field plate have different extending lengths.
  8. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate and the second field plate have the same thickness.
  9. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate and the second field plate viewed along a direction normal to the passivation layer have different edge profiles.
  10. The nitride-based semiconductor device of any one of the preceding claims, wherein a distance between the first field plate and the second field plate is less than a distance between the first dielectric layer and the second dielectric layer.
  11. The nitride-based semiconductor device of any one of the preceding claims, wherein the first and second dielectric layers have different dielectric constants.
  12. The nitride-based semiconductor device of any one of the preceding claims, wherein the first dielectric layer and the passivation have different dielectric constants.
  13. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate extends from the first dielectric layer to the passivation layer.
  14. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate further extends to cover the first and second dielectric layers.
  15. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate forms an interface with the first dielectric layer in a position lower than a top surface of the passivation layer.
  16. A method for manufacturing a nitride-based semiconductor device, comprising:
    forming a first nitride-based semiconductor layer;
    forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;
    forming a doped nitride-based semiconductor layer on the second nitride-based semiconductor layer;
    forming a passivation layer on the second nitride-based semiconductor layer to cover the third nitride-based semiconductor layer;
    removing a first portion and a second portion of the passivation layer to form two trenches;
    forming a first dielectric layer and a second dielectric layer to fill the trenches of the passivation layer; and
    forming a first field plate at least laterally extending over the first dielectric layer.
  17. The method of any one of the preceding claims, further comprising:
    forming a second field plate at least laterally extending over the second dielectric layer.
  18. The method of any one of the preceding claims, further comprising:
    patterning a blanket conductive layer to form the first field plate and the second field plate.
  19. The method of any one of the preceding claims, further comprising:
    forming a dielectric structure filling the trenches of the passivation layer; and covering the passivation layer; and
    thinning the dielectric structure such that the passivation layer is exposed.
  20. The method of any one of the preceding claims, wherein thinning the dielectric structure such that the first dielectric layer and the second dielectric layer have thickness less than the passivation layer.
  21. A nitride-based semiconductor device, comprising:
    a first nitride-based semiconductor layer;
    a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    a doped nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer;
    a passivation layer covering the third nitride-based semiconductor layer;
    a first field plate laterally extending over the second nitride-based semiconductor layer; and
    a first dielectric layer disposed between the second nitride-based semiconductor layer and the first field plate and in contact with the second nitride-based semiconductor layer.
  22. The nitride-based semiconductor device of any one of the preceding claims, wherein the first dielectric layer and the passivation layer have different dielectric constants.
  23. The nitride-based semiconductor device of any one of the preceding claims, wherein the first field plate is in contact with the first dielectric layer and the passivation layer.
  24. The nitride-based semiconductor device of any one of the preceding claims, further comprising:
    a second field plate laterally extending over the second nitride-based semiconductor layer; and
    a second dielectric layer disposed between the second nitride-based semiconductor layer and the second field plate and in contact with the second nitride-based semiconductor layer, wherein the first dielectric layer is located between the doped nitride-based semiconductor layer and the second dielectric layer.
  25. The nitride-based semiconductor device of any one of the preceding claims, wherein the second field plate is in contact with the second dielectric layer and the passivation layer.
PCT/CN2022/106785 2022-07-20 2022-07-20 Nitride-based semiconductor device and method for manufacturing the same WO2024016219A1 (en)

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CN101414625A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Groove gate type gate-leakage composite field plate transistor with high electron mobility
US20120274402A1 (en) * 2011-04-26 2012-11-01 Texas Instruments Incorporated High electron mobility transistor
US20140159116A1 (en) * 2012-12-07 2014-06-12 International Rectifier Corporation III-Nitride Device Having an Enhanced Field Plate
CN104393035A (en) * 2014-11-18 2015-03-04 西安电子科技大学 Heterojunction field effect transistor of composite source field plate based on medium modulation
CN104409493A (en) * 2014-11-18 2015-03-11 西安电子科技大学 Heterostructure device based on T-shaped gate-drain complex field plate and manufacturing method thereof
CN114144891A (en) * 2021-07-16 2022-03-04 英诺赛科(苏州)科技有限公司 Nitrogen-based semiconductor device and method for manufacturing the same

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CN101414625A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Groove gate type gate-leakage composite field plate transistor with high electron mobility
US20120274402A1 (en) * 2011-04-26 2012-11-01 Texas Instruments Incorporated High electron mobility transistor
US20140159116A1 (en) * 2012-12-07 2014-06-12 International Rectifier Corporation III-Nitride Device Having an Enhanced Field Plate
CN104393035A (en) * 2014-11-18 2015-03-04 西安电子科技大学 Heterojunction field effect transistor of composite source field plate based on medium modulation
CN104409493A (en) * 2014-11-18 2015-03-11 西安电子科技大学 Heterostructure device based on T-shaped gate-drain complex field plate and manufacturing method thereof
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