WO2024040600A1

WO2024040600A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2024040600A1
Application number: PCT/CN2022/115252
Authority: WO
Inventors: Po-Wei Chen
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2024-02-29
Also published as: CN118216004A

Abstract

A semiconductor device includes a first and a second nitride-based semiconductor layers, a drain, a source electrodes, a gate electrode, a plurality of field plates, a conductive layer, and at least one contact via. The field plates are disposed over the second nitride-based semiconductor layer and located between the gate and drain electrodes. The gate electrode is free from coverage of the field plates. The conductive layer is disposed over the field plates. The at least one contact via connect one of the field plates to the conductive layer, such that the one of the field plates and the contact via have substantially the same voltage level.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Po-Wei CHEN

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a contact via with a stripe-shaped profile.

Background othe Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a drain, a source electrodes, a gate electrode, a plurality of field plates, a conductive layer, and at least one contact via. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer. The drain and the source electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and located between the drain and the source electrodes. The field plates are disposed over the second nitride-based semiconductor layer and located between the gate and drain electrodes. The gate electrode is free from coverage of the field plates. The conductive layer is disposed over the field plates. The at least one contact via connect one of the field plates to the conductive layer, such that the one of the field plates and the contact via have substantially the same voltage level.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer. A source and a drain electrodes are formed over the second nitride-based semiconductor layer. A gate electrode is formed over the second nitride-based semiconductor layer and between the source and the drain electrodes. A plurality of field plates are formed over the second nitride-based semiconductor layer. The field plates are formed to be located between the gate electrode and the drain electrode. A dielectric layer is formed to cover the gate, source and drain electrodes. The field plates are embedded in the dielectric layer. At least one portion of the dielectric layer is removed, such that a top surface of at least one of the field plates is exposed. At least one contact via is formed to make contact with the exposed first field plate. A conductive layer is formed to make contact with the contact via, such that the conductive layer is electrically coupled to the first field plate through the contact via.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a drain and a source electrodes, a gate electrode, a plurality of field plates, a conductive layer, at least one connecting member, and a dielectric layer. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer. The drain and a source electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and located between the drain and source electrodes. The field plates are disposed over the second nitride-based semiconductor layer and located between the gate and drain electrodes. The conductive layer extends horizontally over the gate electrode and the field plates. The at least one connecting member extends along a vertical direction to make contact with one of the field plates and the conductive layer. The dielectric layer covers the gate, source and drain electrodes. A portion of the dielectric layer is located between each of the field plates and the gate electrode, such that each of the field plates is spaced apart from the gate electrode by the dielectric layer.

By the above configuration, in the present disclosure, a plurality of the field plates are located between the gate and drain electrodes. Each of the field plates is horizontally spaced apart from the gate electrode, and thus the gate electrode is free from coverage of the field plates. Therefore, parasitic/stray capacitances between the gate electrode and the field plate can be reduced. The field plates are configured to modulate an electric field distribution in the device. Thus, the nitride-based semiconductor device of the present disclosure can have a good reliability and be suitable for high frequency devices. Furthermore, the field plate can be electrically connected to a voltage source through the contact via/member. In some embodiments, the contact via/member extends along a direction to have a stripe-shaped profile; and therefore, the contact area between the contact via/member and the field plate can be enlarged by such a configuration, thereby improving uniformity of the voltage distribution of the field plate. Accordingly, the nitride-based semiconductor device of the present disclosure can achieve a desired electric field distribution.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is a vertical cross-section view of the semiconductor device in FIG. 1A;

FIG. 2A, FIG. 2B, and FIG. 2C show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

FIG. 3A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 3B is a vertical cross-section view of the semiconductor device in FIG. 3A;

FIG. 4A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4B is a vertical cross-section view of the semiconductor device in FIG. 4A;

FIG. 5 is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6B is a vertical cross-section view of the semiconductor device in FIG. 6A;

FIG. 7 is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 9 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 10 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 11 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 12 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 13 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 14 is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 15 is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 16A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 16B is a vertical cross-section of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 17 is a top view of a semiconductor device 1P according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a top view of a semiconductor device 1A according to some embodiments of the present disclosure. FIG. 1B is a vertical cross-section view of the semiconductor device 1A in FIG. 1A. Referring to FIGS. 1A and 1B, the semiconductor device 1A can be located in a space defined by directions D1, D2, and D3. The direction D1 (e.g., a width direction) is perpendicular to the direction D2, the direction D2 (e.g., a vertical/thickness direction) is perpendicular to the direction D3, and the direction D3 (e.g., a length direction) is perpendicular to the direction D1. The semiconductor device 1A can include a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, a gate structure GS,

electrodes

22, 24,

field plates

32, 34, 36, a contact via/member 40A (i.e., conductive via) , a conductive layer 38, and a dielectric layer 42.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer 12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer 12. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 16 can be disposed on/over/above the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

22 and 24 can be disposed on/over/above the nitride-based semiconductor layer 16. The

electrodes

22 and 24 can make contact with the nitride-based semiconductor layer 16. In some embodiments, the electrode 22 can serve as a source electrode. In some embodiments, the electrode 22 can serve as a drain electrode. In some embodiments, the electrode 24 can serve as a source electrode. In some embodiments, the electrode 24 can serve as a drain electrode. The role of the

electrodes

22 and 24 depends on the device design.

In some embodiments, the

electrodes

22 and 24 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

22 and 24 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

22 and 24 may be a single layer, or plural layers of the same or different composition. The

electrodes

22 and 24 form ohmic contacts with the nitride-based semiconductor layer 16. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

22 and 24. In some embodiments, each of the

electrodes

22 and 24 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The gate structure GS is disposed on/over/above the nitride-based semiconductor layer 16. The gate structure GS includes a doped nitride-based semiconductor layer 18 and a gate electrode 20. The doped nitride-based semiconductor layer 18 is disposed on/over/above the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 18 makes contact with the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 18 is disposed between the nitride-based semiconductor layer 16 and the gate electrode 20. The gate electrode 20 is disposed on/over/above the doped nitride-based semiconductor layer 18 and nitride-based semiconductor layer 16. The gate electrode 20 makes contact with the doped nitride-based semiconductor layer 18. The gate electrode 20 is located between the

electrodes

22, 24.

A width of the doped nitride-based semiconductor layer 18 is greater than that of the gate electrode 20. In some embodiments, a width of the doped nitride-based semiconductor layer 18 is substantially the same as a width of the gate electrode 20. The profiles of the doped nitride-based semiconductor layer 18 and the gate electrode 20 are the same, for example, both of them are rectangular profiles. In other embodiments, the profiles of the doped nitride-based semiconductor layer 18 and the gate electrode 20 can be different from each other, for example, the profile of the doped nitride-based semiconductor layer 18 can be a trapezoid profile, while the profile of the gate electrode 20 can be a rectangular profile.

In the exemplary illustration of FIG. 1A, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 20 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 18 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 20 has different characteristics (e.g., different electron concentrations) than the remaining portion of the 2DEG region and thus is blocked.

Due to such mechanism, the semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 20 or a voltage applied to the gate electrode 20 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 20) , the zone of the 2DEG region below the gate electrode 20 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 18 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 18 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 18 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 14 includes undoped GaN and the nitride-based semiconductor layer 16 includes AlGaN, and the doped nitride-based semiconductor layer 18 is a p-type doped GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 20 may include metals or metal compounds. The gate electrode 20 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

In order to avoid breakdown phenomenon induced by a strong peak electrical field in the device, field plates are adopted to modulate electric field distribution therein. The configuration of the field plates may induce unwanted parasitic/stray capacitances which limits the maximum operating frequency of the device, thereby degrading the electrical properties and the reliability thereof.

Furthermore, to realize an ideal electric field distribution in the device, voltage level distribution of the field plate is an important factor to determine a desired electric field distribution in the device. Under ideal conditions, a voltage source can be electrically connected to the field plate, such that the field plate can have substantially the same voltage level as the voltage source. However, due to the relationship between the geometry and area of the field plate, the voltage distribution of the field plate is not uniform, and thus the electric field distribution in the device deviates from a desired electric field distribution, resulting in a poor device performance. Therefore, there is a need to improve device performance.

At least to solve the aforesaid issues, the present disclosure provides a novel structure.

The

field plates

32, 34, and 36 are disposed on/over/above the nitride-based semiconductor layer 16. The

field plates

32, 34, and 36 are located between the gate electrode 20 and the electrode 24. The

field plates

32, 34, 36 are configured to modulate an electric field distribution of a region between the gate electrode 20 and the electrode 24.

The

field plates

32, 34, and 36 are located at different heights, respectively. The field plate 32 is the closest field plate to the gate electrode 20 and is the lowest field plate in the

field plates

32, 34, and 36. The field plate 34 is the second closest field plate to the gate electrode 20 and is the second lowest field plate in the

field plates

32, 34, and 36. The field plate 36 is the farthest field plate to the gate electrode 20 and is the highest field plate in the

field plates

32, 34, and 36. The field plate 34 extends to a top of the field plate 32 to vertically overlap with a portion of the field plate 32, such that an edge of the field plate 32 is covered by the field plate 34. The field plate 36 extends to a top of the field plate 34 to vertically overlap with a portion of the field plate 34, such that an edge of the field plate 34 is covered by the field plate 36. The aforesaid configuration of the

field plates

32, 34, and 36 can well modulate the electric field distribution in the semiconductor device 1A.

Each of the

field plates

32, 34, and 36 is horizontally spaced apart from the gate electrode 20, so the gate electrode 20 is free from coverage of each of the

field plates

32, 34, and 36, thereby alleviating parasitic/stray capacitances between the gate electrode 20 and the field plate 32/34/36. Thus, the semiconductor device 1A can be suitable for high frequency device and have a good device performance.

The exemplary materials of the

field plates

32, 34, and 36 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.

The conductive layer 38 is disposed on/over/above the

field plates

32, 34, and 36 and the gate structure GS. The conductive layer 38 horizontally extends over the

field plates

32, 34, 36, and the gate electrode 20. In the embodiment, the conductive layer 38 extends from a position P1 between the electrode 22 and the gate electrode 20 to a position P2 between the gate electrode 20 and the electrode 24, such that the conductive layer 38 span across the gate electrode 20. The

field plates

32, 34, and 36 are directly located under the conductive layer 38.

The contact via 40A is disposed on/over/above the field plate 34. The contact via 40A extends vertically along the direction D2 (i.e., the vertical direction) , such that two ends of the contact via 40A make contact with one of the field plates 32/34/36, and the conductive layer 38, respectively. In the embodiment, the contact via 40A extends vertically, such that two ends of the contact via 40A make contact with the field plate 34 and the conductive layer 38. The contact via 40A extends downward in a vertical manner. Since the contact via 40A connects the field plate 34 and the conductive layer 38, the contact via 40A can serve as a connecting member.

Referring to FIG. 1A, the contact via 40A extends along the direction D3, such that the contact via 40A has a stripe-shaped profile in a top view of the semiconductor device 1A. The extending length of the contact via 40A along the direction D3 can be substantially the same as that of field plate 34. By such a configuration, a contact area between the contact via 40A and the field plate 34 can be increased, and thus the contact resistance between the contact via 40A and the field plate 34 can be reduced. Therefore, the conductive via 40A connects the field plate 34 to the conductive layer 38, such that the field plate 34 and the conductive layer 38 can have substantially the same voltage level. Accordingly, the voltage distribution of the field plate 34 can be more uniform; and therefore, the electric field distribution of the semiconductor device 1A is less likely to deviate from a desired electric field distribution. Hence, the semiconductor device 1A of the present disclosure can have a good device performance.

In addition, in one aspect, the contact via 40A can act as a part of field plate extending along the vertical direction D2, the contact via 40A with a striped-shaped profile can further alleviate the effect of high drain voltage to the gate electrode 20.

In some embodiments, the conductive layer 38 can be electrically coupled/connected to a ground voltage level, and thus voltage levels of the conductive layer 38 and the field plate 34 can be ground voltage levels. In other embodiments, the conductive layer 38 can be electrically coupled/connected to other suitable voltage level, and the present disclosure is not limited thereto.

Referring back to FIG. 1A again, each of the gate electrode 20,

electrodes

22, 24 extends along the direction D3, such that each of the gate electrode 20,

electrodes

22, 24 has a stripe-shaped profile in a top view of the semiconductor device 1A. That is to say, the contact via 40A, the gate electrode 20, the

electrodes

22, 24 are substantially parallel to each other.

The dielectric layer 42 is disposed on/over/above the gate electrode 20, the

electrodes

22, 24, and the nitride-based semiconductor layer 16. The dielectric layer 42 covers the gate electrode 20, the

electrodes

22, 24, and the nitride-based semiconductor layer 16, so as to protect these elements. The dielectric layer 42 can be referred as a protection layer. The

field plates

32, 34, and 36 are embedded in the dielectric layer 42. Each of the

field plates

32, 34, and 36 is spaced apart from the gate electrode 20 by at least a portion of the dielectric layer 42. The contact via 40A is disposed within the dielectric layer 42.

The material of the dielectric layer 42 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 42 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 42 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

Moreover, the dielectric layer 42 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the dielectric layer 42 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the dielectric layer 42 to remove the excess portions, thereby forming a level top surface.

Furthermore, a thickness of the dielectric layer 42 and a magnitude of a drain voltage of the semiconductor device 1A are factors to determine the conductive layer 38 to be a field plate or not. In some cases, the thickness of the dielectric layer 42 is small enough, and/or the magnitude of the drain voltage of the semiconductor device 1A is high enough, such that the conductive layer 38 can obviously affect an electric field distribution of the semiconductor device 1A. In this case, the conductive layer 38 covers the gate electrode 20, such that peak of the electric field near the gate edge can be split into more peaks so as to achieve a more uniform electric field distribution. That is to say, the conductive layer 38 can serve as the farthest field plates in the semiconductor device 1A in some cases. Although the aforesaid configuration may generate a parasitic/stray capacitance between the gate electrode 20 and the conductive layer 38, the conductive layer 38 is designed to be located a position higher than

other field plates

32, 34, and 36, thereby minimizing the negative impact of the parasitic/stray capacitance between the gate electrode 20 and the conductive layer 38.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, and FIG. 2C, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10. A nitride-based semiconductor layer 14 is formed on/over/above the substrate 10 and the buffer layer 12. A nitride-based semiconductor layer 16 is formed on/over/above the nitride-based semiconductor layer 14.

Electrodes

22, 24 are formed on/over/above the nitride-based semiconductor layer 16. A doped nitride-based semiconductor layer 18 is formed on/over/above the nitride-based semiconductor layer 16, in which the doped nitride-based semiconductor layer 18 is located between the

electrodes

22, 24. A gate electrode 20 is formed on/over/above the doped nitride-based semiconductor layer 18 and nitride-based semiconductor layer 16. A plurality of

field plates

30, 32, and 34 are formed on/over/above the nitride-based semiconductor layer 16. The

field plates

30, 32, and 34 are formed to be located between the gate electrode 20 and the electrode 24.

Then, a blanket dielectric layer is formed to cover the gate electrode 20, and the

electrodes

22, 24, in which the

field plates

30, 32, 34 are embedded in the dielectric layer 42. A mask layer ML is provided to cover a top surface of the blanket dielectric layer, such that at least a part of the top surface of the blanket dielectric layer is exposed. An etching process is performed on the blanket dielectric layer, such that at least one portion of the blanket dielectric layer is removed and a trench T is formed, thereby exposing a top surface of at least one of the field plates, for example, the field plate 34. The shape and the location of the trench T also define the shape and the location of a contact via 40A, in which the trench T can be a stripe-shaped trench.

Referring to FIG. 2B, a contact via 40A is formed to fill up the trench T, so as to make contact with the exposed field plate 34.

Referring to FIG. 2C, a conductive layer 38 is formed to make contact with the contact via 40A, such that the conductive layer 38 is electrically coupled to the one of the field plates (e.g., the field plate 34) through the contact via 40A. The conductive layer 38 covers the

field plates

32,34, and 36 between the gate electrode 20 and the electrode 24. Therefore, the semiconductor device 1A in the FIG. 1A can be obtained.

FIG. 3A is a top view of a semiconductor device 1B according to some embodiments of the present disclosure. FIG. 3B is a vertical cross-section view of the semiconductor device 1B in FIG. 3A. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40B is located between the closest field plate 32 to the gate electrode 20 and the conductive layer 38. The contact via 40B extends vertically, such that two ends of the contact via 40B make contact with the t field plate 32 and the conductive layer. Therefore, the field plate 32 and the conductive layer 38 can have substantially the same voltage level.

FIG. 4A is a top view of a semiconductor device 1C according to some embodiments of the present disclosure. FIG. 4B is a vertical cross-section view of the semiconductor device 1C in FIG. 4A. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40C is located between the farthest field plate 32 to the gate electrode 20 and the conductive layer 38, such that the field plate 36 and the conductive layer 38 can have substantially the same voltage level. As such, the negative impact of a parasitic/stray capacitance between the contact via 40C and the gate electrode 20 can be further alleviated.

In the present disclosure, by simply adjusting the location of the contact via, the semiconductor devices can achieve different electric field distributions to meet different device requirements.

FIG. 5 is a top view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40D includes a plurality of separated portions. The portions of the contact via 40D are separated from each other by the dielectric layer 42. The portions of the contact via 40D are densely arranged along a direction D3, such that the contact area between the contact via 40B and the field plate 34 still can maintain at a high level. The portions of the contact via 40D are arranged at equal intervals along the direction D3.

FIG. 6A is a top view of a semiconductor device 1E according to some embodiments of the present disclosure. FIG. 6B is a vertical cross-section view of the semiconductor device 1E in FIG. 6A. The semiconductor device 6C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the semiconductor device 1E includes at least two different types of the contact vias 40E1, 40E2. The contact via 40E1 can have a stripe-shaped profile in a top view of the semiconductor device 1E, and the contact via 40E1 connects the conductive layer 38 to the field plate 34. The contact via 40E2 includes a plurality of separated portions arranged along the direction D3, and the contact via 40E2 connects the conductive layer 38 to the field plate 36. As such, the

field plates

34, 36 and the conductive layer 38 can have the substantially same voltage level.

FIG. 7 is a top view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the semiconductor device 1E as described and illustrated with reference to FIGS. 6A and 6B, except that the semiconductor device 1F includes at least two contact vias 40F1, 40F2. The types of the contact vias 40F1, 40F2 are the same, for example, both of them have a stripe-shaped profile in a top view of the semiconductor device 1F.

FIG. 8 is a top view of a semiconductor device 1G according to some embodiments of the present disclosure. The semiconductor device 1G is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the semiconductor device 1G further includes a connection structure CS. The connection structure CS connects every one of the

field plates

32, 34, 36 and the conductive layer 38 to a ground voltage level.

FIG. 9 is a vertical cross-section view of a semiconductor device 1H according to some embodiments of the present disclosure. The semiconductor device 1H is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40H extends downward in an inclined manner.

FIG. 10 is a vertical cross-section view of a semiconductor device 1I according to some embodiments of the present disclosure. The semiconductor device 1I is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that a width of the contact via 40I is greater than that of the gate electrode 20.

FIG. 11 is a vertical cross-section view of a semiconductor device 1J according to some embodiments of the present disclosure. The semiconductor device 1J is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that a width of the contact via 40J decreases along an anti-direction of the direction D2. The contact via 40J can have an inverted trapezoid profile in a vertical cross-section view of the semiconductor device 1J.

FIG. 12 is a vertical cross-section view of a semiconductor device 1K according to some embodiments of the present disclosure. The semiconductor device 1K is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40K can have a funnel profile in a vertical cross-section view of the semiconductor device 1K.

With respect to the

semiconductor devices

1J and 1K, since the trench of the dielectric layer 42 has a top surface area greater than that of a bottom surface area, the contact via 40J/40K can be easily fill up with the trench during its the manufacturing process.

FIG. 13 is a vertical cross-section view of a semiconductor device 1L according to some embodiments of the present disclosure. The semiconductor device 1I is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the conductive layer 38L extends between the gate electrode 20 and the electrode 24. The gate electrode 20 is free from coverage of the conductive layer 38L. As such, the negative impact of a parasitic/stray capacitance between the conductive layer 38L and the gate electrode 20 can be further alleviated.

FIG. 14 is a top view of a semiconductor device 1M according to some embodiments of the present disclosure. The semiconductor device 1M is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 14M has at least one inclined surface in the top view of the semiconductor device 1M. Specifically, the contact via 14M has a parallelogram profile in the top view of the semiconductor device 1M. In some embodiments, the contact via 14M has a trapezoid profile in the top view of the semiconductor device. In some embodiments, the contact via can have at least one curved surface in the top view of the semiconductor device. The aforesaid configuration can meet different device requirements.

FIG. 15 is a top view of a semiconductor device 1N according to some embodiments of the present disclosure. The semiconductor device 1N is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the semiconductor device 1N further includes a plurality of contact vias CV, in which each of the contact vias CV can have a circle-shaped profile in a top view thereof. The conductive layer 38 can be electrically connected to the field plate 32 through one of the contact vias CV. The conductive layer 38 can be electrically connected to the field plate 36 through another one of the contact vias CV.

In some embodiments, the conductive layer 38 can be electrically connected to the field plate 32 through a plurality of the contact vias CV. Similarly, the conductive layer 38 can be electrically connected to the field plate 36 through a plurality of the contact vias CV. The present disclosure is not limited thereto.

FIG. 16A is a top view of a semiconductor device 1O according to some embodiments of the present disclosure. FIG. 16B is a vertical cross-section view of a semiconductor device 1O according to some embodiments of the present disclosure. The semiconductor device 1O is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the semiconductor device 1O includes at least three contact vias 40O1, 40O2, 40O3. The types of the contact vias 40O1, 40O2 and 40O3 are the same, for example, all of them have a stripe-shaped profile in a top view of the semiconductor device 1O. The conductive layer 38 can be electrically connected to the

field plates

32, 34, 36 through the contact vias 40O3, 40O1, 40O2, respectively.

FIG. 17 is a top view of a semiconductor device 1P according to some embodiments of the present disclosure. The semiconductor device 1P is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the contact via 40P has different portions with different widths in the direction D1, and the contact area between the contact via 40P and the field plate can be further increased.

The different embodiments show the device structure can get flexible so can comply with more requirements. The flexibility of the device can be achieved by making the gate electrode free from vertically coverage of the field plates.

Based on above, in the present disclosure, prior the step of forming a conductive layer on the field plates, an etching process is performed on the dielectric layer to form a trench to accommodate the contact via, so as to achieve a high contact area between the contact via and the field plate. The voltage distribution of the field plate can be more uniform, and thus the device can have a desirable electric field distribution.

In addition, the field plates are located between the gate electrode and the drain electrode instead of being on a top of the gate electrode. Hence, the parasitic/stray capacitance between the gate electrode and the field plate can be reduced. The semiconductor device of the present disclosure can be suitable for high frequency applications.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer;

a drain and a source electrodes disposed over the second nitride-based semiconductor layer;

a gate electrode disposed over the second nitride-based semiconductor layer and located between the drain and the source electrodes;

a plurality of field plates disposed over the second nitride-based semiconductor layer and located between the gate and drain electrodes, wherein the gate electrode is free from coverage of the field plates;

a conductive layer disposed over the field plates; and

at least one contact via connecting one of the field plates to the conductive layer, such that the one of the field plates and the conductive layer have substantially the same voltage level.
The semiconductor device of claim 1, wherein the contact via extends along a first direction, such that the contact via has a stripe-shaped profile in a top view of the semiconductor device.
The semiconductor device of claim 1, wherein each of the gate, drain, and source electrodes extends along a first direction, such that each of the gate, drain, and source electrodes has a stripe-shaped profile in a top view of the semiconductor device.
The semiconductor device of claim 1, wherein the contact via comprises a plurality of separated portions, and the separated portions are arranged along a first direction.
The semiconductor device of claim 4, wherein the separated portions are arranged at equal intervals along the first direction.
The semiconductor device of claim 1, wherein the contact via extends downward to make contact with the one of the field plates.
The semiconductor device of claim 6, wherein the contact via extends downward in a vertical manner.
The semiconductor device of claim 6, wherein the contact via extends downward in an inclined manner.
The semiconductor device of claim 1, wherein a width of the contact via is greater than that of the gate electrode.
The semiconductor device of claim 1, wherein the conductive layer horizontally extends over the field plates.
The semiconductor device of claim 1, wherein each of the field plates is horizontally spaced apart from the gate electrode.
The semiconductor device of claim 1, wherein the field plates are directly located under the conductive layer.
The semiconductor device of claim 1, wherein the field plates are located at different heights, respectively.
The semiconductor device of claim 1, wherein the one of the field plates and the conductive layer are electrically coupled to a ground voltage level.
The semiconductor device of claim 1, further comprising a dielectric layer covering the gate, drain and the source electrodes, wherein the field plates are embedded in the dielectric layer.
A manufacturing method of a semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer;

forming a source and a drain electrodes over the second nitride-based semiconductor layer;

forming a gate electrode over the second nitride-based semiconductor layer and between the source and the drain electrodes;

forming a plurality of field plates over the second nitride-based semiconductor layer, wherein the field plates are formed to be located between the gate electrode and the drain electrode;

forming a dielectric layer to cover the gate, source and drain electrodes, wherein the field plates are embedded in the dielectric layer;

removing at least one portion of the dielectric layer, such that a top surface of at least one of the field plates is exposed; and

forming at least one contact via to make contact with the exposed field plate; and

forming a conductive layer to make contact with the contact via, such that the conductive layer is electrically coupled to the one of the field plates through the contact via.
The method of claim 16, wherein the step of removing the at least one portion of the dielectric layer further comprises:

performing an etching process to form at least one trench in the dielectric layer to define location of the contact via.
The method of claim 17, wherein the trench is a stripe-shaped trench.
The method of claim 17, wherein the contact via 40A is formed to fill up the trench.
The method of claim 16, wherein the field plates are formed to be located directly under the conductive layer.
A semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer;

a drain and a source electrodes disposed over the second nitride-based semiconductor layer;

a gate electrode disposed over the second nitride-based semiconductor layer and located between the drain and source electrodes;

a plurality of field plates disposed over the second nitride-based semiconductor layer and located between the gate and drain electrodes;

a conductive layer extending horizontally over the gate electrode and the field plates;

at least one connecting member extending along a vertical direction to make contact with one of the field plates and the conductive layer; and

a dielectric layer covering the gate, source and drain electrodes, wherein a portion of the dielectric layer is located between each of the field plates and the gate electrode, such that each of the field plates is spaced apart from the gate electrode by the dielectric layer.
The semiconductor device of claim 21, wherein the field plates are embedded in the dielectric layer.
The semiconductor device of claim 21, wherein the at least one connecting member comprises a first and a second connecting member, wherein the first connecting member connects the conductive layer to one of the field plates, the second connecting member connects the conductive layer to another one of the field plates.
The semiconductor device of claim 21, further comprises a connection structure, wherein the connection structure connects every one of the field plates and the conductive layer to ground.
The semiconductor device of claim 21, wherein a width of the connecting member decreases along an anti-direction of the vertical direction.