WO2024108491A1

WO2024108491A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024108491A1
Application number: PCT/CN2022/134085
Authority: WO
Inventors: Huixin He; Kai Hu; Zhongyu ZHANG; King Yuen Wong
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2024-05-30

Abstract

A nitride-based semiconductor device (1A-1D) includes a first nitride-based semiconductor layer (12), a second nitride-based semiconductor layer (14), a first electrode (30) and a second electrode (32), a gate electrode (40) and a gate field plate (42). The second nitride-based semiconductor layer (14) is disposed on the first nitride-based semiconductor layer (12). The second nitride-based semiconductor layer (14) has a first portion (142) and a second portion (144) connected to the first portion (142) and thicker than the first portion (142). The first electrode (30) and a second electrode (32) are disposed over the first portion (142) and the second portion (144) of the second nitride-based semiconductor layer (14), respectively. The gate electrode (40) is disposed over the first portion (142) of the second nitride-based semiconductor layer (14) and between the first and second electrodes (30,32). The gate field plate (42) is disposed over the first portion (142) of the second nitride-based semiconductor layer (14) and between the gate electrode (40) and the second electrode (32).

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Huixin HE; Kai HU; Zhongyu ZHANG; King Yuen WONG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a D-mode nitride-based semiconductor device having an extended distance between a barrier layer and a field plate.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, and a gate field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion. The first electrode and a second electrode are disposed over the first portion and the second portion of the second nitride-based semiconductor layer, respectively. The gate electrode is disposed over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes. The gate field plate is disposed over the first portion of the second nitride-based semiconductor layer and between the gate electrode and the second electrode.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has steps as follows: forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; thinning the second nitride-based semiconductor layer such that the second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion; forming a first dielectric layer over the second nitride-based semiconductor layer; forming a first electrode and a second electrode over the first portion and the second portion of the second nitride-based semiconductor layer, respectively; forming a gate electrode over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes; and forming a gate field plate over the first portion of the second nitride-based semiconductor layer and between the gate electrode and the second electrode.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, and a dielectric layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion. The first electrode and a second electrode are disposed over the first portion and the second portion of the second nitride-based semiconductor layer, respectively. The gate electrode is disposed over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes. The dielectric layer covers the second nitride-based semiconductor layer and is penetrated by the first electrode and the second electrode.

By the above configuration, the nitride-based semiconductor device 1A can have flexible room for operation in different voltage ranges such that low risk for the lateral breakdown is achieved.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based

semiconductor layers

12, 14, a dielectric layer 16,

passivation layers

18 and 20,

electrodes

30 and 32, a doped nitride-based semiconductor layer 30, a gate electrode 40, and a field plate 42.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a buffer layer (not shown) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y)N where x+y ≤ 1, Al _xGa _(1–x)N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The nitride-based semiconductor layer 14 has

portions

142 and 144 which are connected to each other. The portion 144 is thicker than the portion 142. The thickness difference between the

portions

142 and 144 can form a stepwise profile for the nitride-based semiconductor layer 14. The concentration of the 2DEG region may related to the thickness of the nitride-based semiconductor layer 14. Due to the portion 144 thicker than the portion 142, the 2DEG region may have a light concentration directly beneath the portion 142 and a heavy concentration directly beneath the portion 144.

The dielectric layer 16 is disposed over the nitride-based semiconductor layer 14. The dielectric layer 16 covers the nitride-based semiconductor layer 14. The dielectric layer 16 has

portions

162 and 164 covering the

portions

142 and 144 of the second nitride-based semiconductor layer 14, respectively, so as to become stepwise shaped. The thickness difference between the

portions

142 and 144 of the second nitride-based semiconductor layer 144 is less than the thickness difference between the

portions

162 and 164 of dielectric layer 16. Such the configuration is advantageous to modulate the dielectric constant distribution over the nitride-based semiconductor layer 14, the nitride-based semiconductor layer 14 has the different thicknesses. The material of the dielectric layer 16 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 16 can include SiN _x, SiO _x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.

The passivation layer 18 is disposed over the dielectric layer 16. The passivation layer 18 covers the dielectric layer 16. The material of the passivation layer 18 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 18 can include SiNx, SiO _x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 16 and the passivation layer 18 have different materials. In some embodiments, the dielectric layer 16 is a nitride-based layer and the passivation layer 18 is an oxide-based layer.

The

electrodes

30 and 32 are disposed over the nitride-based semiconductor layer 14. The

electrodes

30 and 32 are disposed over the dielectric layer 16 and the passivation layer 18. The electrode 30 is disposed over the portion 142 of the nitride-based semiconductor layer 14 and the portion 162 of the nitride-based semiconductor layer 16. The electrode 30 can penetrate the dielectric layer 16 and the passivation layer 18 so as to make contact with the nitride-based semiconductor layer 14. The electrode 32 is disposed over the portion 144 of the nitride-based semiconductor layer 14 and the portion 164 of the nitride-based semiconductor layer 16. The electrode 32 can penetrate the dielectric layer 16 and the passivation layer 18 so as to make contact with the nitride-based semiconductor layer 14. Each of the

electrodes

30 and 32 can serve as a source electrode or a drain electrode.

In some embodiments, the

electrodes

30 and 32 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

30 and 32 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

30 and 32 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

30 and 32 form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

30 and 32.

In some embodiments, each of the

electrodes

30 and 32 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layer 20 is disposed on the passivation layer 18. The passivation layer 20 covers the

electrodes

30 and 32. The material of the passivation layer 20 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 20 can include SiNx, SiOx, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 16 and the passivation layer 18 have different materials.

The gate electrode 40 is disposed over the nitride-based semiconductor layer 14. The gate electrode 40 is disposed over the dielectric layer 16. The gate electrode 40 is disposed over the portion 142 of the nitride-based semiconductor layer 14 and the portion 162 of the nitride-based semiconductor layer 16. The gate electrode 40 is located between the

electrodes

30 and 32. The electrode 30 can penetrate the passivation layers 18 and 20so as to make contact with the dielectric layer 16. The exemplary materials of the gate electrode 40 may include metals or metal compounds. The gate electrode 40 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The

electrodes

30 and 32 and the gate electrode 40 can collectively constitute a nitride-based transistor using the 2DEG region. More specifically, the dielectric layer 16 can serve as a gate dielectric/isolation layer between the nitride-based semiconductor layer 14 and the gate electrode 40, such that the nitride-based semiconductor device 1A is a depletion-mode high electron mobility transistor (D-Mode HEMT) .

The gate field plate 42 is disposed over the portion 142 of the nitride-based semiconductor layer 14 and the portion 162 of the nitride-based semiconductor layer 16. The gate field plate 42 is disposed on the passivation layers 18 and 20. The gate field plate 42 is located between the gate electrode 42 and the electrode 32. The gate field plate 42 is configurated to modulate the electric field distribution of a region between the gate electrode 42 and the electrode 32, so as to provide longitudinal withstand voltage at the region.

Regarding lateral withstand voltage the nitride-based semiconductor layer 14 having different thickness can have lateral withstand voltage increased. Once a barrier layer has a uniform thin thickness, the resistance of the 2DEG region may increase. Once a barrier layer has a uniform thick thickness, cost to switch off D-mode devices may increase (e.g., need more power to deplete the 2DEG) , which results in lateral breakdown. The nitride-based semiconductor device 1A can have flexible room for operation in different voltage ranges such that low risk for the lateral breakdown is achieved. Therefore, the nitride-based semiconductor layer 14 having different thickness can overcome the defects as above. With such the configuration, the gate field plate 42 is confined in a region corresponding to the portion 142 of the nitride-based semiconductor layer 14, so as to avoid longitudinal breakdown.

Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a nitride-based semiconductor layer 12 is formed over a substrate 10. A nitride-based semiconductor layer 14 is formed over the nitride-based semiconductor layer 12. A dielectric layer 50 is formed on the nitride-based semiconductor layer 14. The dielectric layer 50 covers the nitride-based semiconductor layer 14.

Referring to FIG. 2B, a mask layer 52 is formed over on the dielectric layer 50. The mask layer 52 covers the dielectric layer 50. At least one portion of the dielectric layer 50 is exposed from the mask layer 52.

Referring to FIG. 2C, the exposed portion of the dielectric layer 50 is removed. In some embodiments, the removal of the exposed portion of the dielectric layer 50 is achieved by performing an etching process using the mask layer 52. After the removal of the exposed portion of the dielectric layer 50, at least one portion of the nitride-based semiconductor layer 14 is exposed. Thereafter, the exposed portion of the nitride-based semiconductor layer 14 is thinned such that the nitride-based semiconductor layer 14 can have a portion 142 and a portion 144 thicker than the portion 142.

Referring to FIG. 2D, a dielectric layer 54 is formed over the nitride-based semiconductor layer 14. The dielectric layer 54 can cover the portion 142 of the nitride-based semiconductor layer 14 and the dielectric layer 50. The dielectric layer 50 and the dielectric layer 54 can get merged such that a dielectric layer 16 is formed. Forming the dielectric layer 50 prior to the formation mask layer 52 is to protect the nitride-based semiconductor layer 14 from damaged in the processes. Since the portion 144 of the nitride-based semiconductor layer 14 is to be connected to a drain electrode, defects in the portion 144 of the nitride-based semiconductor layer 14 will result in leakage current as the drain electrode is biased with high voltage.

Referring to FIG. 2E, a passivation layer 18 is formed on the dielectric layer 16. Referring to FIG. 2F, electrodes passivation layer 18 is formed on the dielectric layer 16.

Electrodes

30 and 32 are formed over the

portion

142 and 144 of the nitride-based semiconductor layer 14, respectively. Thereafter, a passivation layer 20 is formed to cover the

electrodes

30 and 32. After the formation of the passivation layer 20, a gate electrode and a gate field plate as afore described are formed.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the gate field plate 42 is replaced by a gate field plate 42B.

The gate field plate 42B is disposed over the passivation layer 20. The gate field plate 42B is disposed over the portion 142 of the nitride-based semiconductor layer 14. The gate field plate 42B has an edge (e.g., the right sidewall of the gate field plate 42B) can vertically coincide with an interface between the

portions

142 and 144 of the nitride-based semiconductor layer 14.

The gate field plate 42B is confined in the region corresponding to the portion 142 of the nitride-based semiconductor layer 14 as well because the heavy concentration corresponding to the portion 144 of the nitride-based semiconductor layer 14 may create unwanted parasitic capacitance. The electric filed distribution may vary greatly at the interface as such so the gate field plate 42B is formed to modulate the distribution there.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the

electrodes

30 and 32 are replaced by

electrodes

30C and 32C.

The

electrodes

30C and 32C can extend to different depths within a thickness range of the nitride-based semiconductor layer 14C. More specifically, the electrode 30C can penetrate the nitride-based semiconductor layer 14C, and the electrode 32C extend can to a position within the thickness range of the nitride-based semiconductor layer 14C. Such the configuration can meet the different requirements for device design. For example, the resistance between the electrode 30C and 2DEG region is different than the resistance between the electrode 32C and 2DEG region, so it can create further room for the operation flexible. The structure can be achieved by using etching selectivity because the dielectric layer 16 has the portions with different thicknesses.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 14, the dielectric layer 16, the

electrodes

30 and 32, and the gate electrode 40 are replaced by a nitride-based semiconductor layer 14D, a dielectric layer 16D, the

electrodes

30D and 32D, and the gate electrode 40D.

The nitride-based semiconductor layer 14D has

portions

142D and 144D. The portion 142D of the nitride-based semiconductor layer 14D has a varying thickness. The thickness of the portion 142D decreases toward a direction away from the portion 144D. As such, the portion 142D of the nitride-based semiconductor layer 14D has an oblique top surface. The profile of the portion 142D of the nitride-based semiconductor layer 14D can be achieved by using a gray-tone mask during an etching stage. The dielectric layer 16D can have an oblique top surface corresponding to the nitride-based semiconductor layer 14D.

During the formation of the

electrodes

30D and 32D, recesses can be formed in the nitride-based semiconductor layer 14D and then are filled with the

electrodes

30D and 32D. The profile of the nitride-based semiconductor layer 14D may related to the shape of the

electrodes

30D and 32D. Accordingly, the electrode 30D has a bottom surface oblique with respect to the nitride-based semiconductor layer 14D. The electrode 32D has a bottom surface flat with respect to the bottom surface of the electrode 30D. The oblique surface of the electrode 30D may increase contact interface with the nitride-based semiconductor layer 14D, thereby decreasing resistance therebetween. Similarly, the gate electrode 40D has a bottom surface oblique with respect to the nitride-based semiconductor layer 14D. The oblique surface of the gate electrode 40D can be tuned to decrease potential parasitic capacitance.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated. Furthermore, the term “connection” in the present disclosure may include “indirect connection” , “direct connection” , or combinations thereof.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion;

a first electrode and a second electrode disposed over the first portion and the second portion of the second nitride-based semiconductor layer, respectively;

a gate electrode disposed over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes; and

a gate field plate disposed over the first portion of the second nitride-based semiconductor layer and between the gate electrode and the second electrode.
The nitride-based semiconductor device according of any one of the preceding claims, further comprising a dielectric layer covering the second nitride-based semiconductor layer and penetrated by the first electrode and the second electrode.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the dielectric layer has a first portion and a second portion which cover the first portion and the second portion of the second nitride-based semiconductor layer, respectively so as to become stepwise shaped.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the second portion of the dielectric layer is thicker than the first portion of the dielectric layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the first electrode and the second electrode extend to different depths within a thickness range of the second nitride-based semiconductor layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the gate field plate has an edge vertically coinciding with an interface between the first portion and the second portion of the second nitride-based semiconductor layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the first electrode penetrates the second nitride-based semiconductor layer, and the second electrode extends to a position within a thickness range of the second nitride-based semiconductor layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the first portion has a varying thickness.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the thickness of the first portion decreases toward a direction away from the second portion.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the gate electrode has a bottom surface oblique with respect to the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first electrode has a bottom surface oblique with respect to the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second electrode further has a bottom surface flat with respect to the bottom surface of the first electrode.
The nitride-based semiconductor device of any one of the preceding claims, further comprising a passivation layer covering the dielectric layer and comprising a material that is different than that of the dielectric layer.
The nitride-based semiconductor device of any one of any one of the preceding claims, wherein the dielectric layer is a nitride-based layer, and the passivation layer is an oxide-based layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the nitride-based semiconductor device is a depletion-mode high electron mobility transistor (D-Mode HEMT) .
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

thinning the second nitride-based semiconductor layer such that the second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion;

forming a first dielectric layer over the second nitride-based semiconductor layer;

forming a first electrode and a second electrode over the first portion and the second portion of the second nitride-based semiconductor layer, respectively;

forming a gate electrode over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes; and

forming a gate field plate over the first portion of the second nitride-based semiconductor layer and between the gate electrode and the second electrode.
The method of any one of the preceding claims, further comprising forming a second dielectric layer over the second nitride-based semiconductor layer prior to thinning the second nitride-based semiconductor layer.
The method of any one of the preceding claims, further comprising removing a portion of the second dielectric layer prior to thinning the second nitride-based semiconductor layer.
The method of any one of the preceding claims, wherein the first dielectric layer is formed such that the first dielectric layer and the second dielectric layer are merged.
The method of any one of the preceding claims, wherein the gate field plate has an edge vertically coinciding with an interface between the first portion and the second portion of the second nitride-based semiconductor layer.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a first portion and a second portion connected to the first portion and thicker than the first portion;

a first electrode and a second electrode disposed over the first portion and the second portion of the second nitride-based semiconductor layer, respectively;

a gate electrode disposed over the first portion of the second nitride-based semiconductor layer and between the first and second electrodes; and

a dielectric layer covering the second nitride-based semiconductor layer and penetrated by the first electrode and the second electrode.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the dielectric layer has a first portion and a second portion which cover the first portion and the second portion of the second nitride-based semiconductor layer, respectively so as to become stepwise shaped.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the second portion of the dielectric layer is thicker than the first portion of the dielectric layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the first electrode and the second electrode extend to different depths within a thickness range of the second nitride-based semiconductor layer.
The nitride-based semiconductor device according of any one of the preceding claims, wherein the nitride-based semiconductor device is a depletion-mode high electron mobility transistor (D-Mode HEMT) .