WO2024040463A1

WO2024040463A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2024040463A1
Application number: PCT/CN2022/114493
Authority: WO
Inventors: Kai Hu; King Yuen Wong; Huixin He; Zhongyu ZHANG
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-08-24
Filing date: 2022-08-24
Publication date: 2024-02-29
Also published as: CN118103987A

Abstract

A semiconductor device includes a first and a second nitride-based semiconductor layers, a first passivation layer, a gate electrode, and a first field plate. The first passivation layer has a first portion with at least one thickness modulating structure and a second portion having a planar structure. The first passivation layer makes contact with a top surface of the second nitride-based semiconductor layer to provide a variable stress thereto, such that an electron density of a first zone of the 2DEG region beneath the first portion is different from that of a second zone of the 2DEG region beneath the second portion. The first field plate is disposed over the first passivation layer and extends horizontally above the gate electrode. An orthogonal projection of the first field plate on the second nitride-based semiconductor layer is located out of the thickness modulating structure on the second nitride-based semiconductor layer.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Kai HU; King Yuen WONG; Huixin HE; Zhongyu ZHANG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device with a variable two-dimensional electron gas (2DEG) region.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first passivation layer, a gate electrode, and a first field plate. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. The first passivation layer covers the first and second nitride-based semiconductor layers. The first passivation layer has a first portion with at least one thickness modulating structure and a second portion having a planar structure, such that the first portion has a thickness different from that of the second portion. The first passivation layer makes contact with a top surface of the second nitride-based semiconductor layer to provide a variable stress thereto, such that an electron density of a first zone of the 2DEG region beneath the first portion is different from that of a second zone of the 2DEG region beneath the second portion. The gate electrode is disposed over the first passivation layer. The first field plate is disposed over the first passivation layer and extends horizontally above the gate electrode. An orthogonal projection of the first field plate on the second nitride-based semiconductor layer is located out of an orthogonal projection of the thickness modulating structure on the second nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. A blanket passivation layer is formed to make contact with the second nitride-based semiconductor layer. A patterning process is performed on the blanket passivation layer to form a first passivation layer, such that a first portion of the first passivation layer has a different thickness from a second portion of the first passivation layer, thereby imposing a variable stress provided by the first passivation layer on the second nitride-based semiconductor layer to modulate an electron density of the 2DEG region. A gate electrode is formed over the first passivation layer. A first field plate is formed over the first passivation layer and the gate electrode, such that an orthogonal projection of the first field plate on the second nitride-based semiconductor layer is located out of an orthogonal projection of the first portion of the first passivation layer on the second nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a stress inducing layer, a source and a drain electrodes, a gate electrode, and a source-connected field plate. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. The stress inducing layer is disposed over and in contact with the second nitride-based semiconductor layer. The source and drain electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and between the source and drain electrodes. A portion of the stress inducing layer has a thickness different from that of the remaining portion thereof is located between the gate and the drain electrodes, such that the portion provides a greater stress than the remaining portion to the second nitride-based semiconductor layer, thereby inducing an increased electron density of a zone of the 2DEG region beneath the portion. The source-connected field plate is disposed over and coupled to the source electrode. The source-connected field plate spans across the gate electrode and terminates at a position between the gate electrode and the portion of the stress inducing layer.

By the above configuration, in the present disclosure, by forming a thickness modulation structure to one of the barrier layer of the nitride-based semiconductor device and a passivation layer above the barrier layer, an electron density of the 2DEG region of the nitride-based semiconductor device can be modulated flexibly. The probability of occurring breakdown phenomenon can be reduced. Thus, the nitride-based semiconductor device can have good reliability.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is an enlarged cross-sectional view of a region in the FIG. 1A;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4B is an enlarged cross-sectional view of a region in the FIG. 4A;

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 7 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. FIG. 1B is an enlarged vertical cross-sectional view of a region A in the FIG. 1A. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, passivation layers 20A, 24,

electrodes

24, 26, conductive vias 36, a passivation layer 38,

field plates

40, 42, a passivation layer 50, conductive vias 52, and isolation structures ISO.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A can further include a buffer layer (not shown) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the substrate 10. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

With respect to the nitride-based semiconductor device, it utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region. The distribution of the 2DEG region would affect electric field distribution in the device. As the electric filed intensity of a localized region in the device exceeds breakdown strength, breakdown phenomenon occurs. Thus, the device may fail. Therefore, there is a need to modulate an electron density of a desired region of the 2DEG region.

A conventional way to modulate a 2DEG region is to alter ratio of the aluminum (Al) content in a barrier layer. Nevertheless, from a process perspective, it is difficult to form a barrier layer having different portions with different Al contents at once. Accordingly, it is difficult to adjust concentration of a 2DEG region of a nitride-based semiconductor device by such a manufacturing method.

At least to solve the aforesaid issues, the present disclosure provides a novel structure.

Electron density of the 2DEG region is positively related to polarization extent of the two nitride-based semiconductor layers. Polarization extent of two nitride-based semiconductor layers 12, 14 can be determined by stress distribution therein. At least to alter the stress distribution of the nitride-based semiconductor layers 12, 14, a passivation layer 20A with different thicknesses is formed to cover the nitride-based semiconductor layers 12, 14.

The material of the passivation layer 20A is different from that of the nitride-based semiconductor layer 14, such that a lattice constant of the passivation layer 20A is different from that of the nitride-based semiconductor layer 14. Thus, the passivation layer 20A can provide additional stress to the nitride-based semiconductor layer 14 thereunder. In some embodiments, the exemplary materials of the passivation layer 20A can be selected as aluminum nitride (AlN) or aluminum oxynitride (AlON) , or a combination thereof. By such a material selection, the passivation layer 20A can provide a compressive stress to the nitride-based semiconductor layer 14 thereunder.

Specifically, the passivation layer 20A includes a portion 202A with at least one thickness modulating structure 2022A and a portion 204A with a planar structure, such that the portion 202A has a thickness different from that of the portion 204A, thereby providing a variable compressive stress to the nitride-based semiconductor layer 14. Hence, the passivation layer 20A can be referred as a stress inducing layer. The thickness modulating structure 2022A includes a recess structure. The portion 202A recesses inwardly to form the recess structure. The planar structure of the portion 204A can include a flat top surface. The portion 202A can have a thickness less than that of the portion 204A, and thus the portion 202A can provide a higher/greater compressive stress than the portion 204A, inducing an increase of an electron density of the 2DEG region regionally. Referring to FIG. 1B, due to the aforesaid thickness relationship, an electron density of a zone Z1 of the 2DEG region G beneath the portion 202A is higher than that of a zone Z2 of the 2DEG region G beneath the portion 204A. Furthermore, the profile of the thickness modulating structure 2022A can determine the distribution of the electron density of the 2DEG region G. In some embodiments, the recess structure of the thickness modulating structure 2022A can have a rectangular profile, and thus the distribution of electron density of the zone Z1 of the 2DEG region G can be rectangular distribution.

In the present disclosure, the distribution of electron density of the 2DEG region can be modified by forming a passivation layer 20A with different thicknesses over the nitride-based semiconductor layer 14. The formed passivation layer 20A can provide a variable stress to the nitride-based semiconductor layer 14, such that the stress distribution of the nitride-based semiconductor layers 12, 14 is modified, thereby changing the electron density distribution of the 2DEG region G. By such a configuration, the modification of electric field distribution can be realized in a relatively simple manufacturing method.

The passivation layer 22 is disposed on/over/above the passivation layer 20A. The passivation layer 22 makes contact with a top surface of the passivation layer 22. A bottom portion of the passivation layer 22 is complementary to that of a top portion of the passivation layer 20A. A portion of the passivation layer 22 extends into the thickness modulating structure 2022A to make contact with the passivation layer 20A. The material of the passivation layer 22 is different from that of the passivation layer 20A. The material of the passivation layer 22 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 22 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the passivation layer 22 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The

electrodes

24 and 26 can be disposed on/over/above the nitride-based semiconductor layer 14. The

electrodes

24 and 26 penetrate the passivation layers 20A and 22 to make contact with a top surface of the nitride-based semiconductor layer 14. In some embodiments, the electrode 24 can serve as a source electrode. In some embodiments, the electrode 24 can serve as a drain electrode. In some embodiments, the electrode 26 can serve as a source electrode. In some embodiments, the electrode 26 can serve as a drain electrode. The role of the

electrodes

24 and 26 depends on the device design.

In some embodiments, the

electrodes

24 and 26 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

24 and 26 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

24 and 26 may be a single layer, or plural layers of the same or different composition. The

electrodes

24 and 26 form ohmic contacts with the nitride-based semiconductor layer 14. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

24 and 26. In some embodiments, each of the

electrodes

24 and 26 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layer 28 is disposed on/over/above the passivation layer 22. The passivation layer 28 makes contact with a top surface of the passivation layer 22. The exemplary materials of the passivation layer 28 can be similar or the same as the passivation layer 22.

The gate electrode 30 is disposed on/over/above the passivation layer 20A. The gate electrode 30 penetrates the passivation layers 28, 22 to make contact with a top surface of the portion 204A of the passivation layer 20A. The gate electrode 30 is located between the

electrodes

22, 24. In some embodiments, the electrode 24 is closer to the gate electrode 30 than the electrode 26. That is, the

electrodes

22 and 24 can be arranged as being asymmetrical about the gate electrode 30. In some embodiments, the

electrodes

22 and 24 can be arranged as being symmetrical about the gate electrode 30. The arrangement depends on different electrical property requirements.

The exemplary materials of the gate electrode 30 may include metals or metal compounds. The gate electrode 30 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

By such a configuration, the nitride-based semiconductor device 1A is a depletion-mode device, which means the nitride-based semiconductor device 1A in a normally-on state at zero gate-source voltage.

The passivation layer 38 is disposed on/over/above the passivation layer 28 and the gate electrode 30. The passivation layer 38 covers the passivation layer 28 and the gate electrode 30. The exemplary materials of the passivation layer 38 can be similar or the same as the passivation layer 22.

The contact vias 36 are disposed within the passivation layer 38. The contact vias 36 can penetrate the passivation layer 38. The contact vias 36 can extend longitudinally to connect to the

electrodes

24 and 26, respectively. The top surfaces of the contact vias 36 are free from coverage of the passivation layer 38. The exemplary materials of the contact vias 36 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The

field plates

40 and 42 are disposed on/over/above the passivation layer 38. The

field plates

40, 42 are located at the same layer. Height levels of the

field plates

40, 42 are the same. The field plate 40 is disposed on/over/above the electrode 24. The field plate 42 is disposed on/over/above the electrode 26. The field plate 40 makes contact with one of the contact vias 36 to be electrically connected/coupled to the electrode 24. The field plate 42 makes contact with another one of the contact vias 36 to be electrically connected/coupled to the electrode 26. In some embodiments, the electrode 24 can be a source electrode, and the electrode 26 can be a drain electrode. Thus, the field plate 40 can be a source-connected field plate, and the field plate 42 can be a drain-connected field plate.

The field plate 40 extends horizontally over the gate electrode 30 and the electrode 24. The field plate 40 spans across the gate electrode 30 and terminates at a position P between the gate electrode 30 and the electrode 26, in which the position P is located between the gate electrode 30 and the portion 202A (i.e., the horizontal location) . An entirety of the gate electrode 30 is covered by the field plate 40. The field plate 42 extends horizontally over the electrode 24. The

field plates

40, 42 are separated from each other. The configuration of the

field plates

40, 42 can make the electric field distribution more uniform.

The exemplary materials of the

field plates

40, 42 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used. Thus, each of the

field plates

40, 42 can be referred as a conductive layer. In some embodiments, the

field plates

40, 42 are formed from the same layer. For example, a blanket conductive layer can be patterned to form the separated

field plates

40, 42. In some embodiments, the blanket conductive layer is patterned such that a metal layer is formed at the same elevation as the

field plates

40, 42. In some embodiments, the blanket conductive layer is patterned such that the

field plates

40, 42 can serve as a metal layer or a circuit layer.

In the present disclosure, an orthogonal projection of the field plate 40 on the nitride-based semiconductor layer 14 is designed to be located out of an orthogonal projection of the thickness modulating structure 2022A/the portion 202A on the nitride-based semiconductor layer 14. The portion 202A with the thickness modulating structure 2022A of the passivation layer 20A is designed to be located between the field plates 40, 42 (or between the gate electrode 30 and the electrode 38) . An end surface of the field plate 40 vertically coincides with an end surface of the thickness modulating structure 2022A. The configuration of the thickness modulating structure 2022A can modulate (increase) electron density of the zone Z2 (e.g., a desired modulated zone) of the 2DEG region G between the

field plates

40, 42, and thus a favorable electric field distribution can be achieved. Withstand voltage of the nitride-based semiconductor device 1A can be further improved.

In some embodiments, in order to minimize the negative influence of parasitic capacitance between the field plate and the 2DEG region in the vertical direction, it should be noted that each of the

field plates

40, 42 is designed to not vertically overlap with the thickness modulating structure 2022A, which means that the thickness modulating structure 2022A is free from coverage of the

field plates

40, 42.

The passivation layer 50 is disposed over the

field plates

40, 42 and the passivation layer 38. The exemplary materials of the passivation layer 50 can be similar or the same as the passivation layer 22. Moreover, the passivation layer 50 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer 50 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 50 to remove the excess portions, thereby forming a level top surface.

The conductive vias 52 are disposed within the passivation layer 38. The contact vias 52 can penetrate the passivation layer 50. The contact vias 36 can extend longitudinally to connect to the

field plates

40, 42, respectively. An external electronic device (not shown) can send at least one electrical signal to the nitride-based semiconductor device 1A via the conductive vias 52 , and vice versa. The exemplary materials of the contact vias 52 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The isolation structures ISO are disposed on/over/above the nitride-based semiconductor layer 12. The isolation structures ISO are located at two opposite sides of the nitride-based semiconductor layers 12, 14 to realize device isolation. In some embodiments, the isolation structure ISO can include solid material such as dielectric material, in which the dielectric material can be for example, oxide, or silicon nitride. In some embodiments, the isolation structure ISO can be an implant region or well. In some embodiments, the isolation structure ISO can be a trench.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A nitride-based semiconductor layer 12 is formed on/over/above the substrate 10. A nitride-based semiconductor layer 14 is formed on/over/above the nitride-based semiconductor layer 12. The nitride-based semiconductor layer 12 has a bandgap greater than that of the nitride-based semiconductor layer 14 to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. A blanket passivation layer 60 is formed on/over/above the nitride-based semiconductor layer 14 to make contact with the nitride-based semiconductor layer 14. The formation of the nitride-based semiconductor layers 12, 14 and the blanket passivation layer 60 includes deposition techniques.

Referring to FIG. 2B, a patterning process is performed on the blanket passivation layer 60 to form a passivation layer 20A, such that a portion 202A of the passivation layer 20A has a different thickness from a portion 204A of the passivation layer 20A, thereby imposing a variable stress provided by the passivation layer 20A on the nitride-based semiconductor layer 14 to modulate (increase) an electron density of the 2DEG region.

Referring to FIG. 2C, a passivation layer 22 is formed to cover the resulted structure of FIG. 1A. Portions of the passivation layers 20A, 22 are removed to form a plurality of through holes, and parts of top surface of the nitride-based semiconductor layer 14 are exposed by the through holes of the passivation layers 20A, 22.

Electrodes

24, 26 are formed on/over/above the nitride-based semiconductor layer 14.

Electrodes

24, 26 are formed in the through holes of the passivation layers 20A, 22 to make contact with the top surface of the nitride-based semiconductor layer 14. A plurality of isolation structures ISO are formed at two sides of the nitride-based semiconductor layers 12, 14. A passivation layer 28 is formed to cover the

electrodes

24, 26, and the passivation layer 22. Portions of the

passivation layer

22 and 28 are removed to form a through hole to expose a top surface of the passivation layer 20A. The gate electrode 30 is formed on/over/above the passivation layer 20A. The

electrodes

24, 26 are located at two opposite sides of the gate electrode 30. The gate electrode 30 is formed in the through hole of the passivation layers 22, 28 to make contact with the passivation layer 20A.

Referring to FIG. 2D, a passivation layer 38 is formed to cover the passivation layer 28. Portions of the passivation layers 28, 38 are removed to form a plurality of through holes, and the though holes of the passivation layers 28, 38 expose the

electrodes

24, 26. A plurality of conductive vias 36 are formed in the through holes of the passivation layers 28, 38 to make contact with the

electrodes

24, 22. The field plate 40 is formed on/over/above the passivation layer 20A and the gate electrode 30, such that an orthogonal projection of the field plate 40 on the nitride-based semiconductor layer 14 is located out of an orthogonal projection of the portion 202A of the passivation layer 20A on the nitride-based semiconductor layer 14. The field plate 40 is formed on/over/above one of the conductive via 36, such that the field plate 40 can be electrically coupled to the electrode 28 through the conductive via 36. The field plate 42 is formed over the passivation layer 20A and the electrode 22. The field plate 42 is formed on/over/above another one of the conductive vias 36, such that the field plate 42 can be electrically coupled to the electrode 22 through the conductive via 36. Thereafter, a passivation layer 50 and a plurality of conductive vias are formed in sequence, obtaining the nitride-based semiconductor device 1A in FIG 1A.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that an end of the orthogonal projection of the field plate 40 on the nitride-based semiconductor layer 14 is spaced apart from an end of the orthogonal projection of the thickness modulating structure 2022B on the nitride-based semiconductor layer 14. Such a configuration can meet a specific device requirement.

FIG. 4A is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. FIG. 4B is an enlarged cross-sectional view of a region A in the FIG. 4A. The nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the thickness modulating structure 2022C of the portion 202C further has a thickness variation structure TV adjacent to the portion 204C with planar structure, such that a sub-part PT of the portion 202C corresponded to the thickness variation structure 2022C has a gradually varied thickness. In some embodiments, the thickness variation structure TV includes an inclined surface, and then the sub-part PT of the portion 202C can have a linearly varied thickness. The thickness modulating structure 2022C can have an inverted trapezoid profile.

Referring to the FIG. 4B, a stress applied by the passivation layer 20C to the nitride-based semiconductor layer 14 is related to its thickness, and the electron density distribution of the 2DEG region is related to the stress. The sub-part PT with the thickness variation structure TV can induce a variable electron density (for example, linearly variable electron density) to a sub-zone SZ of the zone Z1 beneath the sub-part PT, and thus the sub-zone SZ of the zone Z1 can have a variable electron density. Such a configuration can achieve a more uniform electric field distribution in the nitride-based semiconductor device 1C.

In some embodiments, slopes of two inclined surfaces (i.e., left and right inclined surfaces) of the thickness modulating structure 2022C can be different or the same, so as to meet different device requirements. The configuration of the thickness variation structure TV can provide more design flexibility to the device.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the semiconductor device 1C as described and illustrated with reference to FIG. 4A, except that the thickness variation structure TV includes a curved surface, in which the curved surface is a concave surface. In some embodiments, the curved surface can be a convex surface. Such a configuration can evenly distribute the stress from the passivation layer 22.

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the recess structure of the thickness modulating structure 2022E can have a jagged profile. Such a configuration can meet a specific device requirement.

FIG. 7 is a vertical cross-sectional view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the nitride-based semiconductor layer 14F has

different portions

142F, 144F with different thicknesses. The portion 142F of the nitride-based semiconductor layer 14F has a greater thickness than the portion 144F, such that the electron density of a zone of the 2DEG region beneath the portion 142F is greater than that of a zone of the 2DEG region beneath the portion 144F.

With respect to the nitride-based semiconductor device 1F, by additionally forming a material layer ML compositionally the same as the nitride-based semiconductor layer 14F on a desired modulation region, electron density of a zone of the 2DEG region beneath the material layer ML can be increased.

Based on the above descriptions, in the present disclosure, a passivation layer (i.e., stress inducing layer) with a thickness modulating structure is formed to make contact with the barrier layer, such that a variable stress provided by the passivation layer can be applied to the barrier layer and the channel layer, thereby altering the existing stress distribution in the barrier layer and the channel layer. The passivation layer with a thickness modulating structure can locally increase an electronic density of a zone directly under the thickness modulating structure, such that a better electric field distribution can be achieved in the device. Furthermore, the thickness modulating structure can be located out of the field plate, such that parasitic capacitance in a vertical direction between the field plate and the 2DEG region can be avoided.

On the other hand, a material layer compositionally the same as the barrier layer can be formed on the barrier layer to locally increase its thickness. An electron density of a zone of the 2DEG region beneath the material layer can be modulated, thereby achieving a better electric field distribution with a simple manufacturing method.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region;

a first passivation layer covering the first and second nitride-based semiconductor layers, wherein the first passivation layer has a first portion with at least one thickness modulating structure and a second portion having a planar structure, such that the first portion has a thickness different from that of the second portion,

wherein the first passivation layer makes contact with a top surface of the second nitride-based semiconductor layer to provide a variable stress thereto, such that an electron density of a first zone of the 2DEG region beneath the first portion is different from that of a second zone of the 2DEG region beneath the second portion;

a gate electrode disposed over the first passivation layer; and

a first field plate disposed over the first passivation layer and extending horizontally above the gate electrode, wherein an orthogonal projection of the first field plate on the second nitride-based semiconductor layer is located out of an orthogonal projection of the thickness modulating structure on the second nitride-based semiconductor layer.
The semiconductor device of claim 1, wherein an end of the orthogonal projection of the first field plate on the second nitride-based semiconductor layer is spaced apart from an end of the orthogonal projection of the thickness modulating structure on the second nitride-based semiconductor layer.
The semiconductor device of claim 1, wherein an end surface of the first field plate vertically coincides with an end surface of the thickness modulating structure.
The semiconductor device of claim 1, wherein the thickness modulating structure comprises a recess structure, such that the first portion has a thickness less than that of the second portion.
The semiconductor device of claim 4, wherein the recess structure has a rectangular profile, an inverted trapezoid profile, or a jagged profile.
The semiconductor device of claim 1, wherein a lattice constant of the first passivation layer is different from that of the second nitride-based semiconductor layer.
The semiconductor device of claim 1, wherein an entirety of the gate electrode is covered by the first field plate.
The semiconductor device of claim 1, wherein the thickness modulating structure of the first portion further has a thickness variation structure, such that a sub-part of the first portion corresponded to the thickness variation structure has a gradually varied thickness.
The semiconductor device of claim 8, wherein a sub-zone of the first zone beneath the sub-part of first portion has a variable electron density.
The semiconductor device of claim 8, wherein the thickness variation structure comprises an inclined surface or a curved surface.
The semiconductor device of claim 8, wherein the thickness variation structure is adjacent to the second portion.
The semiconductor device of claim 1, further comprising:

a source and a drain electrodes disposed over the second nitride-based semiconductor layer, wherein the gate electrode is between the source and drain electrodes,

wherein the first field plate horizontally extends and terminates at a position between and above the gate and drain electrodes.
The semiconductor device of claim 1, further comprising a second passivation layer disposed over the first passivation layer, wherein a shape of a bottom portion of the second passivation layer is complementary to that of a top portion of the first passivation layer.
The semiconductor device of claim 1, further comprising a second field plate disposed over the first passivation layer and separated from the first field plate.
The semiconductor device of claim 1, wherein the first passivation layer comprises aluminum nitride, aluminum oxynitride, or a combination thereof.
A manufacturing method of a semiconductor device, comprising:

forming a first nitride-based semiconductor layer over a substrate;

forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region;

forming a blanket passivation layer to make contact with the second nitride-based semiconductor layer;

performing a patterning process on the blanket passivation layer to form a first passivation layer, such that a first portion of the first passivation layer has a different thickness from a second portion of the first passivation layer, thereby imposing a variable stress provided by the first passivation layer on the second nitride-based semiconductor layer to modulate an electron density of the 2DEG region;

forming a gate electrode over the first passivation layer; and

forming a first field plate over the first passivation layer and the gate electrode, such that an orthogonal projection of the first field plate on the second nitride-based semiconductor layer is located out of an orthogonal projection of the first portion of the first passivation layer on the second nitride-based semiconductor layer.
The method of claim 16, further comprising:

forming a source electrode and a drain electrode on the second nitride-based semiconductor layer and at two opposite sides of the gate electrode respectively prior the step of forming the first field plate.
The method of claim 17, wherein the first field plate is formed to be electrically coupled to the source electrode.
The method of claim 17, further comprising:

forming a second field plate over the first passivation layer to be electrically coupled to the drain electrode.
The method of claim 16, wherein the blanket passivation layer comprises aluminum nitride, aluminum oxynitride, or a combination thereof.
A semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer having a bandgap greater than that of the first nitride-based semiconductor layer to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region;

a stress inducing layer disposed over and in contact with the second nitride-based semiconductor layer;

a source and a drain electrodes disposed over the second nitride-based semiconductor layer;

a gate electrode disposed over the second nitride-based semiconductor layer and between the source and drain electrodes, wherein a portion of the stress inducing layer having a thickness different from that of the remaining portion thereof is located between the gate and the drain electrodes, such that the portion provides a greater stress than the remaining portion to the second nitride-based semiconductor layer, thereby inducing an increased electron density of a zone of the 2DEG region beneath the portion; and

a source-connected field plate disposed over and coupled to the source electrode, wherein the source-connected field plate spans across the gate electrode and terminates at a position between the gate electrode and the portion of the stress inducing layer.
The semiconductor device of claim 21, wherein a lattice constant of the stress inducing layer is different from that of the second nitride-based semiconductor layer.
The semiconductor device of claim 21, further comprising a drain-connected field plate disposed over and coupled to the drain electrode, wherein the drain-connected field plate and the source-connected field plate are located at the same layer.
The semiconductor device of claim 21, further comprising a passivation layer disposed over the stress inducing layer, wherein a material of the passivation layer is different from that of the stress inducing layer.
The semiconductor device of claim 24, wherein the portion of the stress inducing layer recesses inwardly to form a recess structure, and the passivation layer extends into the recess structure to make contact with the stress inducing layer.