WO2017088253A1 - Dispositif hemt à mode d'enrichissement empêchant l'effet de chute de courant et son procédé de préparation - Google Patents

Dispositif hemt à mode d'enrichissement empêchant l'effet de chute de courant et son procédé de préparation Download PDF

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WO2017088253A1
WO2017088253A1 PCT/CN2015/099391 CN2015099391W WO2017088253A1 WO 2017088253 A1 WO2017088253 A1 WO 2017088253A1 CN 2015099391 W CN2015099391 W CN 2015099391W WO 2017088253 A1 WO2017088253 A1 WO 2017088253A1
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layer
semiconductor
quantum well
gate
hemt device
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PCT/CN2015/099391
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Chinese (zh)
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孙钱
周宇
冯美鑫
李水明
高宏伟
杨辉
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中国科学院苏州纳米技术与纳米仿生研究所
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Publication of WO2017088253A1 publication Critical patent/WO2017088253A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to an enhanced HEMT device that suppresses a current collapse effect and a method of fabricating the same.
  • HEMTs Compared to conventional silicon-based MOSFETs, AGaN/GaN heterojunction-based High Electron Mobility Transistors (HEMTs) have the unique advantages of low on-resistance, high breakdown voltage, and high switching frequency. As a core device in various types of power conversion systems, it has important application prospects in terms of energy saving and consumption reduction, and therefore has received great attention from academic and industrial circles. In addition, in order to meet the requirements of fail-safe and simplified control circuits, the enhancement-enhancement HEMT has obvious application advantages.
  • FIG. 1a shows the exhaustion Schematic diagram of electron trapping center distribution in open HEMT epitaxial materials
  • Figure 1b is a schematic diagram of electron trapping center distribution in enhanced normally-off HEMT epitaxial materials), which will be electrons in the channel during high-speed opening and closing of the device
  • Electron gas forms a physical process of Trapping and De-trapping (as shown in Figure 2): where the gate-injected electrons are captured by the surface state, changing the surface charge distribution, thereby affecting the two-dimensionality at the channel.
  • Electron gas concentration when the device is under high voltage and high current operation, the hot electrons are trapped by the electron trapping center of the material (distributed in the barrier layer, the channel layer, the buffer layer, the p-type layer and various interfaces). Since the electron release process (return to the channel) has a certain time constant, when the electron capture/release process lags behind the device on/off action, it causes a current collapse effect, which leads to an increase in the dynamic on-resistance of the device. The series of reliability issues, this has become the biggest bottleneck to achieve true commercialization of HEMT.
  • the conventional technical route currently adopted is to passivate the surface of the device, such as depositing a dielectric layer such as SiN x or AlN, or a stacked combination of different dielectric layers, such as AlN/Al 2 O 3 .
  • the Low Pressure Chemical Vapor Deposition (LPCVD) technique is generally used to deposit the SiN x passivation layer on the surface of the epitaxial wafer first, followed by subsequent devices. Process.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • other dielectric layer deposition techniques such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Atom Layer Deposition (ALD), etc., are used to perform device surface passivation after the ohmic contact process is completed.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • ALD Atom Layer Deposition
  • the passivation layer technique described above can only partially suppress the current collapse effect associated with the surface state.
  • the electron trapping centers inside the material are The hot electron capture process during high voltage and high current operation is very significant, and the current collapse effect and dynamic resistance characteristic degradation phenomenon are very serious. Therefore, the existing surface passivation technology cannot fundamentally solve the current collapse effect caused by the electron trapping centers (distributed in the barrier layer, the channel layer, the buffer layer, the p-type layer, and various interfaces) inside the material.
  • the p-type gate process is usually adopted.
  • the distance between the p-type gate and the two-dimensional electron gas needs to be reduced, so that when the p-type gate is grown, it needs to be immediately Achieve p-type layer growth.
  • the p-type material is grown by conventional MOCVD process, due to the memory effect of Mg, it takes a long time for Mg doping to be incorporated, and it is impossible to achieve high Mg doping immediately.
  • the grown material has weak p-type or unintentional. Doped type, the growth of the p-type layer cannot be achieved immediately.
  • a primary object of the present invention is to provide an enhanced HEMT device that suppresses current collapse effects and a method of fabricating the same to overcome the deficiencies in the prior art.
  • the technical solution adopted by the present invention includes:
  • One embodiment of the present invention provides an enhanced HEMT device that suppresses a current collapse effect, including a heterostructure and a source, a drain, and a gate connected to the heterostructure, the heterostructure including a first semiconductor of the channel layer and a second semiconductor as a barrier layer formed on the first semiconductor, the two-dimensional electron gas being formed in the heterostructure; wherein: the second A quantum well layer and a third semiconductor are also sequentially formed on the semiconductor, and the third semiconductor and the second semiconductor have different conductivity types, and the gate is in electrical contact with the third semiconductor.
  • One embodiment of the present invention provides a method of fabricating the enhanced HEMT device that suppresses a current collapse effect, comprising:
  • the heterostructure including a first semiconductor as a channel layer and a second semiconductor as a barrier layer, the second semiconductor being formed on the first semiconductor a two-dimensional electron gas is formed in the heterogeneous structure;
  • a source and a drain are provided in the device formed by the foregoing processing.
  • a quantum well layer, a P-type layer, or the like may also be formed on the heterostructure by epitaxial epitaxy.
  • the present invention has at least the following advantages:
  • the present invention directly integrates a quantum well structure in a gate region and a non-gate region in an enhancement type HEMT device, so that when the device is in an on state, light emission can be simultaneously achieved, and the light emission can be effectively radiated in the gate-drain and gate - the surface area between the sources and deep into the material, which can accelerate the release process of electrons captured by various defect states, thereby effectively suppressing the device current collapse effect;
  • the p-type gate after the integration of the quantum well can cause the gate avalanche breakdown phenomenon in the case of large forward gate voltage, which can play the role of early warning and feedback through the illuminating signal, which improves the safety of the device operation. ;
  • the p-type nitride layer is divided into two layers, wherein the first p-type nitride layer adopts a low-temperature p-type growth process, which can realize the rapid incorporation of the Mg source and enhance the p-type gate to the two-dimensional electron gas. Regulatory ability.
  • FIG. 1a and 1b are schematic diagrams showing the distribution of electron capture centers of the depleted normally open and enhanced normally closed HEMT devices in the prior art
  • FIG. 2 is a schematic diagram showing the physical principle of a current collapse effect of a HEMT device (taking a depleted normally-off HEMT as an example) in the prior art;
  • FIG. 3 is a schematic structural view of an enhanced HEMT device in a first embodiment of the present invention.
  • FIGS. 4a to 4h are flowcharts showing a process of preparing an enhanced HEMT device in a second embodiment of the present invention.
  • FIG. 5 is a schematic structural view of an enhanced HEMT device in a third embodiment of the present invention.
  • 6a-6f are flowcharts showing a process of preparing an enhanced HEMT device in a fourth embodiment of the present invention.
  • Figure 7 is a block diagram showing the structure of an enhanced HEMT device in a fifth embodiment of the present invention.
  • One aspect of the present invention provides an enhanced HEMT device that suppresses a current collapse effect, including a heterostructure and a source, a drain, and a gate connected to the heterostructure, the heterostructure including as a trench a first semiconductor of the via layer and a second semiconductor as a barrier layer formed on the first semiconductor (generally, the second semiconductor has a band gap wider than the first semiconductor), the heterogeneity a two-dimensional electron gas is formed in the structure; a quantum well layer and a third semiconductor are sequentially formed on the second semiconductor, and the third semiconductor and the second semiconductor are electrically conductive The type (n-type or p-type) is different, and the gate is in electrical contact with the third semiconductor.
  • the gate is distributed between the source and the drain, the third semiconductor is completely masked by the gate or the third semiconductor is not completely masked by the gate.
  • the gate is distributed between the source and the drain, and the quantum well layer is completely masked by the gate, or the quantum well layer is distributed under the gate And in a region between the gate and the source and/or the drain.
  • the third semiconductor includes a first structural layer and a second structural layer formed on the first structural layer.
  • the growth temperature of the first structural layer is lower than the growth temperature of the second structural layer.
  • a cover layer is also disposed between the quantum well layer and the third semiconductor.
  • an intervening layer is further disposed between the first semiconductor and the second semiconductor.
  • the HEMT device further includes a substrate, and a buffer layer is further disposed between the substrate and the heterostructure.
  • an ohmic contact is formed between the source and drain and the second semiconductor.
  • the range of illuminating wavelengths of the quantum well material in the quantum well layer comprises a visible light band and/or an ultraviolet band.
  • the quantum well material may be selected from, but not limited to, any one or a combination of two or more of InGaN, GaN, AlGaN, AlInN, and AlInGaN.
  • the quantum well structure in the quantum well layer comprises a single quantum well, a double quantum well, a multiple quantum well structure, or a superlattice structure.
  • the quantum well structure in the quantum well layer can be selected from, but not limited to, a GaN/InGaN/AlGaN structure, a GaN/InGaN/GaN/AlGaN structure, a GaN/InGaN/AlN/AlGaN structure, and an AlN/ Any one of structures such as InGaN/AlN/AlGaN.
  • the quantum barrier material in the quantum well layer may be selected from, but not limited to, any one of GaN, InGaN, AlGaN, AlInN, AlInGaN, AlN, or a combination of two or more thereof.
  • the heterostructure can be selected from, but not limited to, an AlGaN/AlN/GaN heterojunction, an AlInN/AlN/GaN heterojunction, an AlInGaN/AlN/GaN heterojunction, a two-channel heterostructure Any one or a combination of two or more of the knots.
  • the Al composition in the barrier layer may be graded, wherein the thickness, composition, and structure of the barrier layer affect the implantation in the electron and hole vector sub-wells and dry etching Stop position.
  • the third semiconductor includes a p-type semiconductor, such as, for example, but not limited to, any one or two of p-GaN, p-AlGaN, p-AlInN, p-InGaN, and p-AlInGaN. More than one combination.
  • the doping concentration of magnesium ions or the like is not limited to a single doping concentration, and may be a function of the z-direction of epitaxial growth.
  • the HEMT device may be a basic HEMT having no passivation layer, no field plate, or the like, or a HEMT having a complicated structure such as a passivation layer or a field plate.
  • the substrate may be selected from, but not limited to, any one of silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, or a combination of two or more;
  • the constituent material of the intercalation layer may be selected from, but not limited to, any one of AlN, AlInN, AlInGaN, or a combination of two or more.
  • the gate metal can be selected from, but not limited to, tungsten (W), and also includes other metals such as titanium nitride (TiN), titanium tungsten alloy (TiW).
  • an enhanced HEMT device that suppresses a current collapse effect can include:
  • nitride buffer layer on the substrate
  • nitride channel layer on the nitride buffer layer
  • nitride barrier layer on the nitride channel layer
  • a source and a drain in contact with the nitride barrier layer, and a gate between the source and the drain, and a quantum well layer and a p are formed between the gate and the nitride barrier layer A nitride layer, the quantum well layer being over the nitride barrier layer, the p-type nitride layer being over the quantum well layer, the gate being in contact with the p-type nitride layer.
  • an AlN insertion layer may be disposed between the nitride channel layer and the nitride barrier layer.
  • a thin layer of GaN may be present between the barrier layer (eg, AlGaN) and the quantum well (eg, InGaN) to enhance the luminous efficiency of the quantum well.
  • the barrier layer eg, AlGaN
  • the quantum well eg, InGaN
  • the quantum well layer covers at least a nitride barrier layer disposed under the gate.
  • the quantum well layer covers a nitride barrier layer between the gate and the source and/or a nitride potential between the gate and the drain, in addition to the nitride barrier layer under the gate.
  • Base layer a nitride barrier layer between the gate and the source and/or a nitride potential between the gate and the drain.
  • the p-type nitride layer comprises a first p-type nitride layer on the quantum well layer and a second p-type nitride layer on the first p-type nitride layer.
  • a nitride coating layer may be disposed between the p-type nitride layer and the quantum well layer.
  • the buffer layer, the channel layer, the barrier layer, the p-type layer, the interposer layer, and the like are all described by taking a nitride material as an example, and in other embodiments, it may be other than nitride.
  • a nitride material as an example, and in other embodiments, it may be other than nitride.
  • Other semiconductor materials are also described.
  • Another aspect of the present invention provides a method of fabricating the enhanced HEMT device that suppresses a current collapse effect, comprising:
  • the heterostructure including a first semiconductor as a channel layer and a second semiconductor as a barrier layer, the second semiconductor being formed on the first semiconductor a two-dimensional electron gas is formed in the heterogeneous structure;
  • a source and a drain are provided in the device formed by the foregoing processing.
  • the preparation method may include: after the third semiconductor layer is grown, performing active region isolation on the formed device, and then forming a gate material layer on the third semiconductor layer.
  • the preparation method may specifically include:
  • the active region is isolated by ion implantation technology, and the ion implantation depth is to the nitride buffer layer;
  • a source ohmic contact electrode and a drain ohmic contact electrode are prepared on the source region and the drain region.
  • etching the non-gate region includes:
  • the non-gate regions of the p-type nitride layer and the quantum well layer are etched using an inductively coupled plasma etch process until a nitride barrier layer is exposed.
  • etching the non-gate region may also include:
  • the non-gate region of the p-type nitride layer is etched by an inductively coupled plasma etch process until the quantum well layer is exposed;
  • the source and drain regions of the quantum well layer are etched using an ion beam etch process until a nitride barrier layer is exposed.
  • the buffer layer, the channel layer, the barrier layer, the p-type layer, the interposer layer, and the like are all nitrogen.
  • the material is described as an example, and in other embodiments, it may be a semiconductor material other than a nitride.
  • the etch etching may be performed by using, but not limited to, an ICP etching technique or other various dry etching techniques.
  • a mask function may be implemented by using, but not limited to, a photoresist or other dielectric layer including SiO x (0 ⁇ x ⁇ 3), SiN x (0 ⁇ x ⁇ 3).
  • a quantum well layer, a p-type layer, or the like may also be formed by epitaxial epitaxy on the heterostructure. It can be selected but not limited to the following two ways:
  • the P-type layer is epitaxially grown by pattern selection.
  • selection area extension and the implementation process thereof can be easily known and understood by those skilled in the art based on the existing knowledge in the industry, and are not described herein again.
  • the invention directly integrates the quantum well structure in the epitaxial structure of the p-type gate-based enhanced HEMT, and promotes the composite luminescence of electrons and holes, and the luminescence can be radiated to the surface of the device and the body region, thereby accelerating the capture by various defect states.
  • the electron release process effectively suppresses the device current collapse effect, significantly reduces the on-resistance of the device during operation, improves dynamic characteristics, and improves device reliability.
  • an enhanced HEMT device in a first embodiment of the present invention includes:
  • a source 91 and a drain 92 in contact with the nitride barrier layer 50 a gate 93 between the source and the drain, a quantum well layer 60 formed between the gate 93 and the nitride barrier layer 50, and
  • the p-type nitride layer 80 is disposed above the nitride barrier layer 50, the p-type nitride layer 80 is positioned above the quantum well layer 60, and the gate 93 is in contact with the p-type nitride layer 80.
  • the quantum well structure is directly integrated in the epitaxial structure of the p-type gate-based enhancement type HEMT, that is, by epitaxially growing the quantum well layer 60 between the p-type nitride layer 80 and the nitride barrier layer 50, electrons can be promoted.
  • the composite luminescence of the holes in the gate region The illuminating radiation to the surface region between the gate-drain and the gate-source can penetrate deep into the body region, which can accelerate the release process of electrons captured by various defect states, thereby effectively suppressing the device current collapse effect.
  • the principle is shown in Figure 3.
  • the enhanced HEMT device in the second embodiment of the present invention is an AlGaN/GaN heterojunction-based HEMT device epitaxially grown by MOCVD, which includes:
  • the substrate 10 may be a substrate of silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride or the like;
  • nitride channel layer 30 on the nitride buffer layer 20 in this embodiment, is a GaN layer;
  • the insertion layer 40 on the nitride channel layer 30, in this embodiment, the insertion layer 40 is an AlN insertion layer;
  • the nitride barrier layer 50 material is AlGaN;
  • the material of the first p-type nitride layer 81 and the second p-type nitride layer 82 is p-GaN, and the second p-type nitride layer 82 is doped with Mg, in other embodiments p
  • the nitride layer may also be selected from p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN, and composite structures thereof.
  • the magnesium doping concentration in the second p-type nitride layer is not limited to a single doping concentration, and may be a function along the z-direction of epitaxial growth.
  • the material of the quantum well layer 60 in the present embodiment is InGaN.
  • it may be GaN, AlGaN, AlInN, AlInGaN, etc., and the light-emitting range thereof includes from the visible light band to the ultraviolet light band.
  • the quantum well structure is not limited to the GaN/InGaN/AlGaN structure in the present embodiment, and may include a structure such as GaN/InGaN/GaN/AlGaN, GaN/InGaN/AlN/AlGaN, AlN/InGaN/AlN/AlGaN.
  • the quantum well structure is not limited to the single quantum well in the embodiment, and may include other double quantum wells, multiple quantum well structures or superlattice structures, and the quantum barrier material may include GaN, InGaN, AlGaN, AlInN, AlInGaN, AlN. Wait.
  • the nitride cap layer 70 is GaN, and the gate metal is metal tungsten (W).
  • the nitride cap layer may also be other nitride materials, and the gate metal is not limited to tungsten (W), but also includes titanium nitride (TiN). Other metal materials such as titanium tungsten alloy (TiW).
  • the active region is isolated by ion implantation technology, and the ion implantation depth is to the nitride buffer layer;
  • a source ohmic contact electrode and a drain ohmic contact electrode are prepared on the source region and the drain region.
  • the etching of the non-gate region includes:
  • the non-gate regions of the second p-type nitride layer, the first p-type nitride layer, the nitride cap layer, and the quantum well layer are etched using an inductively coupled plasma etch process until the nitride barrier layer is exposed.
  • a nitride buffer layer 20, a nitride channel layer 30, an interposer layer 40, and a nitride barrier layer 50 are epitaxially grown on the substrate 10 by MOCVD.
  • a GaN channel is selected.
  • 2DEG two-dimensional electron gas
  • the Al composition x in the Al x Ga 1-x N barrier layer is 10% to 35%
  • the thickness of the Al x Ga 1-x N barrier layer is 5 to 40 nm
  • the thickness of the AlN insertion layer is about 1 nm
  • the GaN groove The thickness of the channel layer is 20 to 200 nm.
  • the quantum well layer 60 is epitaxially grown on the nitride barrier layer 50 by MOCVD.
  • the quantum well layer is an In x Ga 1-x N quantum well layer.
  • In the In x Ga 1-x N In composition x is 0% ⁇ x ⁇ 50%, and the thickness of the In x Ga 1-x N quantum well layer is 0.3-8 nm
  • the nitride cap layer 70, the first p-type nitride layer 81, and the second p-type nitride layer 82 are epitaxially grown on the quantum well layer 60 by MOCVD, and the nitride cap layer in this embodiment.
  • 70 is a GaN cap layer
  • the first p-type nitride layer 81 and the second p-type nitride layer 82 are a first p-GaN layer and a second p-GaN layer, respectively.
  • the GaN cap layer has a thickness of 0.3 to 20 nm.
  • the p-GaN layer is divided into two layers, the first p-GaN layer has a thickness of 1 to 50 nm, a growth temperature of 700 to 1000 ° C, a growth rate of 10 to 3000 nm/h, and a thickness of the second p-GaN layer of 5 to 300 nm.
  • Magnesium doping in a p-GaN layer is rapidly turned on, reaching the order of 10 18 to 10 21 /cm 3 ; the second p-GaN layer is doped with magnesium, and the doping concentration of magnesium is in the range of 10 18 to 10 21 /cm. 3 orders of magnitude.
  • the active region above the nitride buffer layer 20 is isolated and isolated by N ion implantation technology, and the ion implantation energy is 150-400 KeV ion implantation, and the ion dose is 10 12 to 10 14 /cm. 2 , the implantation depth is about 50 to 250 nm beyond the buffer layer, and the isolation channel 101 is obtained in the active region of the HEMT epitaxial structure.
  • a metal layer of gate 93 is deposited on the second p-type nitride layer 82.
  • tungsten (W) metal deposition is performed by magnetron sputtering, and the deposition thickness is 50 to 200 nm.
  • the photoresist is etched on the non-gate region by using the photoresist AZ5214 as a mask:
  • the tungsten metal is etched by IBE (Ion Beam Etch), and etched to the end of the surface of the second p-GaN layer;
  • the second p-GaN layer, the first p-GaN layer, the GaN cap layer, and the In x Ga 1-x N quantum well layer are etched by an ICP (Inductive Coupled Plasma) etching technique. Etching to the end of the surface of the Al x Ga 1-x N barrier layer. In the ICP etching gas, the oxygen content volume ratio accounts for 2% to 70%, and the etching rate is controlled at 5 to 40 nm/min.
  • ICP Inductive Coupled Plasma
  • source 91 and drain 92 are fabricated on the source and drain regions.
  • the source and the drain are both ohmic contact electrodes, and the preparation conditions of the source 91 and the drain 92 are specifically: metal Ti/Al/Ni/Au, thickness 20 nm/130 nm/50 nm/150 nm, in a nitrogen atmosphere, Annealing at 890 ° C for 30 s.
  • a source lead electrode 911 and a drain lead electrode 921 are formed on the source 91 and the drain 92, respectively.
  • the preparation conditions of the source lead electrode 911 and the drain lead electrode 921 are specifically: metal Ni/Au, and the thickness is 50 nm/400 nm.
  • the quantum well layer is directly integrated in the epitaxial structure of the p-type gate-based enhancement type HEMT, and the composite light of electrons and holes is promoted, and the light emission can be radiated to the surface of the device and the body region, thereby accelerating the various defect states.
  • the release process of trapped electrons effectively suppresses the device current collapse effect, significantly reduces the on-resistance of the device during operation, improves dynamic characteristics, and improves device reliability.
  • the gate avalanche breakdown that may occur under the condition of large forward gate voltage has a safety warning function, that is, when the gate current is too large, a high intensity light is emitted.
  • the signal acts as an early warning and feedback to avoid the dangers caused by the gate voltage being higher than the breakdown threshold.
  • the first p-type nitride layer uses a low-temperature p-type Long process, the study found that low temperature is beneficial to the incorporation of Mg in the p-type layer, which helps the "quick opening" of the Mg source.
  • the enhanced HEMT device in the third embodiment of the present invention also includes a substrate 10, a nitride buffer layer 20, a nitride channel layer 30, an interposer layer 40, a nitride barrier layer 50, and a quantum. a well layer 60, a nitride cap layer 70, a first p-type nitride layer 81, a second p-type nitride layer 82, a source 91, a drain 92, and a gate 93, each of which has a material and a thickness
  • the embodiments are the same and will not be described again here.
  • the quantum well layer 60 covers only the nitride barrier layer under the gate electrode.
  • the quantum well layer 60 covers the gate and the source in addition to the nitride barrier layer under the gate.
  • a nitride barrier layer between the nitride barrier layer and the gate and the drain, the nitride cap layer 70 is disposed corresponding to the quantum well layer 60, and the first p-type nitride layer 81 and the second p-type The nitride layer 82 is disposed corresponding to the gate electrode 93.
  • the non-gate region (gate-source region and gate-drain region) also includes a quantum well structure, and through the current diffusion process, electrons and holes can also realize composite light emission in the non-gate region, thereby increasing the light-emitting region.
  • the area is more effective in suppressing the current collapse effect.
  • the quantum well layer covers the nitride barrier layer under the gate, between the gate and the source, and between the gate and the drain.
  • the quantum barrier layer can also be quantum.
  • the well layer may not completely cover the entire nitride barrier layer as long as the quantum well layer covers at least the nitride barrier layer under the gate.
  • the preparation method of the enhanced HEMT device in this embodiment is basically the same as the preparation method in the second embodiment, except that step 6).
  • etching the non-gate region uses the photoresist AZ5214 as a mask to perform plasma etching on the non-gate region:
  • the tungsten metal is etched by IBE (Ion Beam Etch);
  • the second p-GaN layer, the first p-GaN layer and a portion of the GaN cap layer are etched by a low-power ICP etching technique, and the etching gas is Cl 2 /BCl 3 , and the ICP plasma source power is set to 20 ⁇ 50W, the RF power is set to 5 ⁇ 15W, and the etch rate is controlled at 5-20nm/min.
  • the unetched GaN cap layer has a thickness of 1 to 10 nm.
  • the GaN cap layer of the source region and the drain region and the In x Ga 1-x N quantum well layer are etched by an IBE etching technique to expose the surface of the Al x Ga 1-x N barrier layer.
  • the etching technique of the non-gate region is not limited to the ICP etching technique in the above embodiments, and various other dry etching techniques may be employed in the present invention for trench gate etching.
  • the etching process not only the photoresist is used as a mask, but also other dielectric layers, such as SiO x (0 ⁇ x ⁇ 3), SiN x (0 ⁇ x ⁇ 3), etc., can realize the mask function. .
  • the second embodiment and the third embodiment are those in which the active region structure is an AlGaN/AlN/GaN heterojunction HEMT device.
  • the description will be made, but the present invention is not only applicable to an AlGaN/AlN/GaN heterojunction HEMT device having an active region structure, but also to a high electron mobility transistor having other active region structures, such as AlInN/AlN/GaN.
  • Heterojunction HEMT, AlInGaN/AlN/GaN heterojunction HEMT, high electron mobility transistor based on double channel heterojunction, and the like are not described in the present invention.
  • a quantum well and a p-type layer are grown by a selective epitaxial process to form a HEMT.
  • the HEMT may be an AlGaN/GaN heterojunction-based HEMT epitaxially grown by MOCVD, and its structure is as shown in FIG. 6f.
  • the AlGaN barrier layer has an Al composition x of 10% to 35%, a thickness of 5 to 40 nm, an AlN insertion layer of about 1 nm, and a GaN channel layer of 20 to 200 nm.
  • PECVD is used to grow silicon nitride as a mask layer. Growth conditions: substrate temperature is 200-350 ° C, reaction chamber pressure is 1700 mtorr, SiH 4 flow rate is 13-45 sccm, NH 3 flow rate is 10-90 sccm, N 2 purge flow rate is 1000 sccm, RF power is 67 W, LF power It is 53W.
  • the silicon nitride mask layer has a thickness of 50 to 300 nm. Thereafter, the gate region is opened by dry etching, as shown in FIG. 6a.
  • Quantum well In composition x is 0% ⁇ x ⁇ 50%, thickness is 0.3 ⁇ 8nm; GaN cap layer thickness is 0.3 ⁇ 20nm; p-GaN is divided into two layers, the first layer (p-GaN1) thickness is 1 ⁇ 50 nm, growth temperature is 700-1000 ° C, growth rate is 10-3000 nm / h, second layer (p-GaN 2) thickness is 5 ⁇ 300 nm, magnesium doping concentration range is 10 18 ⁇ 10 21 / cm 3 , As shown in Figure 6b.
  • Source and drain ohmic contact preparation After RIE etching is used to make the source and drain ohmic contacts open, the metal Ti/Al/Ni/Au is deposited to a thickness of 20 nm/130 nm/50 nm/150 nm, and the annealing conditions are 890 ° C, 30 s, nitrogen atmosphere. As shown in Figure 6c.
  • Ion implantation is performed by N ion implantation technology.
  • the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 12 ⁇ 10 14 /cm 2 , and the implantation depth is about 50-250 nm above the buffer layer, as shown in Fig. 6d.
  • the tungsten (W) metal is deposited by magnetron sputtering to a thickness of 50 to 200 nm as shown in Fig. 6e.
  • p-GaN is grown by the epitaxial epitaxial technique similar to that of the fourth embodiment, and device fabrication is completed.
  • the final device is shown in Figure 7.
  • the first embodiment to the fifth embodiment are all described by including a substrate, a buffer layer, an interposer layer, and a cap layer.
  • the substrate, the buffer layer, and the like may be included.
  • Some or all of the interposer layer and the cap layer are not included, and can also constitute the HEMT device in the present invention.
  • HEMTs are also suitable for HEMTs with complex structures such as passivation layers and/or field plates.
  • the invention directly integrates the quantum well structure in the gate region and the non-gate region in the enhanced HEMT device, so that when the device is in an on state, light emission can be realized at the same time, and the light emission can be effectively radiated in the gate-drain, gate-source
  • the surface area between the materials penetrates into the interior of the material, which can accelerate the release process of electrons captured by various defect states, thereby effectively suppressing the device current collapse effect;
  • the p-type gate after the integration of the quantum well can cause the gate avalanche breakdown phenomenon of the device under the condition of large forward gate voltage, and can play an early warning and feedback role through the illuminating signal, thereby improving the safety of the device operation;
  • the p-type nitride layer is divided into two layers, wherein the first p-type nitride layer adopts a low-temperature p-type growth process, which can realize the rapid incorporation of the Mg source and enhance the ability of the p-type gate to regulate the two-dimensional electron gas. .

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Abstract

L'invention concerne un dispositif HEMT à mode d'enrichissement inhibant l'effet de chute de courant, ainsi qu'un procédé de préparation de celui-ci. Le dispositif HEMT comprend une hétérostructure et une électrode de source (91), une électrode de drain (92) et une électrode de grille (93) qui sont connectées à l'hétérostructure. L'hétérostructure comprend un premier semi-conducteur servant de couche de canal (30) et un deuxième semi-conducteur servant de couche barrière (50), et elle est caractérisée en ce que le deuxième semi-conducteur est formé sur le premier semi-conducteur, en ce qu'un gaz d'électrons bidimensionnel est formé à l'intérieur de l'hétérostructure, en ce qu'une couche de puits quantique (60) et un troisième semi-conducteur sont successivement formés sur le deuxième semi-conducteur, en ce que les types de conduction du troisième semi-conducteur et du deuxième semi-conducteur sont différents, et en ce que l'électrode de grille (93) établit un contact électrique avec le troisième semi-conducteur. Une structure de puits quantique est directement intégrée dans une région de grille et une région de non-grille, dans un dispositif HEMT à mode d'enrichissement, de sorte que le dispositif peut émettre de la lumière tout en étant dans un état sous tension. La lumière émise peut être efficacement rayonnée sur une région de surface entre une grille-drain et une grille-source et atteindre l'intérieur d'un matériau, de sorte que le processus de libération des électrons piégés par divers états de défauts peut être accéléré, ce qui permet d'inhiber efficacement l'effet de chute de courant du dispositif.
PCT/CN2015/099391 2015-11-24 2015-12-29 Dispositif hemt à mode d'enrichissement empêchant l'effet de chute de courant et son procédé de préparation WO2017088253A1 (fr)

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CN111293173A (zh) * 2018-12-10 2020-06-16 黄山学院 一种硅基氮化镓增强型hemt器件及其制备方法
CN113451128A (zh) * 2021-06-29 2021-09-28 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113451129A (zh) * 2021-06-29 2021-09-28 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113628964A (zh) * 2021-08-04 2021-11-09 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN113628962A (zh) * 2021-08-05 2021-11-09 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
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CN112635557A (zh) * 2020-12-25 2021-04-09 广东省科学院半导体研究所 一种堆叠栅极结构的GaN基常关型HEMT器件
WO2022217436A1 (fr) * 2021-04-12 2022-10-20 Innoscience (Suzhou) Technology Co., Ltd. Dispositif à semi-conducteur et son procédé de fabrication
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CN111293173A (zh) * 2018-12-10 2020-06-16 黄山学院 一种硅基氮化镓增强型hemt器件及其制备方法
CN113451128A (zh) * 2021-06-29 2021-09-28 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113451129A (zh) * 2021-06-29 2021-09-28 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113451129B (zh) * 2021-06-29 2022-05-10 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113451128B (zh) * 2021-06-29 2022-05-10 厦门市三安集成电路有限公司 一种高电子迁移率晶体管及制备方法
CN113628964A (zh) * 2021-08-04 2021-11-09 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN113628964B (zh) * 2021-08-04 2024-03-12 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN113628962A (zh) * 2021-08-05 2021-11-09 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN113628962B (zh) * 2021-08-05 2024-03-08 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN116314321A (zh) * 2023-03-24 2023-06-23 厦门市三安集成电路有限公司 一种hemt射频器件及其制作方法

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