CN113611731A - 一种GaN基增强型垂直HEMT器件及其制备方法 - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 91
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 22
- 238000002161 passivation Methods 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 230000005669 field effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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Abstract
本发明提供了一种GaN基增强型垂直HEMT器件及其制备方法，GaN基增强型垂直HEMT器件的结构从下至上依次包括漏极、衬底、漂移区、垂直沟道阻挡层、沟道层、势垒层、钝化层、沟槽栅和源极。GaN沟道层和其上侧的AlGaN势垒层以及其下方的AlxGa1‑xN垂直沟道阻挡层形成双异质结结构，该结构通过GaN/AlGaN异质结构在垂直沟道方向形成势垒层，从而在关态条件下阻断载流子在垂直方向的输运，进而关断沟道，实现增强型特性。该结构可有效避免传统的Mg掺杂的p‑GaN阻挡层带来的负面影响，设计的器件具有低导通电阻、高漏极电流密度和高阈值电压的显著特性。
Description
技术领域
本发明属于半导体器件技术领域，具体涉及一种GaN基增强型垂直HEMT器件及其制备方法。
背景技术
宽禁带半导体材料凭借其大禁带宽度和高键合能等优势在高频大功率领域和光电领域发挥着越来越重要的作用。横向结构的GaN高电子迁移率晶体管(HEMT)是其在功率器件应用领域的主要结构，其核心是AlGaN/GaN异质结。基于GaN的垂直功率场效应管和传统的GaN横向器件相比，具有面积效率高、热阻更低、更易封装、电场集边效应小、导通电阻更低等优势。
为了减轻电流崩塌效应并提高器件的可靠性，基于GaN的垂直HEMT的高场区一般埋置于器件体内以避免栅极边缘的表面电弧。电流孔径垂直电子晶体管(CAVET)和沟槽栅金属氧化物半导体场效应晶体管(MOSFET)是两种常见的GaN基垂直场效应晶体管。而这两种传统的GaN垂直场效应晶体管均需采用Mg掺杂的p-GaN作为其沟道阻挡层或势垒层。在制作p-GaN层通常可采用两种方法，第一种是刻蚀之后再生长，第二种是Mg离子注入。这两种方法的刻蚀损伤较大，工艺极为复杂，Mg激活率较低，且引入的缺陷态较高，因而难以制作高性能、高可靠的GaN垂直器件。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种GaN基增强型垂直HEMT器件及其制备方法。本发明要解决的技术问题通过以下技术方案实现：
第一方面，本发明提供的一种GaN基增强型垂直HEMT器件包括：漏极1、衬底2、漂移区3、垂直沟道阻挡层4、沟道层5、槽栅6、势垒层7，钝化层8以及源极9，槽栅6内包括槽栅金属61以及槽栅介质62，槽栅介质62包围槽栅金属，槽栅介质62与钝化层8相连，漏极1、衬底2、漂移区3、垂直沟道阻挡层4自下而上依次相触，槽栅6为沟槽栅，从势垒层7的中心位置开始，开槽范围自上而下从势垒层7、穿过沟道层直至垂直沟道阻挡层4底端，钝化层8位于势垒层7之上，与势垒层7的上表面相触，钝化层8与势垒层7边沿重合，源极9截面呈倒C型，源极9位于钝化层8之上，钝化层8以及势垒层7的边沿分别与源极9边沿对应相触，沟道层5和其上侧的势垒层7以及其下方的垂直沟道阻挡层4形成双异质结结构，源极9穿过势垒层7和沟道层5形成欧姆接触。
可选的，槽栅介质62与钝化层8的材质相同，槽栅介质62为厚度100nm的SiN或SiO2。
可选的，势垒层7为厚度30nm的AlxGa1-xN；其中，x＝0.1～0.5。
其中，沟道层为厚度50～500nm的GaN。
其中，漂移区3为厚度500～5000nm的n-GaN。
其中，衬底2的材质为n+-GaN。
其中，的垂直沟道阻挡层4为厚度为50～300nm的AlxGa1-xN，其中x的含量为2％～30％。
第二方面，本发明提供的一种GaN基增强型垂直HEMT器件的制备方法包括：
步骤1：在n+-GaN衬底上外延生长n-GaN漂移区；
步骤2：在n-GaN漂移区上外延生长AlxGa1-xN垂直沟道阻挡层；
步骤3：在垂直沟道阻挡层表面外延生长本征GaN沟道层；
步骤4：在本征GaN沟道层的表面外延生长AlGaN势垒层；
步骤5：在AlGaN势垒层表面上刻蚀沟槽，开槽范围自上而下从势垒层、穿过沟道层直至垂直沟道阻挡层底端；
步骤6：在AlGaN势垒层和沟槽表面沉积SiN或SiO2，作为与钝化层相连的槽栅介质；
步骤7：在沟槽内沉积金属形成栅电极；
步骤8：在沟槽表面外延生长SiN或SiO2钝化层；
步骤9：在钝化层表面的预定的欧姆区域进行介质开孔刻蚀和AlGaN刻蚀直至GaN沟道层，在GaN沟道层形成一个刻蚀的浅槽；
步骤10：在欧姆区域进行源极金属沉积和退火，以使GaN沟道层与沉积的金属形成欧姆接触；
步骤11：在n+-GaN衬底背面刻蚀形成漏区，在该漏区区域沉积欧姆接触的金属并退火形成漏极。
本发明提供了一种GaN基增强型垂直HEMT器件及制备方法，其结构从下至上依次包括漏极、衬底、漂移区、垂直沟道阻挡层、沟道层、势垒层、钝化层、槽栅和源极。器件GaN沟道层和其上侧的AlGaN势垒层以及其下方的AlxGa1-xN垂直沟道阻挡层形成双异质结结构，该结构通过垂直GaN/AlGaN异质结构在垂直沟道方向形成势垒层，从而在关态条件下阻断载流子在垂直方向的输运，进而关断沟道，实现增强型特性。该结构可有效避免传统的Mg掺杂的p-GaN阻挡层带来的负面影响，设计的器件具有低通阻(Ron)、高漏极电流密度和高阈值电压(Vth>3V)的显著特性。
本发明提出一种GaN基增强型垂直HEMT器件的制备方法，通过在漂移区上方依次生长AlxGa1-xN垂直沟道阻挡层、GaN沟道层、AlGaN势垒层，三者形成双异质结结构。与传统的p-GaN增强型HEMT器件相比，本发明利用采用AlxGa1-xN取代了传统的不稳定的Mg掺杂p-GaN作为垂直沟道阻挡层，避免了Mg掺杂p-GaN阻挡层所带来的一系列问题，同时有效提高了漏极电流密度和正向阈值电压。并且源极通过开槽穿过势垒层与沟道层形成欧姆接触，可以充分利用二维电子气高迁移率的优势，降低源极导通电阻。同时本发明工艺过程比较简单，和目前传统的GaN HEMT工艺兼容。
以下将结合附图及实施例对本发明做进一步详细说明。
附图说明
图1是本发明实施例提供的一种GaN基增强型垂直HEMT器件的结构示意图；
图2是本发明提供的GaN基增强型垂直HEMT器件的转移特性曲线图；
图3是本发明提供的GaN基增强型垂直HEMT器件的输出特性曲线图；
图4是本发明实施例提供的一种GaN基增强型垂直HEMT器件的制备方法的流程图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
如图1所示，本发明提供的一种GaN基增强型垂直HEMT器件包括：漏极1、衬底2、漂移区3、垂直沟道阻挡层4、沟道层5、槽栅6、势垒层7、钝化层8以及源极9，槽栅6内包括槽栅金属61以及槽栅介质62，槽栅介质62包围槽栅金属，槽栅介质62与钝化层8相连，漏极1、衬底2、漂移区3、垂直沟道阻挡层4自下而上依次相触，槽栅6为沟槽栅，从势垒层7的中心位置开始，开槽范围自上而下从势垒层7、穿过沟道层直至垂直沟道阻挡层4底端，4，钝化层8位于势垒层7之上，与势垒层7的上表面相触，钝化层8与势垒层7左右边沿重合，源极9截面呈倒C型，源极9位于钝化层8之上，钝化层8以及势垒层7的边沿分别与源极9边沿对应相触，沟道层和其上侧的势垒层7以及其下方的垂直沟道阻挡层4形成双异质结结构，源极9穿过势垒层7和沟道层5形成欧姆接触。
作为本发明一种可选的实施方式，槽栅介质62与钝化层8的材质相同，槽栅介质62为厚度100nm的SiN或SiO2。
作为本发明一种可选的实施方式，势垒层7为厚度30nm的AlxGa1-xN；其中，x＝0.1～0.5。
作为本发明一种可选的实施方式，沟道层为厚度50～500nm的GaN。
作为本发明一种可选的实施方式，漂移区3为厚度500～5000nm的n-GaN。
作为本发明一种可选的实施方式，衬底2的材质为n+-GaN。
作为本发明一种可选的实施方式，的源极9的长度、源极9与槽栅6之间的距离、沟槽栅宽度分别设置为0.5、1.1和0.8μm。
作为本发明一种可选的实施方式，的垂直沟道阻挡层4为厚度为50～300nm的AlxGa1-xN，其中x的含量为2％～30％。
参考图2以及图3，图2是本发明提供的GaN基增强型垂直HEMT器件的转移特性曲线图，横轴为VDS，纵轴为z转移特性，该曲线条件为VDS＝10V，Vth＝5.4V。图3是本发明提供的GaN基增强型垂直HEMT器件的输出特性曲线图，VGS＝0～9V。
本发明提供了一种GaN基增强型垂直HEMT器件，其结构从下至上依次包括漏极、衬底、漂移区、垂直沟道阻挡层、沟道层、势垒层、钝化层、槽栅和源极。所述器件GaN沟道层和其上侧的AlGaN势垒层以及其下方的AlxGa1-xN垂直沟道阻挡层形成双异质结结构，该结构通过垂直GaN/AlGaN异质结构在垂直沟道方向形成势垒层，从而在关态条件下阻断载流子在垂直方向的输运，进而关断沟道，实现增强型特性。该结构可有效避免传统的Mg掺杂的p-GaN阻挡层带来的负面影响，设计的器件具有低通阻(Ron)、高漏极电流密度和高阈值电压(Vth>3V)的显著特性。
如图4所示，本发明提供的一种双异质结基沟槽栅增强型垂直HEMT器件的制备方法包括：
步骤1：在n+-GaN衬底上外延生长n-GaN漂移区；
步骤2：在n-GaN漂移区上外延生长AlxGa1-xN垂直沟道阻挡层；
步骤3：在垂直沟道阻挡层表面外延生长本征GaN沟道层；
步骤4：在本征GaN沟道层的表面外延生长AlGaN势垒层；
步骤5：在AlGaN势垒层(表面上刻蚀沟槽，开槽范围自上而下从势垒层、穿过沟道层直至垂直沟道阻挡层底端；
步骤6：在所述AlGaN势垒层和沟槽表面沉积SiN或SiO2，作为与钝化层相连槽栅介质；
步骤7：在所述沟槽内沉积金属形成栅电极；
步骤8：在所述沟槽表面外延生长SiN或SiO2钝化层；
步骤9：在所述钝化层表面的预定的欧姆区域进行介质开孔刻蚀和AlGaN刻蚀直至GaN沟道层，在GaN沟道层形成一个刻蚀的浅槽；
步骤10：在欧姆区域进行源极金属沉积和退火，以使GaN沟道层与沉积的金属形成欧姆接触；
步骤11：在所述n+-GaN衬底背面刻蚀形成漏区，在该漏区区域沉积欧姆接触的金属并退火形成漏极。
本发明提出的制备方法通过在漂移区上方依次生长AlxGa1-xN垂直沟道阻挡层、GaN沟道层、AlGaN势垒层，三者形成双异质结结构。与传统的p-GaN增强型HEMT器件相比，本发明利用采用AlxGa1-xN取代了传统的不稳定的Mg掺杂p-GaN作为垂直沟道阻挡层，避免了Mg掺杂p-GaN阻挡层所带来的一系列问题，同时有效提高了漏极电流密度和正向阈值电压。并且源极通过开槽穿过势垒层与沟道层形成欧姆接触，可以充分利用二维电子气高迁移率的优势，降低源极导通电阻。同时本发明工艺过程比较简单，和目前传统的GaN HEMT工艺兼容。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。
Claims (8)
1.一种GaN基增强型垂直HEMT器件，其特征在于，包括：漏极(1)、衬底(2)、漂移区(3)、垂直沟道阻挡层(4)、沟道层(5)、槽栅(6)、势垒层(7)，钝化层(8)以及源极(9)，所述槽栅(6)内包括槽栅金属(61)以及槽栅介质(62)，所述槽栅介质(62)包围所述槽栅金属，所述槽栅介质(62)与所述钝化层(8)相连，所述漏极(1)、衬底(2)、漂移区(3)、垂直沟道阻挡层(4)自下而上依次相触，所述槽栅(6)为沟槽栅，从势垒层(7)的中心位置开始，开槽范围自上而下从势垒层(7)、穿过沟道层直至垂直沟道阻挡层(4)底端，所述钝化层(8)位于所述势垒层(7)之上，与所述势垒层(7)的上表面相触，所述钝化层(8)与所述势垒层(7)边沿重合，所述源极(9)截面呈倒C型，所述源极(9)位于所述钝化层(8)之上，所述钝化层(8)以及所述势垒层(7)的边沿分别与源极(9)边沿对应相触，所述沟道层(5)和其上侧的势垒层(7)以及其下方的垂直沟道阻挡层(4)形成双异质结结构，所述源极(9)穿过势垒层(7)和沟道层(5)形成欧姆接触。
2.根据权利要求1所述的器件，其特征在于，所述槽栅介质(62)与所述钝化层(8)的材质相同，槽栅介质(62)为厚度100nm的SiN或SiO2。
3.根据权利要求1所述的器件，其特征在于，势垒层(7)为厚度30nm的AlxGa1-xN；其中，x＝0.1～0.5。
4.根据权利要求1所述的器件，其特征在于，沟道层为厚度50～500nm的GaN。
5.根据权利要求1所述的器件，其特征在于，所述漂移区(3)为厚度500～5000nm的n-GaN。
6.根据权利要求1所述的器件，其特征在于，所述衬底(2)的材质为n+-GaN。
7.根据权利要求1所述的器件，其特征在于，所述的垂直沟道阻挡层(4)为厚度为50～300nm的AlxGa1-xN，其中x的含量为2％～30％。
8.一种GaN基增强型垂直HEMT器件的制备方法，其特征在于，所述制备方法包括：
步骤1：在n+-GaN衬底上外延生长n-GaN漂移区；
步骤2：在n-GaN漂移区上外延生长AlxGa1-xN垂直沟道阻挡层；
步骤3：在垂直沟道阻挡层表面外延生长本征GaN沟道层；
步骤4：在本征GaN沟道层的表面外延生长AlGaN势垒层；
步骤5：在AlGaN势垒层表面上刻蚀沟槽，开槽范围自上而下从势垒层、穿过沟道层直至垂直沟道阻挡层底端；
步骤6：在所述AlGaN势垒层和沟槽表面沉积SiN或SiO2，作为与钝化层相连的槽栅介质；
步骤7：在所述沟槽内沉积金属形成栅电极；
步骤8：在所述沟槽表面外延生长SiN或SiO2钝化层；
步骤9：在所述钝化层表面的预定的欧姆区域进行介质开孔刻蚀和AlGaN刻蚀直至GaN沟道层，在GaN沟道层形成一个刻蚀的浅槽；
步骤10：在欧姆区域进行源极金属沉积和退火，以使GaN沟道层与沉积的金属形成欧姆接触；
步骤11：在所述n+-GaN衬底背面刻蚀形成漏区，在该漏区区域沉积欧姆接触的金属并退火形成漏极。
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