CN110190116B - 一种高阈值电压常关型高电子迁移率晶体管及其制备方法 - Google Patents

一种高阈值电压常关型高电子迁移率晶体管及其制备方法 Download PDF

Info

Publication number
CN110190116B
CN110190116B CN201910361958.6A CN201910361958A CN110190116B CN 110190116 B CN110190116 B CN 110190116B CN 201910361958 A CN201910361958 A CN 201910361958A CN 110190116 B CN110190116 B CN 110190116B
Authority
CN
China
Prior art keywords
layer
electrode
grid
metal
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910361958.6A
Other languages
English (en)
Other versions
CN110190116A (zh
Inventor
黄火林
孙仲豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dalian University of Technology
Original Assignee
Dalian University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dalian University of Technology filed Critical Dalian University of Technology
Priority to CN201910361958.6A priority Critical patent/CN110190116B/zh
Publication of CN110190116A publication Critical patent/CN110190116A/zh
Priority to US17/594,636 priority patent/US20220209000A1/en
Priority to PCT/CN2020/087347 priority patent/WO2020221222A1/zh
Application granted granted Critical
Publication of CN110190116B publication Critical patent/CN110190116B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H01L21/28593—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Abstract

一种高阈值电压常关型高电子迁移率晶体管及其制备方法，属于半导体器件技术领域。技术方案：在衬底上依次生长成核层和外延层，外延层上方为势垒层、源极和漏极，势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，栅极盖帽层上方为经表面等离子体氧化技术处理形成氧化物介质层或者直接沉积单层或者多重栅介质插入层，栅介质插入层上方为栅极，栅极与钝化层接触，在钝化层上、栅极向漏极方向延伸有场板。有益效果:本发明实现常关型器件类型的同时能保持大的导通电流密度；通过提高势垒层导带位置从而提高该常关型器件的栅极耐压和阈值电压。

Description

一种高阈值电压常关型高电子迁移率晶体管及其制备方法
技术领域
本发明属于半导体器件技术领域，尤其涉及一种高阈值电压常关型高电子迁移率晶体管及其制备方法。
背景技术
继第一代半导体材料(Ge、Si等)与第二代化合物半导体材料(GaAs、InP等)之后，氮化镓(GaN)作为第三代新型宽禁带半导体材料的重要代表得到迅速发展，并成为功率半导体领域研究的前沿和热点。GaN基(以GaN为主，包含GaN、AlN、InN以及它们的成分组合等)半导体材料具有大的禁带宽度、高的电子饱和速度以及耐高温高压、抗辐照等优良特性，可以弥补第一、二代半导体材料的不足，在功率开关器件和微波射频领域具有广泛的应用前景。另外，GaN基异质结(以AlGaN/GaN为代表)界面的自发极化和压电极化电荷将诱导产生高密度的二维电子气(2DEG)(～1013cm-2)，由于受输运维数限制以及材料无需故意掺杂，该2DEG沟道具有明显增大的电子迁移率(～2000cm2V-1s-1)。这一特性使GaN基异质结构在研制高性能高电子迁移率晶体管(HEMT)方面具有明显的优势，特别是在1000V以下的中低压芯片市场具有明显的技术优势。
国内外在GaN基功率器件领域开展研究已经有超过20年的时间，目前市场上已经有少量200V以下的GaN基器件产品，其应用主要是在低压射频和消费类电源转换领域。但是在400～1000V范围，GaN技术不够成熟，其产品还未受市场检验，主要原因有两方面。一方面是器件后端封装、匹配电路以及可靠性验证方面需要进一步深入研究；另一方面是常关型器件设计和研究距离向市场推广还有较大距离。功率开关器件按照器件导通时是否需要在栅极施加开启偏压分为常开型和常关型两种类型。常关型功率开关器件在栅极不施加偏压情况下，器件即处于关断状态，相对于常开型类型，常关型器件在实际应用中具有更安全、节能、简化电路设计等方面的优势，因此具有更加重要的研究价值和更加广阔的应用市场。本专利申请即针对常关型GaN基材料功率器件进行结构创新和技术制作。
目前实现HEMT功率器件的常关型操作有多种技术，主要有栅极势垒层刻蚀形成凹槽栅、氟离子注入形成氟化栅以及栅极生长p型盖帽层三种方案。凹槽栅方案通过部分或者全部刻蚀掉AlGaN势垒层来削弱或者直接切断2DEG，从而获得常关型操作，该方案要求精确刻蚀势垒层，对于大面积器件，栅极刻蚀深度均匀性较难控制；氟离子注入栅极方案利用带负电荷的氟离子排斥2DEG可以达到常关型操作目的，但在应用推广过程中，器件中氟离子分布的热稳定性和性能可靠性问题难以克服；栅极p型盖帽层是个较好的技术方案，该技术保留良好的2DEG沟道，利用其附加内建电场将2DEG沟道界面的导带提升到费米能级上方，从而获得常关型操作，该技术方案能获得较高的导通电流密度，适合产业化推广，目前主要存在的问题是栅耐压和阈值电压较小。因此，针对该问题，如何对器件结构进行创新设计，引入新型加工技术，从而提高p型盖帽层方案中器件耐压和阈值电压，是业内急需解决的技术难题。
发明内容
为了解决上述现有技术中存在的问题，本发明提供一种高阈值电压常关型高电子迁移率晶体管及其制备方法，该晶体管实现常关型器件类型的同时能保持大的导通电流密度，在此基础上进一步增大的器件栅极耐压和阈值电压。
技术方案如下：
一种高阈值电压常关型高电子迁移率晶体管，包括：衬底、成核层、外延层、势垒层、钝化层、栅极盖帽层、复合栅介质插入层、栅极、源极和漏极，在所述衬底上依次生长成核层和外延层，所述外延层上方为势垒层、源极和漏极，所述势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，所述势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，所述栅极盖帽层上方为复合栅介质插入层，所述复合栅介质插入层上方为栅极，所述栅极与所述钝化层接触，在所述钝化层上、所述栅极向所述漏极方向延伸有场板。
进一步的，所述衬底是硅、蓝宝石、碳化硅、金刚石、GaN自支撑衬底中的任意一种；所述成核层是AlN或者AlGaN超晶格；所述外延层是GaN或者GaAs；所述势垒层是AlGaN、InAlN、AlN、AlGaAs中的任意一种；所述钝化层是SiO2、Si3N4或者二者的复合结构。
进一步的，所述栅极盖帽层是p-GaN或者p-InGaN或者p-AlGaN。
进一步的，所述复合栅介质插入层是氧化镓、二氧化硅、氮化硅、氧化铝、氧化铪中的任意材料形成的单层结构、或者是由上述材料任意组合的复合多重结构。
本发明还包括一种高阈值电压常关型高电子迁移率晶体管制备方法，步骤如下：
S1、晶片生长；
S2、外延层结构刻蚀；
S3、源、漏电极制作；
S4、栅介质插入层制备；
S5、栅电极制作。
进一步的，步骤S1具体步骤为：
采用金属有机物化学气相沉积或分子束外延方法在衬底上依次生长成核层、外延层、势垒层、栅极盖帽层；
或者
采用MOCVD设备衬底上依次成核层、外延层、势垒层、栅极盖帽层。
进一步的，步骤S2具体步骤为：
利用半导体光刻法和刻蚀法制作器件台面，通过半导体刻蚀方法对表面刻蚀，实现台面隔离；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的栅极盖帽层；
或者
将样品均匀旋涂光刻胶；样品放置在热板上加热，进行软烘；把样品放置在曝光机中持续曝光；在显影液中进行显影；在热板上加热坚膜；通过Cl基等离子体ICP刻蚀方法，刻蚀外延层结构，形成台面隔离，然后样品通过丙酮溶液清洗去胶；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；重复该步骤，刻蚀掉栅极区域外面的盖帽层，形成栅极盖帽层。
进一步的，步骤S3具体步骤为：
通过半导体光刻法定义出源、漏极所需区域，并通过金属沉积法沉积器件的源、漏极金属，通过高温退火，使复合金属结构变为合金，形成欧姆接触；利用等离子体增强化学气相沉积法、低压化学气相沉积法、磁控溅射法、电子束蒸发法中的任意一种方法进行沉积，形成器件表面钝化层；
或者
通过半导体光刻法定义出源、漏极所需区域，通过电子束蒸发法沉积器件的源、漏极金属，然后样品在丙酮溶液中剥离、清洗去胶；通过在氮气高温环境中退火，使复合金属结构变为合金，形成欧姆接触；利用PECVD技术沉积法进行沉积，形成器件表面钝化层。
进一步的，步骤S4具体步骤为：
通过半导体光刻法定义出栅极区域，对栅极盖帽层进行表面氧化，处理形成栅介质插入层；或者采用PECVD、LPCVD、MOCVD、ALD、磁控溅射法中的任意方法进行沉积，形成单层或者复合多重栅介质插入层；
或者
通过半导体光刻法定义出栅极区域，对栅极盖帽层表面进行低功率氧离子预处理，后采用LPCVD进行沉积，形成栅极介质插入层。
进一步的，步骤S5具体步骤为：
通过半导体光刻法定义出栅极和场板区域，通过金属沉积法沉积器件的栅极金属和向漏极延伸的场板金属，最后在器件表面沉积钝化层，然后采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构；
或者
通过半导体光刻法定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，然后样品在丙酮溶液中剥离、清洗去胶；在器件表面采用PECVD沉积钝化层，采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积电极金属，得到最后器件结构。
本发明的有益效果是：
本发明所述的高阈值电压常关型高电子迁移率晶体管及其制备方法实现常关型器件类型的同时能保持大的导通电流密度；采用对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理，形成栅极氧化物介质层或者直接沉积栅介质插入层或者形成多重栅介质插入层，通过提高势垒层导带位置从而提高该常关型器件的栅极耐压和阈值电压。
附图说明
图1是本发明高阈值电压常关型HEMT器件截面示意图；
图2是本发明器件制作工艺流程示例图a；
图3是本发明器件制作工艺流程示例图b；
图4是本发明器件制作工艺流程示例图c；
图5是本发明器件制作工艺流程示例图d；
图6是本发明器件制作工艺流程示例图e；
图7是本发明器件制作工艺流程示例图f；
图8是有、无复合栅介质插入层技术方案中器件能带对比示意图；
图9是有、无复合栅介质插入层技术方案中器件阈值电压特性对比示意图。
具体实施方式
下面结合附图1-9对高阈值电压常关型高电子迁移率晶体管及其制备方法做进一步说明。
本专利申请针对栅极生长p型盖帽层方案，采用对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理形成栅极氧化物介质层或者直接沉积栅介质插入层或者形成多重栅介质插入层，如图1所示，通过提高势垒层导带位置从而提高该常关型器件的栅极耐压和阈值电压。栅极p型盖帽层在产业界目前是个能较好实现常关型器件的技术方案，该技术并未损伤2DEG沟道，因此器件的导通电流密度(或者导通电阻)特性并未下降。而p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层形成的附加内建电场将2DEG沟道界面的导带提升到费米能级上方，从而获得常关型操作，但是阈值电压一般只有1V左右，栅极最高耐压一般小于10V。本专利申请在栅极盖帽层上方引入单层或者复合多重栅介质插入层后，将进一步提升势垒层和2DEG沟道界面的导带位置，获得明显增大的栅极耐压(＞20V)和阈值电压(＞2V)。
图1是本专利申请提出的高阈值电压常关型HEMT器件截面示意图，栅金属电极和p型盖帽层之间引入栅介质插入层为其主要特征。
本专利申请所提器件的基本结构说明如下：底部为衬底，可以是硅、蓝宝石、碳化硅、金刚石或者GaN自支撑衬底等；衬底上方为AlN或者AlGaN超晶格成核层；成核层上方为GaN或者GaAs外延层；外延层上方为AlGaN、InAlN、AlN或AlGaAs势垒层，势垒层和外延层形成异质结结构，该界面由极化电荷诱导产生二维电子气(2DEG)；势垒层上方是二氧化硅(SiO2)、氮化硅(Si3N4)或者它们的复合结构形成钝化层；栅区势垒层上方分别是p-GaN或者p-InGaN或者p-AlGaN盖帽层以及氧化镓(Ga2O3)、二氧化硅(SiO2)、氮化硅(Si3N4)、氧化铝(Al2O3)或者氧化铪(HfO2)等各种材料形成单层或者复合多重栅介质插入层；与外延层接触的源极、漏极，以及栅介质插入层上方的栅极和向漏极延伸的场板。
本专利申请所提器件结构方案的优势是实现常关型器件类型的同时能保持大的导通电流密度，在此基础上进一步增大的器件栅极耐压和阈值电压。
实施例1
本专利申请具体实施过程如下：
步骤①：晶片生长。
采用金属有机物化学气相沉积(MOCVD)或分子束外延(MBE)等半导体材料生长技术依次在硅、蓝宝石、碳化硅、金刚石或者GaN自支撑衬底上依次生长AlN或者AlGaN超晶格成核层、2～10μm的GaN或者GaAs外延层、5～100nm的AlGaN、InAlN、AlN或AlGaAs势垒层(其中Al组分为0.05～0.3)、30～100nm的p-GaN或者p-InGaN或者p-AlGaN栅极盖帽层，如图2、图3所示。
步骤②：外延层结构刻蚀。
利用半导体光刻技术和刻蚀技术制作器件台面，通过如基于Cl基气体的感应耦合等离子体(ICP)或者反应离子刻蚀(RIE)等半导体刻蚀技术，将表面刻蚀300～800nm，实现台面隔离。重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的p型盖帽层，如图4所示。其中半导体光刻技术包含完整的匀胶、软烘、曝光、显影、坚膜等步骤。
步骤③：源、漏电极制作。
通过步骤②所述的半导体光刻技术定义出源、漏极所需区域，并通过如磁控溅射、电子束蒸发等金属沉积技术沉积器件的源、漏极金属，并且通过高温退火，使复合金属结构变为合金，形成欧姆接触。利用等离子体增强化学气相沉积法(PECVD)、低压化学气相沉积法(LPCVD)、磁控溅射法或者电子束蒸发法等技术沉积SiO2、Si3N4或者它们的复合结构，形成器件表面钝化层，如图5所示。
步骤④：栅介质插入层制备。
通过步骤②所述的半导体光刻技术定义出栅极区域，对p-GaN(或p-InGaN或者p-AlGaN)栅极盖帽层进行表面氧化技术处理形成Ga2O3介质层，或者采用PECVD、LPCVD、MOCVD、原子层沉积(ALD)或者磁控溅射等技术直接沉积SiO2、Si3N4、氧化铝(Al2O3)或者氧化铪(HfO2)等单层或者复合多重介质插入层，如图6所示。
步骤⑤：栅电极制作。
通过步骤②所述的半导体光刻技术定义出栅极和场板区域，步骤③所述的金属沉积技术沉积器件的栅极金属和向漏极延伸的场板金属，如图7所示。最后在器件表面沉积300～5000nm的厚钝化层，然后采用步骤②所述的半导体光刻技术定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构。
实施例2
本专利申请具体实施过程如下(详细参数和步骤)：
步骤①：GaN结构外延生长。
采用MOCVD设备在6英寸p型Si衬底上依次生长100nm的AlGaN超晶格成核层、2μm的GaN外延层、20nm的AlGaN势垒层(Al组分为0.25)、50nm的p-GaN盖帽层。器件结构和尺寸设计如下：器件的源极和栅极距离为2μm，栅极长为3μm、宽为200μm，栅极向漏极延伸场板长为1μm、栅极和漏极距离为10μm，各电极面积为200×200μm2。
步骤②：外延层结构刻蚀。
利用半导体光刻技术，其具体过程为：
(1)将样品以4000r/min的速率持续30s均匀旋涂AZ5214光刻胶；
(2)将样品放置在100℃的热板上加热进行软烘90s；
(3)把样品放置在光强为7mW/cm2的曝光机中持续曝光20s；
(4)在显影液中显影45s；
(5)在105℃的热板上加热坚膜60s。
通过Cl基等离子体ICP刻蚀技术，选择150W电源功率，刻蚀500nm深度的外延层结构形成台面隔离，然后样品通过丙酮溶液清洗去胶。重复该步骤，选择30W的较低电源功率，在源、漏极区域刻蚀掉20nm势垒层形成凹槽；重复该步骤，选择30W的较低电源功率，刻蚀掉栅极区域外面的p-GaN，形成栅极盖帽层。
步骤③：源、漏电极制作。
通过步骤②所述的半导体光刻技术定义出源、漏极所需区域，通过电子束蒸发技术沉积器件的源漏极金属，即Ti/Al/Ni/Au(20/100/45/55nm)，然后样品在丙酮溶液中剥离、清洗去胶。通过在875℃的氮气高温环境中退火30s，使复合金属结构变为合金，形成欧姆接触。利用PECVD技术沉积200nm的SiO2钝化层。
步骤④：栅介质插入层制备。
通过步骤②所述的半导体光刻技术定义出栅极区域，对p-GaN栅极盖帽层表面进行低功率(30W)氧离子预处理，后采用LPCVD技术沉积5nm厚度的Si3N4栅极介质插入层。
步骤⑤：栅电极制作。
通过步骤②所述的半导体光刻技术定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，即Ni/Au(100/100nm)，然后样品在丙酮溶液中剥离、清洗去胶。最后在器件表面采用PECVD技术沉积1000nm的SiO2钝化层，然后采用步骤②所述的半导体光刻技术定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积1500nm厚度的Al金属，得到最后器件结构。
图8和图9为采用本实施例器件结构参数获得的，在有、无栅介质插入层技术方案中的器件能带对比和阈值电压特性对比结果。由图中可以看出，引入栅介质插入层可以明显提高势垒层带阶和导带位置，从而提高常关型器件的栅极耐压和阈值电压，器件阈值电压从1.5V提高到4.5V，同时保留器件良好的导通电流等级。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，根据本发明的技术方案及其发明构思加以等同替换或改变，都应涵盖在本发明的保护范围之内。本发明所述的实施例，并非对本发明内容进行限定，其他具有2DEG的异质结HEMT器件都适用于本发明提案涉及范围。任何其他钝化层生长(包括不同的生长技术、不同的钝化层组合或者也可直接省略钝化工艺步骤)、欧姆接触电极制作工艺(包括不同的金属选择、沉积方法、退火条件)或者台面刻蚀工艺，在基于实现本发明所述具有p型栅极盖帽层表面进行等离子体处理形成介质层或者额外引入单层或多重复合介质插入层结构特点的常关型HEMT器件基本功能目的下，都适用于本发明提案涉及范围。同样地，材料结构参数和电极尺寸的改变，或等同替换等，都应涵盖在本发明的保护范围之内。

Claims (4)

1.一种高阈值电压常关型高电子迁移率晶体管，其特征在于，包括：衬底、成核层、外延层、势垒层、钝化层、栅极盖帽层、复合栅介质插入层、栅极、源极和漏极，在所述衬底上依次生长成核层和外延层，所述外延层上方为势垒层、源极和漏极，所述势垒层和外延层形成异质结结构，二者接触界面由极化电荷诱导产生二维电子气，所述势垒层上方为钝化层，栅区势垒层上方为栅极盖帽层，所述栅极盖帽层上方为复合栅介质插入层，所述复合栅介质插入层完全覆盖栅极盖帽层，且所述复合栅介质插入层不与钝化层接触；所述复合栅介质插入层上方为栅极，所述栅极与所述钝化层接触，在所述钝化层上、所述栅极向所述漏极方向延伸有场板；
制备方法如下：
S1、晶片生长；
采用金属有机物化学气相沉积或分子束外延方法在衬底上依次生长成核层、外延层、势垒层、栅极盖帽层；
或者
采用MOCVD设备衬底上依次成核层、外延层、势垒层、栅极盖帽层；
S2、外延层结构刻蚀；
利用半导体光刻法和刻蚀法制作器件台面，通过半导体刻蚀方法对表面刻蚀，实现台面隔离；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；进一步刻蚀掉栅极区域外面的栅极盖帽层；
或者
将样品均匀旋涂光刻胶；样品放置在热板上加热，进行软烘；把样品放置在曝光机中持续曝光；在显影液中进行显影；在热板上加热坚膜；通过Cl基等离子体ICP刻蚀方法，刻蚀外延层结构，形成台面隔离，然后样品通过丙酮溶液清洗去胶；重复该步骤，在源、漏极区域刻蚀掉势垒层形成凹槽；重复该步骤，刻蚀掉栅极区域外面的盖帽层，形成栅极盖帽层；
S3、源、漏电极制作；
通过半导体光刻法定义出源、漏极所需区域，并通过金属沉积法沉积器件的源、漏极金属，通过高温退火，使复合金属结构变为合金，形成欧姆接触；利用等离子体增强化学气相沉积法、低压化学气相沉积法、磁控溅射法、电子束蒸发法中的任意一种方法进行沉积，形成器件表面钝化层；
或者
通过半导体光刻法定义出源、漏极所需区域，通过电子束蒸发法沉积器件的源、漏极金属，然后样品在丙酮溶液中剥离、清洗去胶；通过在氮气高温环境中退火，使复合金属结构变为合金，形成欧姆接触；利用PECVD技术沉积法进行沉积，形成器件表面钝化层；
S4、栅介质插入层制备；
通过半导体光刻法定义出栅极区域，对栅极盖帽层进行表面氧化，处理形成栅介质插入层；或者采用PECVD、LPCVD、MOCVD、ALD、磁控溅射法中的任意方法进行沉积，形成单层或者复合多重栅介质插入层；
或者
通过半导体光刻法定义出栅极区域，对栅极盖帽层表面进行低功率氧离子预处理，后采用LPCVD进行沉积，形成栅介质插入层；
S5、栅电极制作；
通过半导体光刻法定义出栅极和场板区域，通过金属沉积法沉积器件的栅极金属和向漏极延伸的场板金属，最后在器件表面沉积钝化层，然后采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，最后沉积金属薄膜制作引线，完成电极制作，得到最后器件结构；
或者
通过半导体光刻法定义出栅极和场板区域，通过电子束蒸发技术沉积器件的栅极和延伸场板金属，然后样品在丙酮溶液中剥离、清洗去胶；在器件表面采用PECVD沉积钝化层，采用半导体光刻法定义出源极、栅极和漏极所需的开口区域，将定义区域的钝化层去除，暴露出金属电极表面，通过磁控溅射法沉积电极金属，得到最后器件结构。
2.如权利要求1所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述衬底是硅、蓝宝石、碳化硅、金刚石、GaN自支撑衬底中的任意一种；所述成核层是AlN或者AlGaN超晶格；所述外延层是GaN或者GaAs；所述势垒层是AlGaN、InAlN、AlN、AlGaAs中的任意一种；所述钝化层是SiO2、Si3N4或者二者的复合结构。
3.如权利要求1所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述栅极盖帽层是p-GaN或者p-InGaN或者p-AlGaN。
4.如权利要求1所述的高阈值电压常关型高电子迁移率晶体管，其特征在于，所述复合栅介质插入层是氧化镓、二氧化硅、氮化硅、氧化铝、氧化铪中的任意材料形成的单层结构、或者是由上述材料任意组合的复合多重结构。
CN201910361958.6A 2019-04-30 2019-04-30 一种高阈值电压常关型高电子迁移率晶体管及其制备方法 Active CN110190116B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201910361958.6A CN110190116B (zh) 2019-04-30 2019-04-30 一种高阈值电压常关型高电子迁移率晶体管及其制备方法
US17/594,636 US20220209000A1 (en) 2019-04-30 2020-04-28 High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor
PCT/CN2020/087347 WO2020221222A1 (zh) 2019-04-30 2020-04-28 一种高阈值电压常关型高电子迁移率晶体管及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910361958.6A CN110190116B (zh) 2019-04-30 2019-04-30 一种高阈值电压常关型高电子迁移率晶体管及其制备方法

Publications (2)

Publication Number Publication Date
CN110190116A CN110190116A (zh) 2019-08-30
CN110190116B true CN110190116B (zh) 2021-12-31

Family

ID=67715487

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910361958.6A Active CN110190116B (zh) 2019-04-30 2019-04-30 一种高阈值电压常关型高电子迁移率晶体管及其制备方法

Country Status (3)

Country Link
US (1) US20220209000A1 (zh)
CN (1) CN110190116B (zh)
WO (1) WO2020221222A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110190116B (zh) * 2019-04-30 2021-12-31 大连理工大学 一种高阈值电压常关型高电子迁移率晶体管及其制备方法
CN110660643A (zh) * 2019-09-05 2020-01-07 西交利物浦大学 一种优化氮化镓高电子迁移率晶体管钝化的方法
WO2021142823A1 (zh) * 2020-01-19 2021-07-22 中国科学院半导体研究所 GaN基常关型高电子迁移率晶体管及制备方法
CN111370472A (zh) * 2020-03-19 2020-07-03 中国科学院半导体研究所 混合栅p-GaN增强型氮化镓基晶体管结构及制作方法
WO2022051932A1 (en) * 2020-09-09 2022-03-17 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device structures and methods of manufacturing the same
CN112510087B (zh) * 2020-12-01 2023-07-11 晶能光电股份有限公司 p型栅增强型GaN基HEMT器件及其制备方法
CN113113480A (zh) * 2021-03-24 2021-07-13 聚能晶源(青岛)半导体材料有限公司 具有p-GaN盖帽层的HEMT器件及制备方法
CN113078204B (zh) * 2021-03-25 2022-05-17 电子科技大学 一种氮化镓3d-resurf场效应晶体管及其制造方法
CN112951911A (zh) * 2021-04-15 2021-06-11 南通大学 增强型GaN基高电子迁移率晶体管及其制备方法
WO2022261898A1 (zh) * 2021-06-17 2022-12-22 华为技术有限公司 Hemt器件及其制作方法、电子设备
CN113628963B (zh) * 2021-08-05 2024-03-08 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN114597295A (zh) * 2022-02-23 2022-06-07 厦门大学 一种Mini/Micro LED的芯片结构及制备方法
CN115410922A (zh) * 2022-09-07 2022-11-29 中国科学技术大学 一种垂直型氧化镓晶体管及其制备方法
CN115683400A (zh) * 2022-09-14 2023-02-03 大连理工大学 基于复合氮化物和磁致伸缩材料结构的高灵敏度压力传感器、信号采集模块及电路系统
CN115663024A (zh) * 2022-10-28 2023-01-31 上海百功微电子有限公司 一种阈值可调节的GaN器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101897029A (zh) * 2007-12-10 2010-11-24 特兰斯夫公司 绝缘栅e模式晶体管
CN106373884A (zh) * 2016-09-08 2017-02-01 西安电子科技大学 复合栅介质GaN基绝缘栅高电子迁移率晶体管的制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102368501B (zh) * 2011-10-20 2013-11-27 中山大学 一种GaN基增强型MOSHFET器件的制备方法
JP2013157407A (ja) * 2012-01-27 2013-08-15 Fujitsu Semiconductor Ltd 化合物半導体装置及びその製造方法
US9443969B2 (en) * 2013-07-23 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having metal diffusion barrier
CN103904111B (zh) * 2014-01-20 2017-01-04 西安电子科技大学 基于增强型AlGaN/GaN HEMT器件结构及其制作方法
US9601608B2 (en) * 2014-11-13 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for a gallium nitride (GaN) high electron mobility transistor
US20170301780A1 (en) * 2016-04-15 2017-10-19 Macom Technology Solutions Holdings, Inc. High-voltage gan high electron mobility transistors with reduced leakage current
CN105895526B (zh) * 2016-04-26 2019-02-01 中国科学院微电子研究所 一种GaN基功率电子器件及其制备方法
CN107369704B (zh) * 2017-07-10 2021-01-01 西安电子科技大学 含有铁电栅介质的叠层栅增强型GaN高电子迁移率晶体管及制备方法
CN108155099A (zh) * 2017-12-22 2018-06-12 中国科学院苏州纳米技术与纳米仿生研究所 一种包含介质层的p型栅HEMT器件及其制作方法
CN109244130A (zh) * 2018-08-17 2019-01-18 西安电子科技大学 基于p-GaN和SiN层的自对准栅结构GaN MIS-HEMT器件及其制作方法
CN110112215B (zh) * 2019-04-30 2021-01-19 大连理工大学 兼具栅介质与刻蚀阻挡功能结构的功率器件及制备方法
CN110190116B (zh) * 2019-04-30 2021-12-31 大连理工大学 一种高阈值电压常关型高电子迁移率晶体管及其制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101897029A (zh) * 2007-12-10 2010-11-24 特兰斯夫公司 绝缘栅e模式晶体管
CN106373884A (zh) * 2016-09-08 2017-02-01 西安电子科技大学 复合栅介质GaN基绝缘栅高电子迁移率晶体管的制作方法

Also Published As

Publication number Publication date
CN110190116A (zh) 2019-08-30
WO2020221222A1 (zh) 2020-11-05
US20220209000A1 (en) 2022-06-30

Similar Documents

Publication Publication Date Title
CN110190116B (zh) 一种高阈值电压常关型高电子迁移率晶体管及其制备方法
JP6999197B2 (ja) 複合バリア層構造に基づくｉｉｉ族窒化物エンハンスメント型ｈｅｍｔ及びその製造方法
US7456443B2 (en) Transistors having buried n-type and p-type regions beneath the source region
CN110112215B (zh) 兼具栅介质与刻蚀阻挡功能结构的功率器件及制备方法
US8618578B2 (en) Field effect transistor
CN109004017B (zh) 具有极化结纵向泄漏电流阻挡层结构的hemt器件及其制备方法
EP3425674A2 (en) Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
CN105931999B (zh) 薄势垒增强型AlGaN/GaN高电子迁移率晶体管及其制作方法
US20140252371A1 (en) Heterojunction transistor and method of fabricating the same
CN109037326B (zh) 一种具有p型埋层结构的增强型hemt器件及其制备方法
CN102148157A (zh) 制作带有自对准场板的增强型hemt的方法
CN110459595A (zh) 一种增强型AlN/AlGaN/GaN HEMT器件及其制备方法
CN107785435A (zh) 一种低导通电阻MIS凹槽栅GaN基晶体管及制备方法
CN112289858A (zh) Ⅲ族氮化物增强型hemt器件及其制备方法
CN109950323B (zh) 极化超结的ⅲ族氮化物二极管器件及其制作方法
CN110429127B (zh) 一种氮化镓晶体管结构及其制备方法
CN114899227A (zh) 一种增强型氮化镓基晶体管及其制备方法
CN210429824U (zh) 一种增强型AlN/AlGaN/GaN HEMT器件
CN111739801A (zh) 一种SOI基p-GaN增强型GaN功率开关器件的制备方法
CN114361121B (zh) 一种带有p-SnO栅帽层的新型金刚石基垂直GaN-HEMT器件及其制备方法
CN115939183A (zh) 一种氧化镓基mosfet器件及其制备方法
CN111739800B (zh) 一种SOI基凹栅增强型GaN功率开关器件的制备方法
CN106449406B (zh) 一种垂直结构GaN基增强型场效应晶体管及其制造方法
CN209766426U (zh) 一种沉积多晶AlN的常关型HEMT器件
CN108695156B (zh) 改善iii族氮化物mis-hemt欧姆接触的方法及mis-hemt器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant