CN113078204B - 一种氮化镓3d-resurf场效应晶体管及其制造方法 - Google Patents
一种氮化镓3d-resurf场效应晶体管及其制造方法 Download PDFInfo
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Abstract
本发明涉及半导体器件技术领域,具体为一种氮化镓3D‑RESURF场效应晶体管及其制备方法。本发明在传统氮化镓HEMT器件中通过刻槽并二次外延的方式引入P型氮化镓电场调制区。在漂移区处形成P型氮化镓—二维电子气构成的p‑n结,并通过器件阻断耐压时该p‑n结空间电荷区的耗尽与扩展在平行于栅宽方向引入电场强度分量,改变原有电场方向,使得栅极漏侧电场尖峰得到缓解,电场强度明显降低;同时,利用该p‑n结耗尽二维电子气,降低了器件漏电流,提高器件单位漂移区长度耐压能力。本发明通过在氮化镓HEMT器件中引入P型氮化镓—二维电子气p‑n结实现了一种不同于传统场板技术的新型电场调制方式,利用该新结构在提高器件击穿电压的同时降低了器件的导通电阻。
Description
技术领域
本发明涉及半导体器件技术领域,具体涉及氮化镓3D-RESURF场效应晶体管及其制造方法。
背景技术
氮化镓(GaN)以其高临界击穿电场(~3.5×106V/cm)、高浓度二维电子气(~1013cm-2)、高电子迁移率(~2000cm2/v·s)以及良好的高温工作能力等优点,受到高速高功率器件领域的青睐。另外,得益于氮化镓较高的禁带宽度,其抗辐照能力天生优于硅基器件,这也使得氮化镓器件在无线通信、卫星通信等领域受到极大的重视。在功率半导体领域,得益于日益成熟的GaN-on-Si技术,GaN功率器件的成本大幅降低,也为氮化镓功率器件的商业化打下了坚实的基础。目前,以AlGaN/GaN异质结为基础的高电子迁移率晶体管HEMT(或异质结场效应晶体管HFET)已经初步实现了商业化,并成功应用在快充、无线充电、数据中心等领域之中。
氮化镓功率器件的成本虽已经大幅降低,但是和同一应用级别的硅器件相比还缺乏较为明显的成本优势,并且目前的氮化镓HEMT器件电学性能尚不能达到所期望的高度。高耐压的氮化镓HEMT器件通常采用两种技术方法:第一,增加器件漂移区长度。因为较长的漂移区会导致器件面积的增加以及器件导通电阻的上升,而为了实现较低的导通电阻,器件面积会进一步增大,因此该方法会较多的牺牲器件面积。第二,通过引入多层场板技术来提高器件耐压,但是效果较为有限并且会引入较大的寄生电容参数。故而,设计一款具有更高芯片面积利用率的GaN HEMT器件在降低器件使用成本上具有重要现实意义。
发明内容
本发明所要解决的,就是针对上述传统氮化镓HEMT器件芯片面积利用率低的问题,提出了一种具有更高芯片面积利用率、良好体内电场分布、高击穿电压、低导通电阻的新型氮化镓3D-RESURF(3维-降低表面电场)场效应晶体管。
为实现上述目的,本发明采用如下技术方案:
一种氮化镓3D-RESURF场效应晶体管,如图1所示,包括含应力调制结构的异质外延衬底基片1和位于异质外延衬底基片1上表面的氮化镓缓冲层2;所述的氮化镓缓冲层2上表面具有非故意掺杂氮化镓沟道层3和P型氮化镓电场调制区6,所述非故意掺杂氮化镓沟道层3半包围P型氮化镓电场调制区6,在非故意掺杂氮化镓沟道层3上表面具有氮化铝镓势垒层4,在氮化铝镓势垒层4上表面具有第一介质钝化层5、漏极8和源极9;沿横向方向,所述漏极8位于氮化铝镓势垒层4上表面远离P型氮化镓电场调制区6的一端,所述源极9位于另一端,且沿纵向方向,源极9由源极N型欧姆金属91和源极P型欧姆金属92构成,其中源极N型欧姆金属91位于氮化铝镓势垒层4上表面,源极P型欧姆金属92部分嵌入P型氮化镓电场调制区6上层且覆盖源极N型欧姆金属91上表面;所述纵向方向是同时垂直于横向方向和垂直方向的第三维方向;漏极8由漏极N型欧姆金属81和漏极P型欧姆金属82构成,漏极N型欧姆金属81与氮化铝镓势垒层4和第一介质钝化层5接触,漏极P型欧姆金属82位于漏极N型欧姆金属81上表面;所述第一介质钝化层5上表面和P型氮化镓电场调制区6上表面具有第二介质钝化层7,漏极P型欧姆金属82与第二介质钝化层7接触,第二介质钝化层7的上表面高于源极9的上表面,第二介质钝化层7上表面还具有栅介质层10,在栅介质层10上表面临近源极9处具有栅极11,栅极11与源极9之间有间距,所述栅极11和栅介质层11沿垂直方向向下延伸至贯穿第二介质钝化层7后延伸入第一介质钝化层5和P型氮化镓电场调制区6中形成槽栅,且栅极11还沿栅介质层11上表面向两侧延伸形成场板结构;所述非故意掺杂氮化镓沟道层3与氮化铝镓势垒层4界面处生成二维电子气,源极9和漏极8与二维电子气间为欧姆接触。
进一步的,所述氮化铝镓势垒层4的铝组分可选取0~1。
进一步地,所述氮化铝镓势垒层4中的镓元素可替换为镓、铟或镓铟化合物中的一种。
进一步的,所述栅介质层10为二氧化硅、氮化硅、氧化铝、氧化镁和二氧化铪中的一种或多种组合,其厚度可以为1-100nm。介质钝化层5及介质钝化层7为二氧化硅、氮化硅、氧化铝、氧化镁和二氧化铪中的一种或多种组合,其厚度可以为1-300nm。
进一步的,所述栅极11采用的的金属材料包括镍、金、铝、铱、铂、钯、钼、铯、铍、钨、氮化钛、钽、氮化钽中的任一种或任意几种组合。
进一步的,在反向阻断状态时,所述P型氮化镓电场调制区6,辅助耗尽二维电子气沟道,并在垂直于电流流向的水平方向引入Z方向电场,从而对漂移区的电场分布进行调制。
进一步的,所述P型氮化镓电场调制区6通过二次外延技术进行生长,其深度大于非故意掺杂氮化镓沟道层3厚度,其深度可为0.01-2um,其宽度占整个元胞宽度的比例可为0~1。
此新型氮化镓3D-RESURF场效应晶体管的制造方法,其特征在于,包括以下步骤:
第一步:在衬底基片1上层依次外延生长氮化镓缓冲层2、非故意掺杂氮化镓沟道层3、氮化铝镓势垒层4和介质钝化层5并在钝化介质5上沉积一层硬掩模材料。
第二步:首先在需要生长P型氮化镓电场调制区6的位置进行刻蚀,形成刻蚀槽。随后,采用二次外延技术,在刻蚀槽中二次外延P型氮化镓材料,形成P型氮化镓电场调制区6,去除硬掩模并进行平坦化处理。采用化学机械磨平技术与数字刻蚀结合的方案,此处利用化学机械磨平的平面化速度快成本低的特点,并利用了数字刻蚀对半导体材料的低损伤特点。
第三步:沉积钝化介质7,钝化P型氮化镓材料表面。
第四步:采用刻蚀技术对源漏金属电极接触位置进行刻蚀,完全刻蚀该区域的介质层。
第五步:首先在源极需要做N型欧姆接触位置沉积N型欧姆接触金属91、81,并在氮气氛围下进行高温快速退火,形成良好的N型欧姆接触。随后在源漏区域沉积P型欧姆接触金属92、82,并在氧气氛围下进行低温退火形成与P型氮化镓电场调制区6的欧姆接触,并同时实现P型氮化镓电场调制区6与源极9的短接。
第六步:采用刻蚀技术对栅极进行刻蚀,并通过对势垒层刻蚀深度的控制实现对器件阈值电压的调控。
第七步:采用化学气相沉积技术,淀积所需栅介质10,并采用光刻技术对不需要栅介质10的位置进行刻蚀。。
第八步:沉积栅极金属11。
本发明通过引入P型氮化镓电场调制区6在漂移区处形成P型氮化镓-二维电子气结,利用反向电压阻断时该结的耗尽在漂移区引入平行于栅宽方向的电场分量,使得电场方向发生改变,并以此方法对漂移区电场进行调制,最终提升漂移区单位长度耐压并且降低栅极漏测电场尖峰。通过引入P型氮化镓电场调制区6,在反向电压阻断时利用P型氮化镓-二维电子气结的空间电荷区扩展,一定程度上耗尽二维电子气并降低二维电子气浓度,以此实现对二维电子气的辅助耗尽,实现耗尽区辅助拓展最终提高器件穿通击穿电压。
本发明的有益效果为,具有更高芯片面积利用率、高反向耐压、低导通电阻、增强型阈值电压等优点,并且其所选用的衬底以及制造工艺与传统氮化镓异质结HEMT器件相兼容。本发明具有进一步降低目前氮化镓HEMT器件成本的现实意义。
附图说明
图1为本发明氮化镓3D-RESURF场效应晶体管的结构示意图;
图2为本发明氮化镓3D-RESURF场效应晶体管源极一侧的侧视图;
图3为本发明氮化镓3D-RESURF场效应晶体管的制造工艺流程中在衬底基片1上层依次外延生长氮化镓缓冲层2、非故意掺杂氮化镓沟道层3、氮化铝镓势垒层4和介质钝化层5后的结构示意图;
图4为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中P型氮化镓电场调制区6所需凹槽刻蚀后的结构示意图;
图5为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中在P型氮化镓电场调制区6再生长后的结构示意图;
图6为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中介质钝化层7沉积后的结构示意图;
图7为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中对源漏欧姆接触所需凹槽刻蚀形成后的结构示意图;
图8为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中在源、漏沉积N型欧姆金属81、91之后的结构示意图;
图9为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中在源、漏沉积P型欧姆金属82、92后的结构示意图;
图10为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中对栅极所需凹槽刻蚀形成后的结构示意图;
图11为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中在沉积栅介质10后形成的结构示意图;
图12为本发明氮化镓3D-RESURF场效应晶体管的工艺流程中在沉积栅极金属11后形成的结构示意图;
图13为传统氮化镓HEMT晶体管结构示意图;
具体实施方式
下面结合附图,详细描述本发明的技术方案:
本发明提出了一种高性能氮化镓3D-RESURF场效应晶体管,它与传统氮化镓HEMT晶体管不同,本发明通过引入二次外延形成的P型氮化镓电场调制区辅助耗尽二维电子气,并在平行于栅宽的Z轴方向引入电场使得漂移区电场分布更为均匀,有效提高了漂移区单位长度的耐压能力。漂移区单位长度耐压能力的提升使本发明中的氮化镓3D-RESURF场效应晶体管可以通过更小的漂移区尺寸达到与传统氮化镓HEMT晶体管相同的耐压水平,并且漂移区尺寸的缩小又可以进一步带来导通电阻减小的优点。最终使得氮化镓HEMT器件的芯片利用率得到大幅提升。根据半导体器件原理,以HEMT为例的平面氮化镓器件,其阻断电压时的电场尖峰主要出现在栅极漏测边缘。此处的高电场又会导致器件提前击穿、动态导通电阻上升等问题。针对该问题目前主流的解决方案是通过引入多层场板技术来实现对栅极漏测电场尖峰的缓解,但由于存在场板层数限制的有限电场调制作用以及引入的其他寄生问题,场板技术并不是一种令人满意的解决方案。本发明中P型氮化镓电场调制区的引入使得漂移区电场分布更为均匀的同时,也使得栅极漏测边缘电场尖峰得到降低,从而抑制由于栅极漏测电场尖峰过高而产生的各种问题。另外,在引入P型氮化镓电场调制区后,在保证器件漏电不变的同时可采用更厚的非故意掺杂氮化镓沟道层设计,以此来缓解由于氮化镓缓冲层带来的动态导通电阻衰退问题。
如图1和图2所示,一种氮化镓3D-RESURF场效应晶体管,包含应力调制结构异质外延衬底基片1、设置在衬底基片1上表面的氮化镓缓冲层2、设置在氮化镓缓冲层2上表面的非故意掺杂氮化镓沟道层3、设置在非故意掺杂氮化镓沟道层3上的氮化铝镓势垒层4、设置在氮化铝镓势垒层4之上的介质钝化层5、P型氮化镓电场调制区6、设置于介质钝化层5与P型氮化镓电场调制区6两层上表面的介质钝化层7,之上所述的异质结构可在非故意掺杂氮化镓沟道层3与氮化铝镓势垒层4界面处生成二维电子气;所述金属电极包含漏极8、源极9、栅极11,其中源极9的欧姆接触金属由两部分构成,包含实现源极9与二维电子气间欧姆接触的N型欧姆金属91、实现源极9与P型氮化镓电场调制区6之间欧姆接触的P型欧姆金属92,其中源极的N型欧姆金属91与漏极N型欧姆金属81为同一工艺步骤下实现,源极P型欧姆金属92与漏极P型欧姆金属82为同一工艺步骤下实现,栅极11下存在栅介质层10;所述P型氮化镓电场调制区6由源极9处延伸至栅极11与漏极8之间的漂移区处,即延伸至超过栅极11而未达到漏极8的位置。
本发明的工作原理为:
相比于如图13所示的传统结构,本发明的结构源极接地,栅极施加正电压且超过阈值电压时,费米能级相对位置上升,栅下电子积累形成电子沟道,此时器件处于导通状态。当栅极电压低于阈值电压时,栅下沟道消失,此时器件处于关断状态。在关断状态下,随着漏极电压上升,一方面P型氮化镓电场调制区与漂移区处二维电子气之间形成的P-GaN-2DEG结开始发生耗尽;另一方面,靠近栅极漏侧的二维电子气同样开始发生耗尽,耗尽区边界开始向漏侧推进。P-GaN-2DEG结的耗尽在平行于器件栅宽的方向引入电场。电场矢量方向的改变使得器件漂移区电场分布更为均匀,降低了器件栅极漏侧电场尖峰。并且由于P型氮化镓电场调制区在阻断状态下辅助耗尽漂移区的二维电子气,因而器件的漏电流得到明显降低,器件的穿通击穿电压得到明显提升。由此可见通过P型氮化镓电场调制区的引入可以降低器件栅极漏侧电场尖峰并有效提高单位漂移区长度耐,最终获得较高的芯片面积利用率。
由于P型氮化镓电场调制区的掺杂浓度在1017cm-3量级,而二维电子气的浓度在1019cm-3量级,因而P型氮化镓电场调制区与二维电子气发生耗尽时会在结面处产生较高的电场,而该电场可能会引起器件内部的强场击穿。但经过合理设计,使得漂移区的P型氮化镓调制区在未达到强场击穿条件前完全耗尽,即可避免这一问题。
实施例:
图3-图12为本发明一种氮化镓3D-RESURF场效应晶体管的制造工艺步骤示意图,其工艺流程如下:
(1)在衬底基片1上层依次外延生长氮化镓缓冲层2、非故意掺杂氮化镓沟道层3、氮化铝镓势垒层4和介质钝化层5并在钝化介质5上沉积一层硬掩模材料,如图3所示;
(2)首先在需要生长P型氮化镓电场调制区6的位置进行刻蚀,形成刻蚀槽,如图4所示。随后,采用二次外延技术,在刻蚀槽中二次外延P型氮化镓材料,形成P型氮化镓电场调制区6,去除硬掩模并进行平坦化处理。采用化学机械磨平技术与数字刻蚀结合的方案,此处利用化学机械磨平的平面化速度快成本低的特点,并利用了数字刻蚀对半导体材料的低损伤特点,如图5所示;
(3)采用PECVD技术沉积钝化介质7,钝化P型氮化镓材料表面,如图6所示;
(4)采用凹槽刻蚀技术对源漏金属电极接触位置进行刻蚀,完全刻蚀该区域的介质层。如图7所示;
(5)首先在源极需要做N型欧姆接触位置沉积N型欧姆接触金属91、81,如图8所示,并在氮气氛围下进行高温快速退火,形成良好的N型欧姆接触。随后在源漏区域沉积P型欧姆接触金属92、82,如图9所示,并在氧气氛围下进行低温退火形成与P型氮化镓电场调制区6的欧姆接触,并同时实现P型氮化镓电场调制区6与源极9的短接;
(6)采用凹槽刻蚀技术,对栅极进行刻蚀,并通过对势垒层刻蚀深度的控制实现对器件阈值电压的调控,如图10所示;
(7)采用化学气相沉积技术,淀积所需栅介质10,并采用光刻技术对不需要栅介质10的位置进行刻蚀,如图11所示;
(8)沉积栅极金属11,如图12所示。
Claims (6)
1.一种氮化镓3D-RESURF场效应晶体管,包括含应力调制结构的异质外延衬底基片(1)和位于异质外延衬底基片(1)上表面的氮化镓缓冲层(2);所述的氮化镓缓冲层(2)上表面具有非故意掺杂氮化镓沟道层(3)和P型氮化镓电场调制区(6),所述非故意掺杂氮化镓沟道层(3)半包围P型氮化镓电场调制区(6),在非故意掺杂氮化镓沟道层(3)上表面具有氮化铝镓势垒层(4),在氮化铝镓势垒层(4)上表面具有第一介质钝化层(5)、漏极(8)和源极(9);沿横向方向,所述漏极(8)位于氮化铝镓势垒层(4)上表面远离P型氮化镓电场调制区(6)的一端,所述源极(9)位于另一端,且沿纵向方向,源极(9)由源极N型欧姆金属(91)和源极P型欧姆金属(92)构成,其中源极N型欧姆金属(91)位于氮化铝镓势垒层(4)上表面,源极P型欧姆金属(92)部分嵌入P型氮化镓电场调制区(6)上层且覆盖源极N型欧姆金属(91)上表面;所述纵向方向是同时垂直于横向方向和垂直方向的第三维方向;漏极(8)由漏极N型欧姆金属(81)和漏极P型欧姆金属(82)构成,漏极N型欧姆金属(81)与氮化铝镓势垒层(4)和第一介质钝化层(5)接触,漏极P型欧姆金属(82)位于漏极N型欧姆金属(81)上表面;所述第一介质钝化层(5)上表面和P型氮化镓电场调制区(6)上表面具有第二介质钝化层(7),漏极P型欧姆金属(82)与第二介质钝化层(7)接触,第二介质钝化层(7)的上表面高于源极(9)的上表面,第二介质钝化层(7)上表面还具有栅介质层(10),在栅介质层(10)上表面源极(9)处具有栅极(11),栅极(11)与源极(9)之间有间距,所述栅极(11)和栅介质层(10)沿垂直方向向下延伸至贯穿第二介质钝化层(7)后延伸入第一介质钝化层(5)和P型氮化镓电场调制区(6)中形成槽栅,且栅极(11)还沿栅介质层(10)上表面沿横向方向两侧延伸形成场板结构;所述非故意掺杂氮化镓沟道层(3)与氮化铝镓势垒层(4)界面处生成二维电子气,源极(9)和漏极(8)与二维电子气间为欧姆接触。
2.根据权利要求1所述的一种氮化镓3D-RESURF场效应晶体管,其特征在于,所述氮化铝镓势垒层(4)中的镓元素可替换为镓、铟或镓铟化合物中的一种。
3.根据权利要求1所述的一种氮化镓3D-RESURF场效应晶体管,其特征在于,所述栅介质层(10)为二氧化硅、氮化硅、氧化铝、氧化镁和二氧化铪中的一种或多种组合,其厚度为1-100nm。
4.根据权利要求1所述的一种氮化镓3D-RESURF场效应晶体管,其特征在于,在反向阻断状态时,所述P型氮化镓电场调制区(6),辅助耗尽二维电子气沟道,并在垂直于电流流向的横向方向引入纵向方向电场,从而对漂移区的电场分布进行调制。
5.根据权利要求1所述的一种氮化镓3D-RESURF场效应晶体管,其特征在于,所述P型氮化镓电场调制区(6)的结深大于非故意掺杂氮化镓沟道层(3)的结深,P型氮化镓电场调制区(6)的结深为0.01-2um,P型氮化镓电场调制区(6)的宽度占整个元胞宽度的比例为0~1。
6.一种用于如权利要求1所述的氮化镓3D-RESURF场效应晶体管的制造方法,其特征在于,包括以下步骤:
第一步:在含应力调制结构的异质外延衬底基片(1)上层依次外延生长氮化镓缓冲层(2)、非故意掺杂氮化镓沟道层(3)、氮化铝镓势垒层(4)和第一介质钝化层(5),并在第一钝化介质(5)上沉积一层硬掩模材料;
第二步:在需要生长P型氮化镓电场调制区(6)的位置进行刻蚀,形成刻蚀槽,然后采用二次外延技术,在刻蚀槽中二次外延P型氮化镓材料,形成P型氮化镓电场调制区(6),去除硬掩模并进行平坦化处理;
第三步:在第一介质钝化层(5)和P型氮化镓电场调制区(6)上表面沉积第二介质钝化层(7),钝化P型氮化镓材料表面;
第四步:采用刻蚀技术完全刻蚀源漏金属电极接触位置的介质层;
第五步:在漏极位置氮化铝镓势垒层(4)上表面沉积漏极N型欧姆接触金属(81),同时在源极位置铝镓势垒层(4)上表面沉积源极N型欧姆接触金属(91),并在氮气氛围下进行高温快速退火,形成良好的N型欧姆接触,随后在漏极N型欧姆接触金属(81)上表面沉积漏极P型欧姆接触金属(82),在源极位置P型氮化镓电场调制区(6)上表面沉积源极P型欧姆接触金属(92),并在氧气氛围下进行低温退火形成与P型氮化镓电场调制区(6)的欧姆接触,并同时实现P型氮化镓电场调制区(6)与源极(9)的短接;
第六步:采用刻蚀技术对栅极进行刻蚀形成沟槽,并通过对势垒层刻蚀深度的控制实现对器件阈值电压的调控;
第七步:采用化学气相沉积技术,淀积所需栅介质(10),并采用光刻技术对不需要栅介质(10)的位置进行刻蚀;
第八步:在沟槽沉积栅极金属(11)。
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