WO2022261898A1 - Hemt器件及其制作方法、电子设备 - Google Patents

Hemt器件及其制作方法、电子设备 Download PDF

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Publication number
WO2022261898A1
WO2022261898A1 PCT/CN2021/100648 CN2021100648W WO2022261898A1 WO 2022261898 A1 WO2022261898 A1 WO 2022261898A1 CN 2021100648 W CN2021100648 W CN 2021100648W WO 2022261898 A1 WO2022261898 A1 WO 2022261898A1
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hemt device
layer
gate cap
cap layer
gate
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PCT/CN2021/100648
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English (en)
French (fr)
Inventor
胡彬
段焕涛
倪茹雪
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华为技术有限公司
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Priority to PCT/CN2021/100648 priority Critical patent/WO2022261898A1/zh
Priority to CN202180099310.1A priority patent/CN117501451A/zh
Publication of WO2022261898A1 publication Critical patent/WO2022261898A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a HEMT device, a manufacturing method thereof, and electronic equipment.
  • a high-electron-mobility transistor (HEMT) device is a semiconductor electronic device, due to its advantages of high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability, it is It is widely used in the fields of power electronics, microwave radio frequency, and optoelectronic devices.
  • the structure of the HEMT device mainly includes a substrate and a heterostructure disposed on the substrate, for example, the heterostructure includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer.
  • HEMT devices mainly use the two-dimensional electron gas (2DEG) generated by the polarization effect at the interface of the AlGaN/GaN heterostructure to achieve high electron mobility.
  • this kind of HEMT device is a normally-on device (or understood as a depletion device), that is, there is always a two-dimensional electron gas at the interface of the AlGaN/GaN heterostructure, which means that the HEMT device not only needs a negative bias, but also must be in The gate voltage is applied before the drain voltage. Therefore, in practical applications, it is necessary to separately provide a completely independent negative voltage power supply system to turn off the HEMT device, so the circuit is complicated and the cost is high. Moreover, when the HEMT device is normally on, there is additional power loss, resulting in high power consumption.
  • Embodiments of the present application provide a HEMT device, its manufacturing method, and electronic equipment, which are used to alleviate the problems of complex circuit and high power consumption of the depletion-type HEMT device.
  • a high electron mobility transistor HEMT device comprising: a substrate; a heterostructure disposed on the substrate; a capping layer disposed on the heterostructure; a gate cap layer disposed on the capping layer; The oxidation temperature of the material of the gate cap layer is lower than the oxidation temperature of the material of the cap layer; the grid is arranged on the gate cap layer.
  • the oxidation temperature of the material of the gate cap layer is lower than the oxidation temperature of the material of the cap layer. Therefore, in the process of preparing the HEMT device by using the method for manufacturing the HEMT device provided in the embodiment of the present application, when the thermal oxidation treatment is performed on the gate cap film, the cap film will not undergo an oxidation reaction. When the oxidized portion of the gate cap film is etched by an alkaline solution, the cap film below the gate cap film will not be etched because it has not been oxidized. In this way, the cut-off position of etching for the gate cap film can be precisely controlled, and the cap film below the gate cap film will not be etched.
  • the preparation method of the HEMT device provided by the embodiment of the present application is simple, does not rely on expensive and complicated etching equipment, does not require high equipment, and can control the etching cut-off position well, and there will be no insufficient etching. Or the problem of over-etching can improve the yield of HEMT devices.
  • the distance between the gate and the heterostructure can be increased, thereby increasing the threshold voltage of the HEMT device and ensuring the reliability of the circuit. Safety.
  • the material of the gate cap layer is p-type AlGaN.
  • the material of the gate cap layer is doped with Mg, and the doping concentration of Mg is 1e18-1e21/cm3.
  • the mass percentage of Al in the gate cap layer is 10-30%.
  • the thickness of the gate cap layer is 10-200 nm. Since the thickness of the gate cap layer is too large, the thickness of the HEMT device will be increased, and the two-dimensional electron gas concentration at the heterostructure interface will be reduced, thereby reducing the output current. If the thickness of the gate cap layer is too small, the electrons under the gate cap layer cannot be exhausted, and the effect of the enhanced HEMT device cannot be achieved.
  • the material of the capping layer is GaN or Si3N4.
  • the thickness of the capping layer is 1-20 nm.
  • the thickness of the capping layer is too small to protect the barrier layer. Too large thickness of the capping layer will increase the thickness of the HEMT device.
  • the HEMT device further includes a source and a drain; the source and the drain are arranged on the heterostructure and form an ohmic contact with the heterostructure; the source and the drain are exposed on the capping layer.
  • the heterostructure includes a channel layer and a barrier layer; the channel layer is disposed on a side of the barrier layer close to the substrate.
  • a method for preparing a high electron mobility transistor HEMT device comprising: forming a heterostructure on a substrate; forming a cap film on the heterostructure; forming a gate cap film on the cap film; and forming a gate cap film
  • the oxidation temperature of the material is lower than the oxidation temperature of the cap layer material; the gate cap film is thermally oxidized and etched to form a gate cap layer; and a gate is formed on the surface of the gate cap layer.
  • the oxidation temperature of the material of the gate cap layer is lower than the oxidation temperature of the material of the cap layer. Therefore, in the process of preparing the HEMT device by using the method for manufacturing the HEMT device provided in the embodiment of the present application, when the thermal oxidation treatment is performed on the gate cap film, the cap film will not undergo an oxidation reaction. When the oxidized portion of the gate cap film is etched by an alkaline solution, the cap film below the gate cap film will not be etched because it has not been oxidized. In this way, the cut-off position of etching for the gate cap film can be precisely controlled, and the cap film below the gate cap film will not be etched.
  • the preparation method of the HEMT device provided by the embodiment of the present application is simple, does not rely on expensive and complicated etching equipment, does not require high equipment, and can control the etching cut-off position well, and there will be no insufficient etching. Or the problem of over-etching can improve the yield of HEMT devices.
  • performing thermal oxidation treatment and etching on the gate cap film includes: forming a mask pattern on the surface of the gate cap film; wherein, the mask pattern is the same as the pattern of the gate cap layer to be formed ; performing thermal oxidation treatment on the part of the gate cap film not covered by the mask pattern; removing the oxidized part of the gate cap film; removing the mask pattern.
  • the material of the gate cap layer is p-type AlGaN.
  • the thickness of the gate cap layer is 10-200 nm.
  • the material of the capping layer is GaN or Si3N4.
  • the thickness of the capping layer is 1-20 nm.
  • an electronic device including a HEMT device and an antenna; the HEMT device is used to amplify a radio frequency signal and output it to the antenna for external radiation; wherein, the HEMT device is the HEMT device according to any one of the first aspect.
  • the electronic equipment provided by the embodiment of the present application includes the HEMT device of the first aspect, and its beneficial effect is the same as that of the HEMT device, so it will not be repeated here.
  • an electronic device which is characterized in that it includes a HEMT device and a printed circuit board electrically connected to the HEMT device; wherein, the HEMT device is the HEMT device of any one of the first aspect; the substrate of the HEMT device is a conductive type substrate.
  • the electronic equipment provided by the embodiment of the present application includes the HEMT device of the first aspect, and its beneficial effect is the same as that of the HEMT device, so it will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a base station provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an AAU provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a charger provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram during the manufacture of a HEMT device provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a HEMT device provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram during the preparation of a HEMT device provided by an embodiment of the present application.
  • Fig. 7 is the flowchart of the preparation method of a kind of HEMT device provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram during the preparation process of a gate cap layer provided by an embodiment of the present application.
  • first”, second, etc. are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • the direction indications such as up, down, left, right, front and back, etc. used to explain the structure and movement of different components in the present application are relative. These indications are pertinent when the parts are in the positions shown in the figures. However, should the description of component locations change, these directional indications will change accordingly.
  • A is located on B, and it can be understood that B acts as a carrier of A. Or it can be understood that, according to the preparation sequence of the film layers, B is formed first, and then A is formed. It is not limited that A is above B in space. If the device is placed at an angle and rotated, although A is not above B in space, A is still carried by B, that is, A is still on B.
  • the term "semi-insulating (SI)" refers to: the resistivity is greater than 10 5 ⁇ cm.
  • a semi-insulating SiC substrate means that the resistivity of the SiC substrate is greater than 10 5 ⁇ cm.
  • two-dimensional electron gas (2DEG) refers to: the movement of electrons in the direction perpendicular to the interface is bound by the potential well and quantized, while its movement parallel to the surface Movement is still free, and such free electrons in two-dimensional directions are called two-dimensional electron gas.
  • the term "current collapse effect” refers to the effect that when the drain voltage of the HEMT device exceeds a certain value, the current begins to decrease as the drain voltage increases, and cannot reach an ideal value.
  • mass percentage means mass fraction, which is a physical term used to express the percentage of a certain substance contained in a solution per unit mass.
  • heterostructure refers to a stacked structure formed of two or more different semiconductor materials.
  • An embodiment of the present application provides an electronic device, which can be, for example, a charger, a charging small household appliance, a drone, aerospace equipment, a lidar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network , fifth-generation mobile communication technology) communication equipment and other different types of user equipment or terminal equipment; the electronic equipment can also be network equipment such as base stations.
  • the embodiment of the present application does not specifically limit the specific form of the electronic device.
  • HEMT devices are semiconductor electronic devices, which are widely used as radio frequency devices or power devices due to their advantages of high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.
  • a base station 1 includes a base band processing unit (base band unit, BBU) 11 and an active antenna unit (active antenna unit, AAU) 12.
  • BBU11 is mainly responsible for baseband digital signal processing, for example, FFT (fast fourier transform, fast Fourier transform)/IFFT (inverse fast fourier transform, inverse fast Fourier transform), modulation/demodulation, channel coding/decoding, etc.
  • the AAU 12 includes a calculation unit 121 , a first transmission unit 122 and an antenna unit 123 .
  • the computing unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212 and a power supply unit 1213, the control unit 1210, the second transmission unit 1211, the baseband unit 1212 and the power supply unit 1213 are electrically connected to each other, and the control unit 1210 is used for Responsible for the control of radio frequency signals, the second transmission unit 1211 is used to be responsible for the transmission of radio frequency signals, and the baseband unit 1212 is used to be responsible for the conversion of digital signals and analog signals.
  • the baseband unit 1212 is, for example, a DAC (digital to analog converter, digital to analog converter) ), the DAC can convert the digital signal output by the BBU 11 into an analog signal, and the power supply unit 1213 is electrically connected to the power supply 124 for powering the control unit 1210, the second transmission unit 1211 and the baseband unit 1212 in the computing unit 121.
  • the first transmission unit 122 is used for transmitting and amplifying radio frequency signals.
  • the first transmission unit 122 includes an RF (radio frequency, radio frequency) unit 1221 and a PA (power amplifier, power amplifier) 1222, the RF unit 1221 is used to convert the analog signal into a low-power radio frequency signal, and the PA1222 is used to convert the low-power radio frequency
  • the signal is output to the antenna unit 123 after power amplification.
  • the antenna unit 123 is responsible for radiating the radio frequency signal to the outside.
  • the AAU 12 may include multiple RF units 1221 , multiple PAs 1222 and multiple antenna units 123 . It should be noted that the above PA1222 may be a HEMT device.
  • the electronic equipment provided in the embodiment of the present application is not limited to the base station shown in Figure 1 and Figure 2, any electronic equipment that needs to use a power amplifier to amplify the signal belongs to the scope of the present application The application scenario of the embodiment.
  • the charger 2 may include a power device, a resistor R, an inductor L, a capacitor C, etc.
  • the power device may be, for example, a HEMT device.
  • the HEMT device, the resistor R, the inductor L and the capacitor C can be interconnected through a printed circuit board (PCB).
  • PCB printed circuit board
  • the electronic device provided by the embodiment of the present application is not limited to the charger shown in FIG. 3 , any electronic device that needs to use a power device belongs to the application scenario of the embodiment of the present application .
  • an enhancement mode (E-Mode) HEMT device is provided.
  • the enhanced HEMT device is well compatible with other parts of the circuit, and there is no need to design an independent power system. Moreover, when HEMT devices are used in the electronic field, depletion-type HEMT devices not only require an independent negative bias system, but also require the operation of this negative bias system to be powered on before the power supply for system safety. Since the enhanced HEMT device does not need to design an independent power supply system, it can avoid conduction damage during system startup and mode transition. Furthermore, the enhancement mode HEMT device is a normally-off device, so it can save energy.
  • a HEMT device includes a substrate 10, a heterostructure 20, a gate cap layer 30, a source (source, S), a drain (drain, D) and a gate (gate, G).
  • the heterostructure 20 includes a channel layer 21 and a barrier layer 22 , and the channel layer 21 is disposed on a side of the barrier layer 22 close to the substrate 10 . Or it can be understood that the channel layer 21 is disposed on the barrier layer 22 .
  • the material of the channel layer 21 is GaN, and the material of the barrier layer 22 is AlGaN.
  • the material of the gate cap layer 30 is a P-type doped GaN layer, and the thickness of the gate cap layer 30 is 40-150 nm.
  • the working principle of the HEMT device is as follows: the source S and the drain D respectively form a conductive ohmic contact with the barrier layer 22 , and the gate G forms a Schottky contact with the barrier layer 22 .
  • the dotted line in the channel layer 21 represents the 2DEG generated by polarization in the heterostructure 20 formed by the channel layer 21 and the barrier layer 22 in the HEMT device. 2DEG is used to efficiently conduct electrons under the action of an electric field.
  • the source S and the drain D are used to make the 2DEG flow in the channel layer 21 between the source S and the drain D under the action of the electric field, and the conduction between the source S and the drain D occurs in the channel Two-dimensional electron gas in layer 21.
  • the gate G is disposed between the source S and the drain D, and is used to allow or block the passage of the two-dimensional electron gas.
  • 2DEG has high conductivity, partly because the 2DEG in the potential well is on the side of the intrinsic semiconductor, and there is no scattering effect of ionized impurity centers there, so the mobility of these 2DEGs moving along the plane direction is relatively High (especially at lower temperatures, when lattice vibrations are weakened).
  • the gate cap layer 30 can adjust the energy band structure of the heterostructure 20 to deplete the electrons directly under the gate cap layer 30 .
  • the 2DEG is in a pinch-off state without a bias voltage, the 2DEG cannot communicate and flow in the channel layer 21 between the source S and the drain D, and the HEMT device is in an off state. That is, HEMT devices are normally off devices.
  • the preparation method of the HEMT device includes:
  • the thickness of the gate cap layer 30 is 40-150 nm, it is usually relatively thin, and the GaN material is also relatively special. Therefore, when etching a thinner P-type GaN film, the requirements for the etching process are relatively high, and higher requirements are put forward for roughness, uniformity, selectivity, and chamber control. Moreover, the problem of over-etching (the barrier layer 22 is also etched) or insufficient etching (the GaN film is not etched completely, and the barrier layer 22 is not exposed) is prone to occur during etching, resulting in unstable process and low device yield. will be affected.
  • a high-precision microscope such as a scanning electron microscope or an atomic force microscope
  • a high-precision microscope is used to repeatedly detect the etching depth and perform repeated etching to control the etching precision.
  • the HEMT device includes a substrate 10 , a heterostructure 20 , a gate dielectric layer, a source S, a drain D and a gate G.
  • the heterostructure 20 includes a channel layer 21 and a barrier layer 22 , and the channel layer 21 is disposed on a side of the barrier layer 22 close to the substrate 10 . Or it can be understood that the channel layer 21 is disposed on the barrier layer 22 .
  • the material of the channel layer 21 is GaN, and the material of the barrier layer 22 is AlGaN.
  • a groove is provided on the barrier layer 22 , and the gate dielectric layer covers the barrier layer 22 , exposing the source S and the drain D.
  • the gate G is located directly above the groove on the barrier layer 22 .
  • the groove is located directly below the gate G, so that the 2DEG directly below the gate G is depleted, and the concentration of 2DEG in the rest of the channel layer 21 does not change. Therefore, the 2DEG is in a pinch-off state without a bias voltage, the 2DEG cannot communicate and flow in the channel layer 21 between the source S and the drain D, and the HEMT device is in an off state. That is, HEMT devices are normally off devices.
  • the thickness from the bottom of the groove to the channel layer 21 is generally reserved below 3-5 nm. That is to say, the thickness of the barrier layer 22 generally needs to be etched to be reduced to less than 3-5 nm. To control the etching precision to such a high level, the process is relatively difficult and highly dependent on etching equipment. Due to the limitation of the process, the thickness from the bottom of the groove to the channel layer 21 is a fluctuating value, which causes the pinch-off voltage of the HEMT device to fluctuate greatly. Also, this structure has limited pinch-off effect, with a small amount of leakage at zero bias. Due to the existence of electric leakage, HEMT devices are easy to burn out in a high-voltage environment.
  • an embodiment of the present application provides a HEMT device, which can be applied to the above-mentioned electronic device.
  • the structure of the HEMT device and its manufacturing method are exemplarily introduced.
  • the HEMT device includes a substrate 10 , a nucleation layer 40 , a graded buffer layer 50 , a heterostructure 20 , a capping layer 60 , a gate capping layer 30 , a source S, a drain D, and a gate G.
  • the preparation method of the HEMT device includes:
  • the nucleation layer 40 is provided on the substrate 10 .
  • the nucleation layer 40 is provided on the surface of the substrate 10 .
  • the method for forming the nucleation layer 40 may be, for example, metal-organic chemical vapor deposition (MOCVD) growth method or molecular beam epitaxy (molecular beam epitaxy, MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the material of the nucleation layer 40 may include, for example, one or more of GaN, AlGaN, and aluminum nitride (AlN).
  • the nucleation layer 40 can provide a nucleation center to promote the epitaxial growth of the graded buffer layer 50 .
  • the above substrate 10 is a semi-insulating substrate.
  • the aforementioned substrate 10 is a conductive substrate.
  • the aforementioned substrate 10 is a diamond substrate or a silicon carbide (SiC) substrate.
  • the grown SiC substrate is a conductive type substrate if the purity of the raw material is not high.
  • the grown SiC substrate is a semi-insulating substrate.
  • the diamond substrate formed by normal growth is a semi-insulating substrate.
  • the formed diamond substrate is a conductive substrate.
  • the thermal conductivity of the diamond substrate is generally 1000W ⁇ m -1 ⁇ K -1 to 2000W ⁇ m -1 ⁇ K -1
  • the thermal conductivity of the SiC substrate is generally about 370W ⁇ m -1 ⁇ K -1 .
  • the substrate 10 is a diamond substrate or a SiC substrate, the heat dissipation capability of the substrate 10 is relatively high, thereby improving the heat dissipation capability of the HEMT device.
  • the graded buffer layer 50 is formed on the side of the nucleation layer 40 away from the substrate 10 .
  • the graded buffer layer 50 is disposed on the side of the nucleation layer 40 away from the substrate 10 .
  • the graded buffer layer 50 is disposed on the surface of the nucleation layer 40 away from the substrate 10 .
  • the method of forming the graded buffer layer 50 may, for example, adopt the MOCVD process to epitaxially grow an AlGaN graded layer whose Al (aluminum) composition gradually decreases.
  • an Al 0.8 Ga 0.2 N layer, an Al 0.5 Ga 0.5 N layer, and an Al 0.2 Ga 0.8 N layer are sequentially formed on the side of the nucleation layer 40 away from the substrate 10 by MOCVD process to form the graded buffer layer 50 .
  • the composition of the graded buffer layer 50 is different from that when the HEMT device is used as a power device.
  • the heterostructure 20 is formed on the side of the graded buffer layer 50 away from the substrate 10 .
  • both the nucleation layer 40 and the graded buffer layer 50 are formed on the substrate 10 . Therefore, the heterostructure 20 formed on the side of the graded buffer layer 50 away from the substrate 10 is also located on the substrate 10 .
  • the heterostructure 20 includes a channel layer 21 and a barrier layer 22 .
  • the channel layer 21 is disposed on the side of the barrier layer 22 close to the substrate 10 , that is, the channel layer 21 is disposed on the side of the barrier layer 22 close to the graded buffer layer 50 .
  • the channel layer 21 is disposed on the surface of the graded buffer layer 50 facing the barrier layer 22 .
  • forming the heterostructure 20 on the substrate 10 includes sequentially forming a channel layer 21 and a barrier layer 22 on the substrate 10 .
  • the method of forming the channel layer 21 and the barrier layer 22 may be, for example, MOCVD growth method or MBE growth method.
  • the material of the channel layer 21 may include, for example, one or more of GaN, AlGaN, indium aluminum nitride (InAlN), AlN, and scandium aluminum nitride (ScAlN).
  • the material of the barrier layer 22 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.
  • the materials of the channel layer 21 and the barrier layer 22 are different.
  • the material of the channel layer 21 includes GaN
  • the material of the barrier layer 22 includes AlGaN.
  • the capping film 61 is formed on the side of the heterostructure 20 away from the substrate 10 .
  • the capping film 61 is disposed on the heterostructure 20 .
  • the capping film 61 is disposed on the surface of the heterostructure 20 away from the substrate 10 .
  • the method of forming the capping film 61 may be, for example, the MOCVD growth method or the MBE growth method to form the capping film 61 .
  • the material of the capping film 61 may be, for example, GaN or silicon nitride (Si 3 N 4 ).
  • the thickness of the capping layer 60 is too small to protect the barrier layer 22 .
  • a too large thickness of the capping layer 60 will increase the thickness of the HEMT device. Therefore, in some embodiments, the thickness of the capping film 61 may be 1-20 nm, for example.
  • the thickness of the capping film 61 is 2nm, 3nm, 4nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm.
  • the gate cap layer 30 is formed on the side of the cap film 61 away from the substrate 10 .
  • the gate cap layer 30 is disposed on the capping film 61 .
  • the gate cap layer 30 is disposed on the surface of the cap film 61 away from the substrate 10 .
  • the gate cap layer 30 is used to adjust the energy band structure of the heterostructure 20 to deplete the electrons directly under the gate cap layer 30 .
  • the 2DEG in the HEMT device is in a pinch-off state without bias voltage, the 2DEG cannot communicate and flow in the channel layer 21 between the source S and the drain D, and the HEMT device is in an off state, so that the HEMT device is normally off device.
  • the method for forming the gate cap layer 30 includes: forming the gate cap film 31 on the cap film 61 , performing thermal oxidation treatment and etching on the gate cap film 31 to form the gate cap layer 30 .
  • the method for forming the gate cap layer 30 includes:
  • the gate cap film 31 is formed on the side of the cap film 61 away from the substrate 10 .
  • the gate cap film 31 can be formed by MOCVD growth method or MBE growth method.
  • the material of the gate cap film 31 may be, for example, p-type AlGaN, for example, magnesium (Mg) may be doped during the AlGaN growth process to form the gate cap film 31 of p-type AlGaN.
  • the doping concentration can be controlled at 1e18-1e21/cm3, for example, the doping concentration is 1e19/cm3, 1e20/cm3.
  • the mass percentage of aluminum (Al) in the gate cap film 31 can be controlled at 10-30%, for example, the mass percentage of Al is 15%, 20%, 25%.
  • the material of the gate cap film 31 may be, for example, AlN.
  • the above-mentioned material of the gate cap film 31 is only an illustration, and the oxidation temperature of the material of the gate cap film 31 is lower than the oxidation temperature of the material of the cap film 61 .
  • the oxidation temperature of the material of the gate cap film 31 refers to the lowest temperature at which the material of the gate cap film 31 undergoes an oxidation reaction.
  • the oxidation temperature of the material of the capping film 61 refers to the lowest temperature at which the material of the capping film 61 undergoes an oxidation reaction.
  • the thickness of the gate cap film 31 may be, for example, 10-200 nm.
  • the thickness of the gate cap film 31 is 30nm, 50nm, 80nm, 100nm, 130nm, 150nm, 180nm.
  • a mask pattern is formed on the surface of the gate cap film 31 away from the substrate 10 .
  • the pattern of the mask is the same as that of the gate cap layer to be formed, and the pattern of the mask may be photoresist, for example.
  • the oxidation temperature of the material of the gate cap film 31 is lower than the oxidation temperature of the material of the cap film 61 , when thermal oxidation treatment is performed on the gate cap film 31 , the temperature is insufficient to oxidize the cap film 61 . That is to say, when the gate cap film 31 is thermally oxidized, the cap film 61 will not be oxidized.
  • the material of the gate cap film 31 is p-type AlGaN, and the material of the cap film 61 is GaN.
  • the material of the cap film 61 is GaN.
  • AlGaN is more easily oxidized than GaN, and GaN will not be oxidized.
  • the temperature continues to rise to 800 ° C, both AlGaN and GaN can be oxidized. That is to say, the oxidation temperature of the material of the gate cap film 31 is 550°C, and the oxidation temperature of the material of the cap film 61 is 800°C.
  • AlGaN is more easily oxidized than GaN mainly because the Gibbs free energy change of Al 2 O 3 is larger than that of Ga 2 O 3 .
  • the thermal oxidation treatment temperature is controlled at 550-650° C., and the time may be 30-60 minutes, for example, and sufficient oxygen is introduced during the thermal oxidation treatment to ensure sufficient oxidation of the p-type AlGaN. Under this condition, AlGaN and oxygen react to form Al 2 O 3 and Ga 2 O 3 .
  • the oxidized gate cap film 31 may be etched with an alkaline solution.
  • Al 2 O 3 and Ga 2 O 3 can be etched away by a 70° potassium hydroxide (KOH) solution. Moreover, since the gate cap film 31 is hardly oxidized, the gate cap film 31 will not be etched substantially in the process of etching Al 2 O 3 and Ga 2 O 3 in the KOH solution. The influence of the cap film 31 is relatively small.
  • KOH potassium hydroxide
  • the material of the gate cap layer 30 can be, for example, p-type AlGaN.
  • the concentration range of Mg doping is 1e18-1e21/cm3, and the mass percentage of Al is 10-30%.
  • the oxidation temperature of the material of the gate cap layer 30 is lower than the oxidation temperature of the material of the cap layer 60 .
  • the thickness of the gate cap layer 30 may be, for example, 10-200 nm.
  • the cross-sectional shape of the gate cap layer 30 is not limited, for example, it may be rectangular, trapezoidal, inverted trapezoidal, hourglass-shaped or drum-shaped, etc.
  • the orthographic projection of the gate cap layer 30 on the substrate 10 is located at within the orthographic projection above. That is, the pattern of the gate cap layer 30 is smaller than the pattern of the capping film 61 . Or it can be understood that the gate cap layer 30 exposes the surface of the cap film 61 away from the substrate 10 .
  • openings for setting the source S and the drain D are etched on the capping film 61 , and the openings on the capping film 61 expose the barrier layer 22 below the capping film 61 .
  • the barrier layer 22 can be protected, preventing the surface of the barrier layer 22 from being oxidized, and reducing the surface state of the HEMT device. That is, the on-resistance of the HEMT device is reduced, thereby reducing the gate leakage, the effect of too small thickness and power consumption of the HEMT device, and improving the reliability of the HEMT device.
  • the cap film 61 when the cap film 61 is etched to form openings for making the source S and the drain D, a small amount of etching is performed on the barrier layer 22 . That is to say, finally, there will be recesses on the barrier layer 22 .
  • the source S and the drain D and the recessed portion (Recess) on the barrier layer 22 can form a new ohmic contact surface, which is beneficial to the TiN ( Diffusion of titanium nitride) to form a second conductive channel, effectively reducing the ohmic contact resistance.
  • adopting the structure of forming a recessed part on the barrier layer 22 can effectively increase the maximum current of the drain D and reduce the on-resistance of the HEMT device.
  • the opening of the capping layer 60 exposes the barrier layer 22, then the source S and the drain D are formed at the opening of the capping layer 60, which is equivalent to the source S and the drain D being arranged on the barrier layer 22 in the heterostructure 20 , the source S and the drain D form ohmic contact with the barrier layer 22 in the heterostructure 20 , and the source S and the drain D are exposed to the cap layer 60 .
  • the source S and the drain D can be formed synchronously.
  • the materials of the source S and the drain D may be sequentially stacked titanium (Ti) layer, Al layer, nickel (Ni) layer and gold (Au) layer, namely Ti/Al/Ni/Au.
  • the material of the source S and the drain D may be Ti layer, Al layer, platinum (Pt) layer and Au layer stacked in sequence, that is, Ti/Al/Pt/Au.
  • the material of the source S and the drain D may be Ti layer, tantalum (Ta) layer and Ti layer stacked in sequence, that is, Ti/Ta/Ti.
  • the material of the source S and the drain D may be Au or palladium (Pd).
  • the gate G is formed on the surface of the gate cap layer 30 away from the substrate 10 .
  • the gate G is disposed on the surface of the gate cap layer 30 .
  • the gate G is disposed on the surface of the gate cap layer 30 , so the pattern of the gate G is smaller than or equal to the pattern of the gate cap layer 30 . That is, the orthographic projection of the gate G on the substrate 10 is located within the orthographic projection of the gate cap layer 30 on the substrate 10 . Alternatively, the orthographic projection of the gate G on the substrate 10 coincides with the orthographic projection of the gate cap layer 30 on the substrate 10 .
  • the material of the gate G may be, for example, Au or palladium (Pd).
  • the source S, the drain D and the gate D may be formed simultaneously. It is also possible to form the source S and the drain D at the same time first, and then form the gate G. It is also possible to form the gate G first, and then form the source S and the drain D at the same time.
  • the oxidation temperature of the material of the gate cap layer 30 is lower than the oxidation temperature of the material of the cap layer 60 . Therefore, in the process of fabricating the HEMT device using the method for fabricating the HEMT device provided in the embodiment of the present application, when the gate cap film 31 is thermally oxidized, the cap film 61 will not undergo oxidation reaction. When the oxidized portion of the gate cap film 31 is etched by an alkaline solution, the cap film 61 below the gate cap film 31 will not be etched because it has not been oxidized.
  • the preparation method of the HEMT device provided by the embodiment of the present application is simple, does not rely on expensive and complicated etching equipment, does not require high equipment, and can control the etching cut-off position well, and there will be no insufficient etching. Or the problem of over-etching can improve the yield of HEMT devices.
  • the stability of the threshold voltage of the HEMT device can be increased by arranging the capping layer 60 and the gate capping layer 30 between the gate G and the heterostructure 20 . At the same time, the surface of the HEMT device can be well protected, and the current collapse effect can be effectively suppressed.
  • the substrate 10 and the layer between the substrate 10 and the source S are further provided with through holes.
  • a transition part can be formed on the side of the substrate 10 away from the heterostructure 20, and the transition part is coupled to the source S of the HEMT device through the above-mentioned through hole in the HEMT device, so as to realize the HEMT device coupled in parallel.
  • a transition portion can be formed on the side of the substrate 10 away from the heterostructure 20, and the transition portion passes through the HEMT device.
  • the above-mentioned through hole is coupled to the source S of the HEMT device, and the transition part is also coupled to the electronic device on the side of the substrate 10 away from the heterostructure 20, so as to realize the coupling between the HEMT device and the electronic device.

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Abstract

本申请实施例提供一种HEMT器件及其制作方法、电子设备，涉及半导体技术领域，可以缓解耗尽型HEMT器件电路复杂、功耗大的问题。HEMT器件包括：衬底、异质结构、盖帽层、栅帽层以及栅极。异质结构设置在衬底上。盖帽层设置在异质结构上。栅帽层设置在盖帽层上，栅帽层材料的氧化温度低于盖帽层材料的氧化温度。栅极设置在栅帽层上。

Description

HEMT器件及其制作方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种HEMT器件及其制作方法、电子设备。
背景技术
高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件是一种半导体电子器件，由于其具有高击穿电场、高沟道电子浓度、高电子迁移率和高温度稳定性等优点，因而被广泛的应用于功率电子领域、微波射频领域、光电器件领域等。
HEMT器件的结构主要包括衬底以及设置在衬底上的异质结构，异质结构例如包括氮化镓(GaN)层和氮化铝镓(AlGaN)层。HEMT器件主要是利用AlGaN/GaN异质结构界面处极化效应产生的二维电子气(2DEG)实现高电子迁移率。
但是由于这种HEMT器件为常开器件(或者理解为耗尽型器件)，即，AlGaN/GaN异质结构界面处一直存在二维电子气，意味着HEMT器件不仅需要负偏压，还必须在漏极电压之前施加栅极电压。因此，在实际应用中，需要单独提供一个完全独立的负压电源系统将HEMT器件关闭，所以电路复杂，成本高。而且HEMT器件常开也有额外功率损耗，导致功耗较大。
发明内容
本申请实施例提供一种HEMT器件及其制作方法、电子设备，用于缓解耗尽型HEMT器件电路复杂、功耗大的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种高电子迁移率晶体管HEMT器件，包括：衬底；异质结构，设置在衬底上；盖帽层，设置在异质结构上；栅帽层，设置在盖帽层上；栅帽层材料的氧化温度低于盖帽层材料的氧化温度；栅极，设置在栅帽层上。
本申请实施例提供的HEMT器件中栅帽层材料的氧化温度低于盖帽层材料的氧化温度。因此，采用本申请实施例提供的HEMT器件的制备方法制备HEMT器件的过程中，对栅帽薄膜进行热氧化处理时，盖帽薄膜不会发生氧化反应。在通过碱性溶液对栅帽薄膜被氧化的部分进行刻蚀时，位于栅帽薄膜下方的盖帽薄膜因未被氧化而不会被刻蚀。这样一来，可以精准的控制对栅帽薄膜的刻蚀截止位置，不会刻蚀到位于栅帽薄膜下方的盖帽薄膜。因此，本申请实施例提供的HEMT器件的制备方法工艺方法简单，不依赖于昂贵复杂的刻蚀设备、对设备要求不高，而且可以很好的控制刻蚀截止位置、不会存在刻蚀不够或者过刻蚀的问题，可提高HEMT器件的良率。另外，通过在栅极与异质结构之间设置盖帽层和栅帽层两层膜层，可增大栅极与异质结构之间的距离，从而增大HEMT器件的阈值电压，保障电路的安全。
在一种可能的实施例中，栅帽层的材料为p型AlGaN。
在一种可能的实施例中，栅帽层的材料中掺杂有Mg，Mg的掺杂浓度为1e18-1e21/cm3。
在一种可能的实施例中，栅帽层中Al的质量百分比为10-30％。
在一种可能的实施例中，栅帽层的厚度为10-200nm。由于栅帽层的厚度太大，会增大HEMT器件的厚度，而且会导致异质结构界面处的二维电子气浓度降低，从而会减小输出电流。栅帽层的厚度太小，栅帽层下方电子不能耗尽，则起不到增强型HEMT器件的效果。
在一种可能的实施例中，盖帽层的材料为GaN或者Si3N4。
在一种可能的实施例中，盖帽层的厚度为1-20nm。盖帽层的厚度太小，对势垒层起不到保护作用。盖帽层厚度太大会增大HEMT器件的厚度。
在一种可能的实施例中，HEMT器件还包括源极和漏极；源极和漏极设置在异质结构上，与异质结构形成欧姆接触；源极和漏极露出于盖帽层。
在一种可能的实施例中，异质结构包括沟道层和势垒层；沟道层设置在势垒层靠近衬底一侧。
第二方面，提供一种高电子迁移率晶体管HEMT器件的制备方法，包括：在衬底上形成异质结构；在异质结构上形成盖帽薄膜；在盖帽薄膜上形成栅帽薄膜；栅帽薄膜材料的氧化温度低于盖帽层材料的氧化温度；对栅帽薄膜进行热氧化处理并刻蚀，形成栅帽层；在栅帽层的表面上形成栅极。
本申请实施例提供的HEMT器件中栅帽层材料的氧化温度低于盖帽层材料的氧化温度。因此，采用本申请实施例提供的HEMT器件的制备方法制备HEMT器件的过程中，对栅帽薄膜进行热氧化处理时，盖帽薄膜不会发生氧化反应。在通过碱性溶液对栅帽薄膜被氧化的部分进行刻蚀时，位于栅帽薄膜下方的盖帽薄膜因未被氧化而不会被刻蚀。这样一来，可以精准的控制对栅帽薄膜的刻蚀截止位置，不会刻蚀到位于栅帽薄膜下方的盖帽薄膜。因此，本申请实施例提供的HEMT器件的制备方法工艺方法简单，不依赖于昂贵复杂的刻蚀设备、对设备要求不高，而且可以很好的控制刻蚀截止位置、不会存在刻蚀不够或者过刻蚀的问题，可提高HEMT器件的良率。
在一种可能的实施例中，对栅帽薄膜进行热氧化处理并刻蚀，包括：在栅帽薄膜的表面上形成掩膜图案；其中，掩膜图案与待形成的栅帽层的图案相同；对栅帽薄膜中未被掩膜图案覆盖的部分进行热氧化处理；去除栅帽薄膜中被氧化的部分；去除掩膜图案。
在一种可能的实施例中，栅帽层的材料为p型AlGaN。
在一种可能的实施例中，栅帽层的厚度为10-200nm。
在一种可能的实施例中，盖帽层的材料为GaN或者Si3N4。
在一种可能的实施例中，盖帽层的厚度为1-20nm。
第三方面，提供一种电子设备，包括HEMT器件及天线；HEMT器件用于将射频信号放大后输出至天线向外辐射；其中，HEMT器件为第一方面任一项的HEMT器件。
本申请实施例提供的电子设备，包括第一方面的HEMT器件，其有益效果与HEMT器件的有益效果相同，此处不再赘述。
第四方面，提供一种电子设备，其特征在于，包括HEMT器件及与HEMT器件电连接的印刷电路板；其中，HEMT器件为第一方面任一项的HEMT器件；HEMT器件的衬底为导电型衬底。
本申请实施例提供的电子设备，包括第一方面的HEMT器件，其有益效果与HEMT 器件的有益效果相同，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种基站的结构示意图；
图2为本申请的实施例提供的一种AAU的结构示意图；
图3为本申请的实施例提供的一种充电器的结构示意图；
图4为本申请的实施例提供的一种HEMT器件的制作过程中的结构示意图；
图5为本申请的实施例提供的一种HEMT器件的结构示意图；
图6为本申请的实施例提供的一种HEMT器件的制备过程中的结构示意图；
图7为本申请的实施例提供的一种HEMT器件的制备方法的流程图；
图8为本申请的实施例提供的一种栅帽层的制备过程中的结构示意图。
附图标记：
1-基站；2-充电器；10-衬底；11-基带处理单元；12-有源天线单元；121-计算单元；122-第一传输单元；123-天线单元；1210-控制单元；1211-第二传输单元；1212-基带单元；1213-供电单元；1221-RF单元；1222-PA；20-异质结构；21-沟道层；22-势垒层；30-栅帽层；31-栅帽薄膜；40-成核层；50-渐变缓冲层；60-盖帽层；61-盖帽薄膜。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请实施例中，除非另有明确的规定和限定，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本申请实施例中，例如上、下、左、右、前和后等用于解释本申请中不同部件的结构和运动的方向指示是相对的。当部件处于图中所示的位置时，这些指示是恰当的。但是，如果元件位置的说明发生变化，那么这些方向指示也将会相应地发生变化。
在本申请实施例中，A位于B上，可以理解为，B作为A的承载体。或者理解为，按照膜层的制备顺序，先形成B，后形成A。并不限定为空间上的A位于B的上方，若器件放置角度进行旋转后，虽然在空间上的A不位于B的上方，但是，A依然由B承载，也就是A依然位于B上。
在本申请实施例中，术语“半绝缘(semi-insulating，SI)”指的是：电阻率大于10 5 Ω·cm。例如，半绝缘SiC衬底指的是SiC衬底的电阻率大于10 5Ω·cm。
在本申请实施例中，术语“二维电子气(two-dimensional electron gas，2DEG)”指的是：电子在垂直于界面方向的运动被势阱束缚而被量子化，而其平行于表面的运动仍然是自由的，这样的二维方向的自由电子被称为二维电子气。
在本申请实施例中，术语“电流崩塌效应”指的是：HEMT器件的漏极电压超过一定值时，随着漏极电压的增加，电流开始下降，不能达到理想的值的效应。
在本申请实施例中，术语“质量百分比”即质量分数，是物理学术语，用来表述单位质量的溶液中含有某物质的百分比。
在本申请实施例中，术语“异质结构”即：两种以上不同的半导体材料形成的叠层结构。
本申请实施例提供一种电子设备，该电子设备例如可以为充电器、充电家用小型电器、无人机、航空航天设备、激光雷达驱动器、激光器、探测器、雷达、5G(the 5th generation mobile network，第五代移动通信技术)通信设备等不同类型的用户设备或终端设备；该电子设备也可以为基站等网络设备。本申请实施例对电子设备的具体形式不作特殊限制。
HEMT器件是一种半导体电子器件，由于其具有高击穿电场、高沟道电子浓度、高电子迁移率和高温度稳定性等优点，因而被广泛用于作为射频器件或功率器件。
在HEMT器件用于作为射频器件的情况下，以电子设备为基站为例，对电子设备的结构进行说明。如图1所示，基站1包括基带处理单元(base band unit，BBU)11和有源天线单元(active antenna unit，AAU)12。其中，BBU11主要负责基带数字信号处理，例如，FFT(fast fourier transform，快速傅立叶变换)/IFFT(inverse fast fourier transform，逆快速傅立叶变换)、调制/解调、信道编码/解码等。如图2所示，AAU12包括计算单元121、第一传输单元122和天线单元123。其中，计算单元121包括控制单元1210、第二传输单元1211、基带单元1212和供电单元1213，控制单元1210、第二传输单元1211、基带单元1212和供电单元1213相互电连接，控制单元1210用于负责射频信号的控制，第二传输单元1211用于负责射频信号的传输，基带单元1212用于负责数字信号和模拟信号的转换，基带单元1212例如以是DAC(digital to analog converter，数字模拟转换器)，DAC可以将BBU 11输出的数字信号转换为模拟信号，供电单元1213与电源124电连接，用于为计算单元121中的控制单元1210、第二传输单元1211和基带单元1212供电。第一传输单元122用于负责射频信号的传输和放大。第一传输单元122包括RF(radio frequency，射频)单元1221和PA(power amplifier，功率放大器)1222，RF单元1221用于将模拟信号转化为小功率的射频信号，PA1222用于将小功率的射频信号进行功率放大后输出至天线单元123。天线单元123负责将射频信号向外辐射。如图2所示，AAU12可以包括多个RF单元1221、多个PA1222以及多个天线单元123。需要说明的是，上述PA1222可以为HEMT器件。
应当理解到，在HEMT器件用于作为PA时，本申请实施例提供的电子设备不限于图1和图2所示的基站，任意需要使用功率放大器对信号进行放大的电子设备均属于本申请的实施例的应用场景。
在HEMT器件用于作为功率器件的情况下，以电子设备为充电器为例，对电子设 备的结构进行说明。如图3所示，充电器2可以包括功率器件、电阻R、电感L、电容C等，功率器件例如可以为HEMT器件。其中，HEMT器件、电阻R、电感L和电容C可以通过印刷电路板(printed circuit board，PCB)实现互连。
应当理解到，在HEMT器件用于作为功率器件时，本申请实施例提供的电子设备不限于图3所示的充电器，任意需要使用功率器件的电子设备均属于本申请的实施例的应用场景。
为了缓解耗尽型HEMT器件存在的问题，提供一种增强型(E-Mode)HEMT器件。
增强型HEMT器件与电路的其它部分可以很好地兼容，不需要设计独立的电源系统。而且，HEMT器件应用于电子领域时，耗尽型HEMT器件不仅需要独立的负偏压系统，系统安全性还需要这个负偏压系统的运行先于电源通电。由于增强型HEMT器件不需要设计独立的电源系统，因此可以避免系统启动和模式转换时的导通损坏。再者，增强型HEMT器件为常关型器件，因此可以节省能源。
在一些可选的实施例中，如图4所示，HEMT器件包括衬底10、异质结构20、栅帽层30、源极(source，S)、漏极(drain，D)和栅极(gate，G)。
异质结构20包括沟道层21和势垒层22，沟道层21设置在势垒层22靠近衬底10一侧。或者理解为，沟道层21设置在势垒层22上。沟道层21的材料为GaN，势垒层22的材料为AlGaN。
栅帽层30的材料为P型掺杂的GaN层，栅帽层30的厚度为40-150nm。
HEMT器件的工作原理为：源极S和漏极D分别与势垒层22形成导电欧姆接触，栅极G与势垒层22形成肖特基接触。沟道层21中虚线代表HEMT器件中沟道层21和势垒层22形成的异质结构20中通过极化作用产生的2DEG。2DEG用于在电场的作用下，高效地传导电子。源极S和漏极D用于在电场的作用下使2DEG在源极S和漏极D之间的沟道层21内流动，源极S和漏极D之间的导通发生在沟道层21中的二维电子气处。栅极G设置在源极S和漏极D之间，用于允许或阻碍二维电子气的通过。其中，2DEG具有高导电性，部分原因是因为势阱中的2DEG是处在本征半导体一边，而该处不存在电离杂质中心的散射作用，因此，这些2DEG沿着平面方向运动的迁移率比较高(特别是在较低温度下、晶格振动减弱时)。
而本示例中，栅帽层30可以调节异质结构20的能带结构，使栅帽层30正下方的电子耗尽。如图4所示，2DEG在无偏压的情况下处于夹断状态，2DEG在源极S和漏极D之间的沟道层21内无法连通流动，HEMT器件处于关闭状态。也就是说，HEMT器件为常关器件。
如图4所示，HEMT器件的制备方法包括：
在衬底10上形成异质结构20；在异质结构20的表面上形成P型GaN薄膜；在P型GaN薄膜的表面上形成栅极G；对P型GaN薄膜进行刻蚀；形成源极S和漏极D。
由于栅帽层30的厚度为40-150nm，通常比较薄，而且GaN材料也比较特殊。因此，在对较薄的P型GaN薄膜进行刻蚀时，对刻蚀工艺要求比较高，对粗糙度、均匀性、选择性、腔室控制等方面提出了较高的要求。而且在刻蚀的时候容易出现过刻(将势垒层22也刻蚀)或者刻蚀不够(GaN薄膜没有刻蚀完全，势垒层22未露出)的问题，造成工艺不稳定，器件良率会受影响。
在一些实施例中，为了开发新的刻蚀工艺，采用高精度显微镜(例如电子扫描显微镜或者原子力显微镜)不断的重复检测刻蚀深度，反复的刻蚀，来控制刻蚀精度。这就导致刻蚀工艺复杂，工艺难度大，对刻蚀设备的精度依赖度高的问题，制备得到的产品的良率还比较低。
在一些可选的实施例中，如图5所示，HEMT器件包括衬底10、异质结构20、栅介质层、源极S、漏极D和栅极G。
异质结构20包括沟道层21和势垒层22，沟道层21设置在势垒层22靠近衬底10一侧。或者理解为，沟道层21设置在势垒层22上。沟道层21的材料为GaN，势垒层22的材料为AlGaN。
势垒层22上设置有凹槽，栅介质层覆盖势垒层22，露出源极S和漏极D。栅极G位于势垒层22上凹槽的正上方。
通过在势垒层22上挖凹槽，凹槽位于栅极G的正下方，使得栅极G正下方的2DEG耗尽，沟道层21的其余部分的2DEG浓度不发生变化。因此，2DEG在无偏压的情况下处于夹断状态，2DEG在源极S和漏极D之间的沟道层21内无法连通流动，HEMT器件处于关闭状态。也就是说，HEMT器件为常关器件。
然而，由于这种通过设置凹槽使凹槽正下方的2DEG耗尽的结构中，凹槽槽底到沟道层21的厚度一般仅预留3-5nm以下。也就是说，势垒层22的厚度一般需刻蚀减小到3-5nm以下。将刻蚀精度控制在这么高，工艺难度比较大、对刻蚀设备依赖度高。由于受工艺限制，凹槽槽底到沟道层21的厚度是一个波动值，导致HEMT器件的夹断电压也会波动很大。此外，这种结构的夹断效果有限，在零偏置时会有少量漏电。因为漏电的存在，导致HEMT器件在高电压环境中容易烧毁。
为了缓解上述制作HEMT器件存在的问题，本申请实施例提供一种HEMT器件，该HEMT器件可以应用于上述的电子设备中。
以下，对HEMT器件的结构及其制备方法进行示例性介绍。
如图6所示，HEMT器件包括衬底10、成核层40、渐变缓冲层50、异质结构20、盖帽层60、栅帽层30、源极S、漏极D以及栅极G。
如图7所示，HEMT器件的制备方法包括：
S10、如图6所示，在衬底10上形成成核层40。
也就是说，如图6所示，成核层40设置在衬底10上。例如，成核层40设置在衬底10的表面上。
其中，形成成核层40的方法，例如可以通过金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。
成核层40的材料，例如可以包括GaN、AlGaN、氮化铝(AlN)中一种或多种。
此处，成核层40可以提供成核中心，促进渐变缓冲层50的外延生长。
另外，可以理解的是，在HEMT器件用于作为射频器件时，上述衬底10为半绝缘衬底。在HEMT器件用于作为功率器件时，上述衬底10为导电型衬底。
在一些实施例中，上述衬底10为金刚石衬底或碳化硅(SiC)衬底。
其中，在上述衬底10为SiC衬底的情况下，在原料纯度不高的情况下，生长得到 的SiC衬底是导电型衬底。在原料纯度较高的情况下，生长得到的SiC衬底是半绝缘衬底。
在上述衬底10为金刚石衬底的情况下，正常生长形成的金刚石衬底为半绝缘衬底。在形成金刚石衬底的过程中，当杂质含量较高或者掺杂时，形成的金刚石衬底为导电型衬底。
金刚石衬底的热导率一般为1000W·m -1·K -1～2000W·m -1·K -1，SiC衬底的热导率一般为370W·m -1·K -1左右。当衬底10为金刚石衬底或SiC衬底时，衬底10的散热能力较高，从而可以提高HEMT器件的散热能力。
S20、如图6所示，在成核层40上形成渐变缓冲层50。
或者理解为，在成核层40远离衬底10一侧形成渐变缓冲层50。
也就是说，如图6所示，渐变缓冲层50设置在成核层40远离衬底10一侧。例如，渐变缓冲层50设置在成核层40远离衬底10的表面上。
其中，形成渐变缓冲层50的方法，例如可以采用MOCVD工艺外延生长Al(铝)组分逐渐降低的AlGaN渐变层。
示例的，通过MOCVD工艺，在成核层40远离衬底10一侧依次形成Al 0.8Ga 0.2N层、Al 0.5Ga 0.5N层、Al 0.2Ga 0.8N层，以形成渐变缓冲层50。
另外，可以理解的是，HEMT器件用于作为射频器件时，上述渐变缓冲层50的成分，和，HEMT器件用于作为功率器件时，上述渐变缓冲层50的成分不同。
S30、如图6所示，在渐变缓冲层50上形成异质结构20。
或者理解为，在渐变缓冲层50远离衬底10一侧形成异质结构20。
通过上述描述可知，成核层40和渐变缓冲层50均形成在衬底10上。因此，在渐变缓冲层50远离衬底10一侧形成的异质结构20，也位于衬底10上。
如图6所示，异质结构20包括沟道层21和势垒层22。沟道层21设置在势垒层22靠近衬底10一侧，也就是沟道层21设置在势垒层22靠近渐变缓冲层50一侧。例如，沟道层21设置在渐变缓冲层50朝向势垒层22的表面上。
基于此，在衬底10上形成异质结构20包括，在衬底10上依次形成沟道层21和势垒层22。
其中，形成沟道层21和势垒层22的方法，例如可以通过MOCVD生长法或MBE生长法等。
上述沟道层21的材料例如可以包括GaN、AlGaN、铟氮化铝(InAlN)、AlN、钪氮化铝(ScAlN)中一种或多种。
上述势垒层22的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。
其中，沟道层21和势垒层22的材料不相同。
示例的，沟道层21的材料包括GaN，势垒层22的材料包括AlGaN。
S40、如图6所示，在异质结构20上形成盖帽薄膜61。
或者理解为，在异质结构20远离衬底10一侧形成盖帽薄膜61。
也就是说，盖帽薄膜61设置在异质结构20上。例如，盖帽薄膜61设置在异质结构20远离衬底10的表面上。
其中，形成盖帽薄膜61的方法，例如可以采用MOCVD生长法或MBE生长法形成盖帽薄膜61。
在一些实施例中，盖帽薄膜61的材料例如可以为GaN或者氮化硅(Si 3N 4)。
盖帽层60的厚度太小，对势垒层22起不到保护作用。盖帽层60厚度太大会增大HEMT器件的厚度。因此，在一些实施例中，盖帽薄膜61的厚度例如可以为1-20nm。示例的，盖帽薄膜61的厚度为2nm、3nm、4nm、5nm、8nm、10nm、12nm、15nm、18nm。
S50、如图6所示，在盖帽薄膜61上形成栅帽层30。
或者理解为，在盖帽薄膜61远离衬底10一侧形成栅帽层30。
也就是说，栅帽层30设置在盖帽薄膜61上。例如，栅帽层30设置在盖帽薄膜61远离衬底10的表面上。
其中，栅帽层30用于调节异质结构20的能带结构，使栅帽层30正下方的电子耗尽。使得HEMT器件中2DEG在无偏压的情况下处于夹断状态，2DEG在源极S和漏极D之间的沟道层21内无法连通流动，HEMT器件处于关闭状态，使得HEMT器件为常关器件。
关于形成栅帽层30的方法，在一些实施例中，包括：在盖帽薄膜61上形成栅帽薄膜31，对栅帽薄膜31进行热氧化处理并刻蚀，形成栅帽层30。
示例的，如图8所示，形成栅帽层30的方法，包括：
S51、在盖帽薄膜61上形成栅帽薄膜31。
或者理解为，在盖帽薄膜61远离衬底10一侧形成栅帽薄膜31。
例如可以采用MOCVD生长法或MBE生长法形成栅帽薄膜31。
在一些实施例中，栅帽薄膜31的材料例如可以为p型AlGaN，例如可以在生长AlGaN的过程中掺杂镁(Mg)元素，以形成p型AlGaN的栅帽薄膜31。掺杂浓度可以控制在1e18-1e21/cm3，例如掺杂浓度为1e19/cm3、1e20/cm3。栅帽薄膜31中铝(Al)的质量百分比可以控制在10-30％，例如，Al的质量百分比为15％、20％、25％。
或者，在一些实施例中，栅帽薄膜31的材料例如可以为AlN。
当然，上述栅帽薄膜31的材料仅为一种示意，栅帽薄膜31材料的氧化温度低于盖帽薄膜61材料的氧化温度即可。
其中，栅帽薄膜31材料的氧化温度是指栅帽薄膜31的材料发生氧化反应的最低温度。同理，盖帽薄膜61材料的氧化温度是指盖帽薄膜61的材料发生氧化反应的最低温度。
由于栅帽层30的厚度太大，会增大HEMT器件的厚度，而且会导致异质结构20界面处的二维电子气浓度降低，从而会减小输出电流。栅帽层30的厚度太小，栅帽层30下方电子不能耗尽，则起不到增强型HEMT器件的效果。因此，在一些实施例中，栅帽薄膜31的厚度例如可以为10-200nm。例如，栅帽薄膜31的厚度为30nm、50nm、80nm、100nm、130nm、150nm、180nm。
S52、在栅帽薄膜31的表面上形成掩膜图案。
或者理解为，在栅帽薄膜31远离衬底10的表面上形成掩膜图案。其中，掩膜图案与待形成的栅帽层的图案相同，掩膜图案例如可以是光刻胶。
S53、对栅帽薄膜31中未被掩膜图案覆盖的部分进行热氧化处理。
由于栅帽薄膜31材料的氧化温度低于盖帽薄膜61材料的氧化温度，因此，在对栅帽薄膜31进行热氧化处理时，所处的温度不足以使盖帽薄膜61氧化。也就是说，对栅帽薄膜31进行热氧化处理时，盖帽薄膜61不会被氧化。
在对栅帽薄膜31进行热氧化处理的过程中，通入足够的氧气，保证栅帽薄膜31充分的氧化，而盖帽薄膜61不会被氧化。
示例的，栅帽薄膜31的材料为p型AlGaN，盖帽薄膜61的材料为GaN。550-650℃的温度条件下AlGaN比GaN更容易被氧化，GaN不会被氧化。当温度继续升高到800℃时，AlGaN和GaN都可以被氧化。也就是说，栅帽薄膜31的材料的氧化温度为550℃，盖帽薄膜61的材料的氧化温度为800℃。
其中，
Figure PCTCN2021100648-appb-000001
AlGaN比GaN更容易被氧化主要是因为，反应得到Al 2O 3的Gibbs自由能变化，比反应得到Ga 2O 3的自由能变化大。
因此，将热氧化处理温度控制在550-650℃，时间例如可以是30-60min，热氧化处理的过程中通入足够的氧气，保障p型AlGaN充分氧化。在这种条件下，AlGaN和氧气反应生成Al 2O 3和Ga 2O 3。
S54、去除栅帽薄膜31中被氧化的部分。
例如，可以通过碱性溶液对氧化后的栅帽薄膜31进行刻蚀。
示例的，Al 2O 3和Ga 2O 3可被70°的氢氧化钾(KOH)溶液蚀刻掉。而且由于栅帽薄膜31几乎未被氧化，在KOH溶液对Al 2O 3和Ga 2O 3刻蚀的过程中，基本不会对栅帽薄膜31进行刻蚀，这种刻蚀的方法对栅帽薄膜31影响比较小。
S55、去除掩膜图案，以形成栅帽层30。
通过上述对栅帽薄膜31的描述可知，栅帽层30的材料例如可以为p型AlGaN，栅帽层30的材料中，Mg掺杂的浓度范围为1e18-1e21/cm3，Al的质量百分比为10-30％。栅帽层30材料的氧化温度低于盖帽层60材料的氧化温度。栅帽层30的厚度例如可以为10-200nm。
其中，不对栅帽层30的截面形状进行限定，例如可以是矩形、梯形、倒梯形、沙漏型或者腰鼓型等，栅帽层30在衬底10上的正投影位于盖帽薄膜61在衬底10上的正投影内即可。也就是说，栅帽层30的图案小于盖帽薄膜61的图案。或者理解为，栅帽层30露出盖帽薄膜61远离衬底10的表面。
S60、如图6所示，对盖帽薄膜61进行刻蚀，形成盖帽层60。
例如，在盖帽薄膜61上刻蚀出用于设置源极S和漏极D的开口，盖帽薄膜61上的开口露出位于盖帽薄膜61下方的势垒层22。
通过在势垒层22上形成盖帽层60，可对势垒层22起到保护作用，防止势垒层22表面被氧化，可降低HEMT器件表面态。即，降低HEMT器件的导通电阻，从而降低HEMT器件的栅极漏电、厚度太小效应以及功耗，提高HEMT器件的可靠性。
在一些实施例中，如图6所示，刻蚀盖帽薄膜61，形成开口，以制作源极S和漏极D时，会对势垒层22进行少量刻蚀。也就是说，最终势垒层22上会有凹陷部。
这样一来，源极S和漏极D和势垒层22上的凹陷部(Recess)可以形成新的欧姆 接触表面，有利于源极S和漏极D与势垒层22表面形成的TiN(氮化钛)的扩散，形成第二条导电通道，有效的降低欧姆接触电阻。另外，采用在势垒层22上形成凹陷部的结构，能有效的提高漏极D最大电流，降低HEMT器件的导通电阻。
S70、如图6所示，在盖帽层60的开口处形成源极S和漏极D。
盖帽层60的开口露出势垒层22，那么在盖帽层60的开口处形成源极S和漏极D，相当于源极S和漏极D设置在异质结构20中的势垒层22上，源极S和漏极D与异质结构20中的势垒层22形成欧姆接触，且源极S和漏极D露出于盖帽层60。
其中，源极S和漏极D可以同步形成。
此外，源极S、漏极D的材料可以为依次层叠的钛(Ti)层、Al层、镍(Ni)层和金(Au)层，即Ti/Al/Ni/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、Al层、铂(Pt)层和Au层，即Ti/Al/Pt/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、钽(Ta)层和Ti层，即Ti/Ta/Ti。或者源极S、漏极D的材料可以为Au或者钯(Pd)。
S80、如图6所示，在栅帽层30的表面上形成栅极G。
或者理解为，在栅帽层30远离衬底10的表面上形成栅极G。
也就是说，栅极G设置在栅帽层30的表面上。
可以理解的是，栅极G设置在栅帽层30的表面上，那么栅极G的图案小于或者等于栅帽层30的图案。即，栅极G在衬底10上的正投影位于栅帽层30在衬底10上的正投影内。或者，栅极G在衬底10上的正投影与栅帽层30在衬底10上的正投影重合。
栅极G的材料例如可以是Au或者钯(Pd)。
需要说明的是，此处，可以同时形成源极S、漏极D和栅极D。也可以先同时形成源极S和漏极D，再形成栅极G。还可以先形成栅极G，再同时形成源极S和漏极D。
本申请实施例提供的HEMT器件中栅帽层30材料的氧化温度低于盖帽层60材料的氧化温度。因此，采用本申请实施例提供的HEMT器件的制备方法制备HEMT器件的过程中，对栅帽薄膜31进行热氧化处理时，盖帽薄膜61不会发生氧化反应。在通过碱性溶液对栅帽薄膜31被氧化的部分进行刻蚀时，位于栅帽薄膜31下方的盖帽薄膜61因未被氧化而不会被刻蚀。这样一来，可以精准的控制对栅帽薄膜31的刻蚀截止位置，不会刻蚀到位于栅帽薄膜31下方的盖帽薄膜61。因此，本申请实施例提供的HEMT器件的制备方法工艺方法简单，不依赖于昂贵复杂的刻蚀设备、对设备要求不高，而且可以很好的控制刻蚀截止位置、不会存在刻蚀不够或者过刻蚀的问题，可提高HEMT器件的良率。
另外，通过在栅极G与异质结构20之间设置盖帽层60和栅帽层30两层膜层，可增大HEMT器件的阈值电压的稳定性。同时能保护好HEMT器件表面，可以有效抑制电流崩塌效应。
在一些实施例中，衬底10以及衬底10与源极S之间的膜层上还设置有通孔。
HEMT器件之间并联时，可在衬底10的远离异质结构20一侧形成转接部，转接部通过HEMT器件中的上述通孔与HEMT器件的源极S耦接，以实现HEMT器件之 间并联耦接。
或者，与源极S耦接的电子器件位于衬底10的远离异质结构20一侧时，可在衬底10的远离异质结构20一侧形成转接部，转接部通过HEMT器件中的上述通孔与HEMT器件的源极S耦接，转接部还与衬底10的远离异质结构20一侧的电子器件耦接，以实现HEMT器件与电子器件的耦接。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种高电子迁移率晶体管HEMT器件，其特征在于，包括：
    衬底；
    异质结构，设置在所述衬底上；
    盖帽层，设置在所述异质结构上；
    栅帽层，设置在所述盖帽层上；所述栅帽层材料的氧化温度低于所述盖帽层材料的氧化温度；
    栅极，设置在所述栅帽层上。
  2. 根据权利要求1所述的HEMT器件，其特征在于，所述栅帽层的材料为p型AlGaN。
  3. 根据权利要求2所述的HEMT器件，其特征在于，所述栅帽层的材料中掺杂有Mg，Mg的掺杂浓度为1e18-1e21/cm3；
    和/或，
    所述栅帽层中Al的质量百分比为10-30％。
  4. 根据权利要求1或2所述的HEMT器件，其特征在于，所述栅帽层的厚度为10-200nm。
  5. 根据权利要求1-4任一项所述的HEMT器件，其特征在于，所述盖帽层的材料为GaN或者Si 3N 4。
  6. 根据权利要求1-5任一项所述的HEMT器件，其特征在于，所述盖帽层的厚度为1-20nm。
  7. 根据权利要求1-6任一项所述的HEMT器件，其特征在于，所述HEMT器件还包括源极和漏极；
    所述源极和所述漏极设置在所述异质结构上，与所述异质结构形成欧姆接触；所述源极和所述漏极露出于所述盖帽层。
  8. 一种高电子迁移率晶体管HEMT器件的制备方法，其特征在于，包括：
    在衬底上形成异质结构；
    在异质结构上形成盖帽薄膜；
    在所述盖帽薄膜上形成栅帽薄膜；所述栅帽薄膜材料的氧化温度低于所述盖帽层材料的氧化温度；
    对所述栅帽薄膜进行热氧化处理并刻蚀，形成栅帽层；
    在栅帽层的表面上形成栅极。
  9. 根据权利要求8所述的HEMT器件的制备方法，其特征在于，对所述栅帽薄膜进行热氧化处理并刻蚀，包括：
    在所述栅帽薄膜的表面上形成掩膜图案；其中，所述掩膜图案与待形成的所述栅帽层的图案相同；
    对所述栅帽薄膜中未被所述掩膜图案覆盖的部分进行热氧化处理；
    去除所述栅帽薄膜中被氧化的部分；
    去除所述掩膜图案。
  10. 根据权利要求8或9所述的HEMT器件的制备方法，其特征在于，所述栅帽 层的材料为p型AlGaN。
  11. 根据权利要求8-10任一项所述的HEMT器件的制备方法，其特征在于，所述栅帽层的厚度为10-200nm。
  12. 根据权利要求8-11任一项所述的HEMT器件的制备方法，其特征在于，所述盖帽层的材料为GaN或者Si 3N 4。
  13. 根据权利要求8-12任一项所述的HEMT器件的制备方法，其特征在于，所述盖帽层的厚度为1-20nm。
  14. 一种电子设备，其特征在于，包括HEMT器件及天线；所述HEMT器件用于将射频信号放大后输出至所述天线向外辐射；
    其中，所述HEMT器件为如权利要求1-7任一项所述的HEMT器件。
  15. 一种电子设备，其特征在于，包括HEMT器件及与所述HEMT器件电连接的印刷电路板；
    其中，所述HEMT器件为如权利要求1-7任一项所述的HEMT器件；所述HEMT器件的衬底为导电型衬底。
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