WO2023197213A1 - 半导体器件及其工作方法、电子设备 - Google Patents

半导体器件及其工作方法、电子设备 Download PDF

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Publication number
WO2023197213A1
WO2023197213A1 PCT/CN2022/086659 CN2022086659W WO2023197213A1 WO 2023197213 A1 WO2023197213 A1 WO 2023197213A1 CN 2022086659 W CN2022086659 W CN 2022086659W WO 2023197213 A1 WO2023197213 A1 WO 2023197213A1
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Prior art keywords
layer
semiconductor device
hole injection
injection layer
substrate
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PCT/CN2022/086659
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English (en)
French (fr)
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鲁微
马俊彩
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华为技术有限公司
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Priority to PCT/CN2022/086659 priority Critical patent/WO2023197213A1/zh
Publication of WO2023197213A1 publication Critical patent/WO2023197213A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device, its working method, and electronic equipment.
  • semiconductor devices with high thermal conductivity, high temperature resistance, wide band gap, high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and stable chemical properties are widely used in radio frequency devices and power electronic devices.
  • semiconductor devices are prone to current collapse and static current drops, thus affecting the performance of semiconductor devices.
  • Embodiments of the present application provide a semiconductor device, a working method thereof, and electronic equipment for improving the performance of the semiconductor device.
  • a first aspect of the embodiment of the present application provides a semiconductor device.
  • the semiconductor device can be used as a radio frequency device or a power device.
  • the semiconductor device includes a substrate; a channel layer and a barrier layer, which are stacked in sequence on one side of the substrate; a gate, a source, a drain and a first hole injection layer, which are arranged on a side of the barrier layer away from the substrate;
  • the gate electrode is located between the source electrode and the drain electrode; part of the bottom surface of the gate electrode covers the top surface of the first hole injection layer, and part of the bottom surface of the gate electrode is in contact with the barrier layer.
  • the substrate is a conductive substrate
  • the semiconductor device can be used as a power device.
  • the semiconductor device can be used as a radio frequency device.
  • the semiconductor device when the semiconductor device is in the on state, under the action of the gate high voltage, the first hole injection layer injects holes into the surface of the barrier layer and into the channel, and the holes are balanced to be captured by traps on the surface of the material or in the body.
  • the electrons quickly recover the two-dimensional electron gas channel exhausted by the trapped electrons, thus suppressing current collapse and static current drop problems.
  • the first hole injection layer has a depletion effect on the two-dimensional electron gas below the first hole injection layer, because part of the structure of the gate directly forms Schottky contact with the barrier layer, the The signal can be directly transmitted into the channel without being affected by the first hole injection layer. Therefore, the semiconductor device provided in this example can suppress current collapse and static current drop.
  • the gate electrode covers the top surface and side surfaces of the first hole injection layer.
  • the gate electrode covers the top surface and side surfaces of the first hole injection layer.
  • the gate electrode covers part of the top surface of the first hole injection layer.
  • the semiconductor device further includes a second hole injection layer, the second hole injection layer is disposed on a side of the barrier layer away from the substrate; the drain electrode wraps the second hole injection layer. The drain electrode is wrapped around the second hole injection layer. Then, the second hole injection layer is in direct contact with the drain electrode to form equipotential coupling, and part of the structure of the drain electrode is located on the side of the second hole injection layer close to the gate electrode. In this way, when the semiconductor device is in the off state, the drain high voltage causes the second hole injection layer to inject holes into the surface of the barrier layer and into the channel, modulating the electric field between the gate and the drain to reduce the channel electrons being absorbed by the material.
  • the second hole injection layer has a depletion effect on the two-dimensional electron gas below the second hole injection layer.
  • the current in the semiconductor device can enter the drain through the drain structure on the side of the second hole injection layer close to the gate without passing through A two-dimensional electron gas depletion region beneath the second hole injection layer.
  • the semiconductor device provided in this example achieves the function of suppressing current collapse and static current drop without affecting the on-state on-resistance of the semiconductor device.
  • the semiconductor device provided by the embodiment of the present application can be applied to radio frequency devices and power devices.
  • the drain electrode includes an ohmic contact layer and a thickened electrode layer; the first hole injection layer is disposed on the surface of the barrier layer. A way to achieve it.
  • the drain electrode includes an ohmic contact layer and a thickened electrode layer; the first hole injection layer is disposed between the ohmic contact layer and the thickened electrode layer. A way to achieve it.
  • the first hole injection layer includes a plurality of spaced-apart block structures.
  • the gate electrode is filled between adjacent block structures, which can increase the contact area between the gate electrode and the barrier layer, and the contact effect between the gate electrode and the barrier layer is good.
  • the first hole injection layer has a planar structure.
  • the planar first hole injection layer can inject more holes and has a better effect of suppressing current collapse and static current drop.
  • the second hole injection layer includes a plurality of spaced-apart block structures. In this way, the drain electrode is filled between adjacent block structures, which can increase the contact area between the drain electrode and the barrier layer, and the contact resistance between the drain electrode and the barrier layer is small.
  • the second hole injection layer has a planar structure.
  • the planar second hole injection layer can inject more holes and has a better effect of suppressing current collapse and static current drop.
  • the semiconductor device further includes an insulating layer disposed between the gate electrode and the barrier layer, and the insulating layer is located on the periphery of the first hole injection layer and the drain electrode.
  • the semiconductor device may be a MISFET device.
  • the material of the first hole injection layer includes a P-type semiconductor material.
  • a second aspect of the embodiment of the present application provides a semiconductor device, including: a substrate; a channel layer and a barrier layer, which are sequentially stacked on one side of the substrate; a gate electrode, a source electrode, a drain electrode, and a second hole
  • the injection layer is arranged on the side of the barrier layer away from the substrate; the gate electrode is located between the source electrode and the drain electrode; the drain electrode wraps the second hole injection layer.
  • the drain high voltage causes the second hole injection layer to inject holes into the surface of the barrier layer and into the channel, modulating the electric field between the gate and the drain to reduce The probability of channel electrons being captured by material traps, and balancing the electrons captured by material traps (surface or body traps), so that the channel depleted of trapped electrons can quickly recover to reduce the sensitivity of the channel current to the off-state drain voltage degree, thus playing the role of suppressing current collapse and static current drop during the switching process of semiconductor devices.
  • the second hole injection layer has a depletion effect on the two-dimensional electron gas below the second hole injection layer.
  • the semiconductor device provided in this example achieves the function of suppressing current collapse and static current drop without affecting the on-state on-resistance of the semiconductor device.
  • the semiconductor device provided by the embodiment of the present application can be applied to radio frequency devices and power devices.
  • the semiconductor device further includes a third hole injection layer, the gate electrode is disposed on the third hole injection layer, and the bottom surface of the gate electrode is in contact with the third hole injection layer.
  • the semiconductor device may be an enhancement mode semiconductor device.
  • the semiconductor device further includes an insulating layer, the insulating layer is disposed between the gate electrode and the barrier layer, and the insulating layer is located around the drain electrode.
  • the semiconductor device may be a MISFET device.
  • a third aspect of the embodiment of the present application provides an electronic device, including a semiconductor device and an antenna; the semiconductor device is used to amplify the radio frequency signal and output it to the antenna for external radiation; wherein the semiconductor device is any one of the first aspect or the third aspect.
  • Semiconductor devices in either of the two aspects.
  • the electronic device provided in the third aspect of the embodiment of the present application includes the semiconductor device of the first aspect or the second aspect, and its beneficial effects are the same as those of the semiconductor device, which will not be described again here.
  • a fourth aspect of the embodiments of the present application provides an electronic device, including a semiconductor device and a printed circuit board electrically connected to the semiconductor device; wherein the semiconductor device is a semiconductor according to any one of the first aspect or any one of the second aspect. device.
  • the electronic device provided in the fourth aspect of the embodiment of the present application includes the semiconductor device of the first aspect or the second aspect, and its beneficial effects are the same as those of the semiconductor device, which will not be described again here.
  • a fifth aspect of the embodiment of the present application provides a working method of a semiconductor device, including a semiconductor device.
  • the semiconductor device includes a substrate; a channel layer and a barrier layer, which are sequentially stacked on one side of the substrate; a gate electrode, and a source electrode. , the drain electrode and the first hole injection layer are arranged on the side of the barrier layer away from the substrate; the gate electrode is located between the source electrode and the drain electrode; part of the bottom surface of the gate electrode covers the top surface of the first hole injection layer , part of the bottom surface of the gate is in contact with the barrier layer; the working method of the semiconductor device includes: the first hole injection layer receives the signal from the gate and injects holes into the barrier layer.
  • the semiconductor device further includes a second hole injection layer, which is disposed on a side of the barrier layer away from the substrate; the drain electrode wraps the second hole injection layer;
  • the working method also includes: the second hole injection layer receives the signal from the drain and injects holes into the barrier layer.
  • the sixth aspect of the embodiment of the present application provides a working method of a semiconductor device, including a semiconductor device, a substrate; a channel layer and a barrier layer, which are sequentially stacked on one side of the substrate; a gate electrode, a source electrode, and a drain electrode. and a second hole injection layer, which is disposed on the side of the barrier layer away from the substrate; the gate electrode is located between the source electrode and the drain electrode; the drain electrode wraps the second hole injection layer; the working method of the semiconductor device also includes: second The hole injection layer receives the signal from the drain and injects holes into the barrier layer.
  • Figure 1A is a schematic structural diagram of a base station provided by an embodiment of the present application.
  • Figure 1B is a schematic structural diagram of an active antenna unit provided by an embodiment of the present application.
  • FIG. 1C is a schematic structural diagram of a charger provided by an embodiment of the present application.
  • 2A-2D are schematic structural diagrams of a semiconductor device provided by embodiments of the present application.
  • Figure 3A is a schematic top view of a semiconductor device provided by an embodiment of the present application.
  • Figure 3B is a cross-sectional view along the A1-A2 direction in Figure 3A;
  • FIG. 3C is a schematic top view of another semiconductor device provided by an embodiment of the present application.
  • Figure 3D is another cross-sectional view along the A1-A2 direction in Figure 3A;
  • Figure 3E is another cross-sectional view along the A1-A2 direction in Figure 3A;
  • Figure 3F is a schematic structural diagram of another semiconductor device
  • FIG. 4A is a schematic top view of another semiconductor device provided by an embodiment of the present application.
  • Figure 4B is a cross-sectional view along the B1-B2 direction in Figure 4A;
  • FIG. 4C is a schematic top view of another semiconductor device provided by an embodiment of the present application.
  • Figure 4D is a schematic structural diagram of another semiconductor device
  • Figure 4E is a schematic structural diagram of another semiconductor device
  • Figures 5A-5B are schematic structural diagrams of yet another semiconductor device
  • Figure 6 is a schematic structural diagram of another semiconductor device
  • Figure 7A is a schematic structural diagram of yet another semiconductor device
  • FIG. 7B is a schematic structural diagram of yet another semiconductor device.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Si-insulating refers to a resistivity greater than 10 5 ⁇ cm.
  • a semi-insulating SiC substrate means that the resistivity of the SiC substrate is greater than 10 5 ⁇ cm.
  • two-dimensional electron gas 2DEG
  • 2DEG two-dimensional electron gas
  • the term "current collapse phenomenon” refers to: when the semiconductor device changes from the off state to the on state, the trapped electrons have not had time to be released from the trap, and the electrons in the channel are still trapped.
  • the state of electron depletion causes the channel conductivity to decrease and the current to decrease.
  • the current collapse phenomenon is intuitively manifested as the phenomenon that when the off-state voltage is applied to a semiconductor device for a certain period of time, the channel current decreases at the moment when the semiconductor device is turned on.
  • the term "quiescent current (Idq) drop” refers to: when a semiconductor device is used as a radio frequency device, a certain static DC current Idq is applied to the semiconductor device to improve the linearity characteristics of the device, and the device receives After the radio frequency signal (RF on) starts working, the radio frequency signal ends (RF off) after a period of time. At this time, the static current will drop, which will cause the linearity of the device to deteriorate the next time it works (RF on). It needs to be Idq after a certain period of time. will return to the initial value. This drop phenomenon is the static current drop.
  • the quiescent current drop is also related to some defect traps in semiconductor devices. Electrons trapped during the switching process of radio frequency signals (RF) cannot recover quickly.
  • Embodiments of the present application provide an electronic device.
  • the electronic device may be, for example, a charger, a small charging household appliance, a drone, a lidar driver, a laser, a detector, a radar, the fifth generation mobile network technology , 5G) communication equipment and other different types of user equipment or terminal equipment; the electronic equipment can also be network equipment such as base stations.
  • the electronic equipment may also be a device such as a power amplifier used in the above-mentioned electronic equipment.
  • the embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
  • the third-generation semiconductor gallium nitride (GaN) material has excellent characteristics, such as a large band gap (3.4eV), a high breakdown electric field (3.3MV/cm), and a large saturation rate (2.5e7cm/ s), and the high density of 2DEG at the aluminum gallium nitride (AlGaN)/GaN heterostructure interface caused by the polarization effect, making AlGaN/GaN prepared on silicon carbide (SiC) substrates or silicon (Si) substrates with high Electron mobility transistor (high-electron-mobility transistor, HEMT) devices can operate at higher voltages, higher temperatures and higher frequencies, and are therefore widely used as radio frequency devices or power devices.
  • a large band gap 3.4eV
  • 3.3MV/cm high breakdown electric field
  • 2.5e7cm/ s large saturation rate
  • 2DEG at the aluminum gallium nitride (AlGaN)/GaN heterostructure interface caused by the polarization effect, making
  • the base station 1 includes a baseband processing unit (base band unit, BBU) 11 and an active antenna unit (active antenna unit, AAU) 12.
  • BBU11 is mainly responsible for baseband digital signal processing, such as FFT (fast fourier transform, fast Fourier transform)/IFFT (inverse fast fourier transform, inverse fast Fourier transform), modulation/demodulation, channel coding/decoding, etc.
  • AAU 12 includes a calculation unit 121 , a first transmission unit 122 and an antenna unit 123 .
  • the computing unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212 and a power supply unit 1213.
  • the control unit 1210, the second transmission unit 1211, the baseband unit 1212 and the power supply unit 1213 are electrically connected to each other.
  • the control unit 1210 is used to Responsible for the control of radio frequency signals.
  • the second transmission unit 1211 is responsible for the transmission of radio frequency signals.
  • the baseband unit 1212 is responsible for the conversion of digital signals and analog signals.
  • the baseband unit 1212 is, for example, a DAC (digital to analog converter, digital to analog converter). ), the DAC can convert the digital signal output by the BBU 11 into an analog signal.
  • the power supply unit 1213 is electrically connected to the power supply 124 and is used to power the control unit 1210, the second transmission unit 1211 and the baseband unit 1212 in the computing unit 121.
  • the first transmission unit 122 is responsible for the transmission and amplification of radio frequency signals.
  • the first transmission unit 122 includes an RF (radio frequency, radio frequency) unit 1221 and a PA (power amplifier) 1222.
  • the RF unit 1221 is used to convert the analog signal into a low-power radio frequency signal
  • the PA 1222 is used to convert the low-power radio frequency signal into a low-power radio frequency signal.
  • the signal is power amplified and then output to the antenna unit 123 .
  • the antenna unit 123 is responsible for radiating radio frequency signals outward.
  • the AAU 12 may include multiple RF units 1221 , multiple PAs 1222 , and multiple antenna units 123 . It should be noted that the above-mentioned PA1222 can be a semiconductor device.
  • the electronic equipment provided by the embodiment of the present application is not limited to the base station shown in FIG. 1A and FIG. 1B , and any electronic equipment that needs to use a power amplifier to amplify the signal belongs to the present application.
  • the electronic device When the semiconductor device is used as a power device, the electronic device is used as a charger as an example to describe the structure of the electronic device.
  • the charger 2 may include a power device, a resistor R, an inductor L, a capacitor C, etc.
  • the power device may be a semiconductor device, for example.
  • the semiconductor device, resistor R, inductor L and capacitor C can be interconnected through a printed circuit board (PCB).
  • PCB printed circuit board
  • the electronic device provided by the embodiment of the present application is not limited to the charger shown in FIG. 1C. Any electronic device that requires the use of a power device belongs to the application scenarios of the embodiment of the present application. .
  • the AlGaN/GaN heterojunction When the AlGaN/GaN heterojunction is fabricated on a SiC or Si substrate, there is a mismatch between the crystal lattice of the AlGaN/GaN heterojunction and the crystal lattice of the substrate, resulting in defects in the AlGaN/GaN heterojunction material.
  • the density is high, and the semiconductor devices produced therefrom have obvious current collapse problems.
  • the principle of current collapse is that when the semiconductor device is turned off, under the action of the gate high field, the electrons in the channel are captured by defect traps on the surface of the AlGaN/GaN heterojunction or in the buffer layer material below the heterojunction.
  • a certain quiescent current (Idq) is usually set to ensure the linearity of the amplification factor.
  • Idq quiescent current
  • a common problem is that when the RF device is subjected to RF stress for a period of time, the quiescent current will drop significantly. It will take some time to return to the set value.
  • Static current sag is a physical phenomenon similar to current collapse. Static current sag is also related to some defect traps in radio frequency devices. Electrons captured during the switching process of radio frequency signals (RF) cannot recover quickly. The magnitude of the quiescent current drop and the recovery time are related to the density and type of defects in the material.
  • the quiescent current drop will make the pre-distortion (digital pre-distortion, DPD) calibration of the system linearity difficult or even impossible to correct.
  • DPD digital pre-distortion
  • a semiconductor device is provided. As shown in FIG. 2A , the semiconductor device includes a substrate, a buffer layer, a channel layer and a barrier layer that are sequentially stacked on the substrate. The channel layer and the barrier layer are Heterojunctions that form semiconductor devices.
  • the semiconductor device also includes a source S, a drain D, and a gate G. The gate G forms Schottky contact with the barrier layer, and the source S and drain D form ohmic contact with the barrier layer.
  • the semiconductor device also includes a passivation layer and a field plate (FP).
  • the passivation layer is provided on the surface of the barrier layer.
  • the field plate is disposed above the gate G, the field plate is located on the side of the gate G close to the drain D, and the field plate is coupled to the source S. And in the direction perpendicular to the substrate, the field plate overlaps the gate G.
  • a passivation layer is formed on the surface of the barrier layer through a chemical vapor deposition (CVD) process.
  • the material of the passivation layer may be, for example, silicon nitride (SiN) or silicon oxide (SiO).
  • the passivation effect of the passivation layer can weaken the trapping effect of surface traps of the barrier layer on electrons in the channel, thereby inhibiting current collapse and static current drop.
  • a field plate is formed above the passivation layer on the side of the gate G close to the drain D.
  • the existence of the field plate structure can weaken the electric field intensity at the edge of the gate G and under the field plate (between the gate G and the drain D). After the electric field is weakened, electrons in the channel are less likely to be captured by surface traps.
  • the electric field modulation effect of the field plate can reduce the probability that electrons in the channel are excited by a strong electric field and captured by surface traps, thus suppressing current collapse and static current drop.
  • the current collapse phenomenon and the static current drop phenomenon cannot be completely eliminated.
  • the drain voltage is high in power device applications (usually the drain voltage is >650V)
  • surface passivation technology and field plate electric field modulation technology cannot effectively solve the current collapse problem when the drain voltage is high. Therefore, the current collapse problem remains one of the key constraints that limit nitride semiconductor devices from achieving their theoretical limit performance.
  • a semiconductor device is also provided. As shown in FIG. 2B, the semiconductor device includes a substrate, a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate. The channel layer and the barrier layer are sequentially stacked on the substrate. The barrier layer forms the heterojunction of the semiconductor device.
  • the semiconductor device also includes a source S, a drain D and a gate G. The gate G forms Schottky contact with the barrier layer, and the source S and drain D form ohmic contact with the barrier layer.
  • the semiconductor device also includes a hole injection layer one, which is provided on the barrier layer.
  • the hole injection layer one is located on the side of the drain electrode D close to the gate electrode and is coupled with the drain electrode D.
  • the hole injection layer 1 is used to inject holes into the semiconductor device.
  • a conductive layer is provided on the side of the hole injection layer 1 away from the barrier layer, and the conductive layer passes through the wire. Coupled with the drain D to achieve coupling between the drain D and the hole injection layer one.
  • a conductive layer is provided on the side of the hole injection layer away from the barrier layer, and the conductive layer is contact-coupled with the drain D to realize the connection between the drain D and the holes.
  • Injection layer one coupling.
  • the drain D and the hole injection layer 1 are overlapped to realize the coupling between the drain D and the hole injection layer 1.
  • the hole injection layer 1 By setting the hole injection layer 1 at the drain D end, during the switching process of the semiconductor device, the hole injection layer 1 injects holes into the surface of the barrier layer and into the barrier layer, channel layer and buffer layer, and is balanced by holes. The trapped channel electrons thereby suppress current collapse and quiescent current drop.
  • the provision of the hole injection layer 1 will deplete the two-dimensional electron gas in the channel below the hole injection layer 1, resulting in a decrease in the channel carrier concentration and an increase in the channel on-resistance (Rdson). That is to say, when the semiconductor device is turned on, the depletion effect of the hole injection layer on the two-dimensional electron gas of the channel will cause the channel on-resistance to increase, sacrificing the conduction characteristics of the semiconductor device.
  • a hole injection layer 2 when used as an enhancement-mode semiconductor device, a hole injection layer 2 will be provided under the gate G.
  • the structure of the T-shaped hole injection layer 2 leads to the preparation of the T-shaped hole injection layer 2. It is necessary to combine the recessed-gate and regrow processes, which increases the process complexity.
  • the semiconductor device mainly includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40 and a potential layer that are sequentially stacked on the substrate 10.
  • the barrier layer 50 , the source electrode S and the drain electrode D arranged side by side on the side of the barrier layer 50 away from the substrate 10 , and the source electrode S and the drain electrode D arranged on the side of the barrier layer 50 away from the substrate 10 and between the source electrode S and the drain electrode D
  • Gate G and the first hole injection layer 61 disposed on the side of the barrier layer 50 away from the substrate 10 .
  • Part of the bottom surface of the gate G covers the top surface of the first hole injection layer 61 .
  • Part of the gate G The bottom surface is in contact with the barrier layer 50 .
  • the substrate 10 in the semiconductor device is a silicon (Si) or silicon carbide (SiC) substrate.
  • the semiconductor device when the substrate 10 is a conductive substrate (Si substrate), the semiconductor device is used as a power device in electronic equipment and is interconnected with the PCB in the electronic equipment.
  • the substrate 10 is a semi-insulating substrate (SiC substrate)
  • the semiconductor device is used as a radio frequency device in electronic equipment to achieve signal intercommunication with the antenna in the electronic equipment.
  • the nucleation layer 20 is disposed on the substrate 10 , for example, the nucleation layer 20 is disposed on the surface of the substrate 10 .
  • the nucleation layer 20 can be formed by, for example, a metal-organic chemical vapor deposition (MOCVD) growth method or a molecular beam epitaxy (MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the material of the nucleation layer 20 may include, for example, one or more of GaN, AlGaN, and aluminum nitride (AlN).
  • the nucleation layer 20 can provide a nucleation center to promote the epitaxial growth of the buffer layer 30 .
  • the buffer layer 30 is disposed on the side of the nucleation layer 20 away from the substrate 10 .
  • the buffer layer 30 is disposed on the surface of the nucleation layer 20 away from the substrate 10 .
  • the buffer layer 30 may be a gradient buffer layer, for example.
  • the buffer layer 30 may be formed by, for example, using a MOCVD process to epitaxially grow an AlGaN graded layer with gradually lower Al (aluminum) components. For example, through a MOCVD process, an Al 0.8 Ga 0.2 N layer, an Al 0.5 Ga 0.5 N layer, and an Al 0.2 Ga 0.8 N layer are sequentially formed on the side of the nucleation layer 20 away from the substrate 10 to form the buffer layer 30 .
  • the buffer layer 30 may also be a GaN layer, an AlN/GaN superlattice structure layer, or a combination of the above-mentioned structures.
  • composition of the buffer layer 30 when the semiconductor device is used as a radio frequency device and the composition of the buffer layer 30 when the semiconductor device is used as a power device may be different.
  • the function of the buffer layer 30 is that the different bandgap widths of the buffer layer 30 and the channel layer 40 can make the potential well depth of the heterojunction formed by the barrier layer 50 and the channel layer 40 deeper, thereby increasing the two-dimensional electron gas ( The concentration of two-dimensional electron gas, 2DEG).
  • the buffer layer 30 in order to reduce the mobility reduction caused by electron scattering, the buffer layer 30 generally adopts an undoped structure.
  • the channel layer 40 is disposed on one side of the substrate 10 .
  • the channel layer 40 is disposed on the surface of the buffer layer 30 .
  • the channel layer 40 may be formed by, for example, MOCVD growth or MBE growth.
  • the material of the channel layer 40 may include, for example, one or more of GaN, AlGaN, indium aluminum nitride (InAlN), aluminum nitride (AlN), and scandium aluminum nitride (ScAlN).
  • the semiconductor device further includes an intervening layer.
  • the insertion layer is disposed on the channel layer 40 and is located between the channel layer 40 and the barrier layer 50 .
  • the insertion layer is disposed on the surface of the channel layer 40 .
  • the insertion layer may be formed by, for example, MOCVD growth method or MBE growth method.
  • Providing an insertion layer between the channel layer 40 and the barrier layer 50 can increase the concentration of the two-dimensional electron gas.
  • the barrier layer 50 and the channel layer 40 are stacked.
  • the barrier layer 50 is disposed on the surface of the channel layer 40 .
  • the barrier layer 50 is disposed on the surface of the insertion layer.
  • the barrier layer 50 may be formed by, for example, MOCVD growth or MBE growth.
  • the material of the barrier layer 50 may include, for example, one or more of GaN, AlGaN, InAlN, AIN, and ScAlN.
  • the channel layer 40 and the barrier layer 50 constitute a heterojunction of the semiconductor device, and a two-dimensional electron gas is generated above the channel layer 40 . Therefore, the channel layer 40 and the barrier layer 50 are made of different materials.
  • the material of the channel layer 40 includes GaN
  • the material of the barrier layer 50 includes AlGaN.
  • the first hole injection layer 61 is disposed on the side of the barrier layer 50 away from the substrate 10 .
  • the first hole injection layer 61 is provided on the surface of the barrier layer 50 .
  • the first hole injection layer 61 can be formed by forming the hole injection film by the MOCVD growth method or the MBE growth method after forming the barrier layer 50, and then etching by inductively coupled plasma (ICP). This method selectively removes the hole injection film in unnecessary areas to form the first hole injection layer 61 .
  • ICP inductively coupled plasma
  • the first hole injection layer 61 is formed by epitaxial growth combined with an etching process. No further growth process is required and the process complexity will not be increased.
  • the formation of the first hole injection layer 61 can also be done by directly forming the first hole injection layer 61 through a selective epitaxy growth (SEG) process under the gate G after forming the barrier layer 50 .
  • SEG selective epitaxy growth
  • the material of the first hole injection layer 61 may be, for example, a P-type semiconductor material.
  • the P-type semiconductor material can be P-type doped (such as magnesium (Mg) doped) P-type gallium nitride (p-GaN), P-type aluminum nitride (p-AlN), P-type indium nitride (p- InN), P-type aluminum gallium nitride (p-AlGaN), P-type indium aluminum nitride (p-InAlN), P-type indium gallium nitride (p-InGaN), P-type indium aluminum gallium nitride (p-InGaN), P-type indium aluminum gallium nitride (p-In x Al x Ga 1-xy N) (where x+y ⁇ 1), or other P-type semiconductor materials (such as nickel oxide (NiO), etc.).
  • P-type doped such as magnesium (Mg) doped
  • the cross-sectional shape of the first hole injection layer 61 may be a rectangle.
  • the first hole injection layer 61 has a planar structure.
  • the shape of the first hole injection layer 61 may be square, rectangular, circular, elliptical, trapezoidal, etc.
  • the first hole injection layer 61 has a planar structure, has a simple structure and is easy to prepare.
  • the first hole injection layer 61 includes a plurality of spaced-apart block structures.
  • each block structure can be square, rectangular, circular, elliptical, trapezoidal, etc.
  • the shapes of the plurality of block structures may be the same, or the shapes of the plurality of block structures may be different.
  • multiple block-shaped structures may be arranged in one row along the extending direction of the drain electrode D, and multiple block-shaped structures may also be arranged in multiple rows along the extending direction of the drain electrode D.
  • Multiple block structures can be arranged regularly, and multiple block structures can also be arranged irregularly.
  • the semiconductor device further includes a passivation layer 70 covering the surface of the barrier layer 50.
  • the passivation layer 70 has an opening, and the opening exposes the first hole injection In layer 61 , the source electrode S and the drain electrode D form ohmic contact with the barrier layer 50 through the openings on the passivation layer 70 , and the gate G forms Schottky contact with the barrier layer 50 through the openings on the passivation layer 70 .
  • the material of the passivation layer 70 may be, for example, silicon nitride (SiN) or silicon oxide (SiO).
  • the passivation effect of the passivation layer 70 can weaken the trapping effect of surface traps of the barrier layer on electrons in the channel, thereby inhibiting current collapse and static current drop.
  • the gate G is disposed on the side of the barrier layer 50 away from the substrate 10 , and the gate G forms a Schottky contact with the barrier layer 50 .
  • the gate G may be formed by photolithography and etching processes, for example.
  • the material of the gate G may be, for example, Au or Pd.
  • the cross-sectional shape of the gate G is rectangular. In this way, the structure is simple and easy to manufacture.
  • the cross-sectional shape of the gate G is T-shaped.
  • the portion of the gate G located above the passivation layer 70 can be equivalent to a field plate and has the function of adjusting the electric field.
  • it is equivalent to thickening and widening the gate G, reducing the resistance of the gate G, thereby reducing the resistance of the semiconductor device.
  • part of the bottom surface of the gate G facing the barrier layer 50 covers the top surface of the first hole injection layer 61, and the part of the gate G also in contact with barrier layer 50 .
  • the gate G wraps the top surface and side surfaces of the first hole injection layer 61 .
  • the first hole injection layer 61 is buried in the gate G.
  • the first hole injection layer 61 is surrounded by a gate structure all around.
  • the side surface of the first hole injection layer 61 can be understood as the intersection surface of the first hole injection layer 61 and the barrier layer 50 , and the top surface of the first hole injection layer 61 can be understood as the first hole injection layer 61 .
  • Layer 61 is remote from the surface of barrier layer 50 .
  • the gate G covers part of the top surface of the first hole injection layer 61 , and part of the top surface of the first hole injection layer 61 is covered by the passivation layer 70 .
  • first hole injection layer 61 is partially located under the gate G, and the first hole injection layer 61 is partially located under the passivation layer 70 .
  • the gate G covers at least part of the first hole injection layer 61 , and the gate G is also in contact with the barrier layer 50 .
  • the first hole injection layer 61 receives the signal from the gate G and injects holes into the surface and interior of the barrier layer 50 to balance the electrons captured by the defect trap.
  • the source S and the drain D are disposed on the barrier layer 50 and form ohmic contact with the barrier layer 50 .
  • the source electrode S and the drain electrode D can be formed, for example, through photolithography and etching processes, and the source electrode S and the drain electrode D can be formed simultaneously, for example.
  • the source electrode S and the drain electrode D have a single-layer structure.
  • the structure is simple and easy to prepare.
  • the materials of the source S and the drain D may be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence, that is, Ti/Al/Ni/Au.
  • the materials of the source S and the drain D may be a Ti layer, an Al layer, a platinum (Pt) layer and an Au layer stacked in sequence, that is, Ti/Al/Pt/Au.
  • the materials of the source S and the drain D may be a Ti layer, a tantalum (Ta) layer and a Ti layer stacked in sequence, that is, Ti/Ta/Ti.
  • the source S and drain D may be made of Au or palladium (Pd).
  • the source electrode S and the drain electrode D have a double-layer structure.
  • the source S includes a coupled source ohmic contact layer S1 and a source thickened electrode layer S2.
  • the source ohmic contact layer S1 is disposed close to the barrier layer 50 relative to the source thickened electrode layer S2.
  • the source ohmic contact Layer S1 forms ohmic contact with barrier layer 50 .
  • the work function of the material of the source ohmic contact layer S1 is smaller than the work function of the material of the source thickened electrode layer S2.
  • the drain D includes a coupled drain ohmic contact layer D1 and a drain thickened electrode layer D2.
  • the drain ohmic contact layer D1 is disposed close to the barrier layer 50 relative to the drain thickened electrode layer D2.
  • the drain ohmic contact Layer D1 forms ohmic contact with barrier layer 50 .
  • the work function of the material of the drain ohmic contact layer D1 is smaller than the work function of the material of the drain thickened electrode layer D2.
  • the materials of the source ohmic contact layer S1 and the drain ohmic contact layer D1 can be Ti/Al/Ni/Au, Ti/Al/Pt/Au, Ti/Al/Ti, etc.
  • the source thickening electrode The material of the layer S2 and the drain thickened electrode layer D2 may be, for example, a low resistivity material such as Au, Al, or Cu.
  • the gate G may be formed simultaneously with the source ohmic contact layer S1 and the drain ohmic contact layer D1, for example.
  • the embodiment of the present application does not limit the shape and size of the source ohmic contact layer S1 and the source thickened electrode layer S2.
  • the shapes and sizes of the drain ohmic contact layer D1 and the drain thickened electrode layer D2 are not limited. There is no limit on size.
  • the structure in Figure 3F is only an illustration without any limitation.
  • the material work functions of the source ohmic contact layer S1 and the drain ohmic contact layer D1 are smaller, and the ohmic contact resistance at the contact surface with the barrier layer 50 is smaller. , thereby reducing the resistance of the semiconductor device and improving the current conduction capability of the semiconductor device.
  • the semiconductor device further includes a field plate 80.
  • the field plate 80 is disposed on the side of the gate G away from the substrate 10 and is coupled to the source S.
  • one or more interlayer insulating layers or passivation layers may be provided between the field plate 80 and the gate G as needed.
  • the field plate 80 overlaps the gate G on a side close to the gate G.
  • the orthographic projection of the field plate 80 on the substrate 10 overlaps with the orthographic projection of the gate G on the substrate 10 on the side close to the gate G.
  • the facing area of the field plate 80 and the gate G can be reduced, thereby reducing the gate-source parasitic capacitance (Cgs) of the semiconductor device, thereby reducing the field plate 80 on the frequency characteristics of semiconductor devices.
  • the side of the field plate 80 close to the gate G does not overlap with the gate G along the direction perpendicular to the substrate 10 .
  • the gap between the gate G and the field plate 80 can be minimized.
  • gate-source parasitic capacitance Cgs
  • the semiconductor device may include one layer of field plates 80 , and the semiconductor device may also include multiple layers of field plates 80 .
  • the multiple layers of field plates 80 are separated by a dielectric layer, and the multiple layers of field plates 80 are all coupled to the source S.
  • the structure of the field plate 80 shown in FIG. 3B is only an illustration and is not limited in any way.
  • the semiconductor device provided by the embodiments of the present application may be provided with film layers such as an insulation layer, a passivation layer, and a planarization layer as needed.
  • the semiconductor device also includes a passivation layer covering the source thickened electrode layer S2, the drain thickened electrode layer D2 and the field plate 80 to passivate the surface of the semiconductor device.
  • the passivation layer is provided with an exposed gate electrode G, The openings of the source S and the drain D are used to realize signal communication between the pad and the gate G, the source S and the drain D.
  • the preparation steps of the semiconductor device shown in FIG. 3F may be, for example: first forming the nucleation layer 20, the buffer layer 30, the channel layer 40 and the barrier layer 50 on the substrate 10 in sequence, and then forming a current collapse suppressing and barrier layer.
  • the first hole injection layer 61 is formed, and then the passivation layer 70 is formed to perform surface passivation protection on the barrier layer 50, and then the source ohmic contact layer S1, the drain ohmic contact layer D1 and the gate electrode G are formed, and then Form an interlayer insulating layer (or passivation layer) covering the gate G, then form the field plate 80, then form the source thickened electrode layer S2 and the drain thickened electrode layer D2, and then form the surface passivation of the semiconductor device. passivation layer.
  • the semiconductor device Since the electric field intensity at the corner of the gate G is high when the semiconductor device is turned off, the high electric field here can easily cause breakdown of the semiconductor device, resulting in increased leakage or even permanent failure of the semiconductor device.
  • the semiconductor device When the semiconductor device is turned on, the semiconductor device will exhibit current collapse and static current drop problems due to the influence of material surface and internal defect traps.
  • the first hole injection layer 61 can reduce the electric field intensity at the corner of the gate G, reducing the flow of electrons from the gate G and being captured by material traps. probability, which plays a role in balancing the electric field at the corners of the gate G, thereby reducing the leakage of the gate G and improving the stability of the gate G of the semiconductor device.
  • the first hole injection layer 61 injects holes into the surface of the barrier layer 50 and into the channel. holes to balance the electrons captured by traps on the surface of the material or in the body, so that the two-dimensional electron gas channel exhausted by the captured electrons can quickly recover, thus suppressing current collapse and static current drop problems.
  • the first hole injection layer 61 has a depletion effect on the two-dimensional electron gas below the first hole injection layer 61, since part of the structure of the gate G directly forms Schottky contact with the barrier layer 50, therefore The signal on the gate G can be directly transmitted into the channel without being affected by the first hole injection layer 61 . Therefore, the semiconductor device provided in this example can suppress current collapse and static current drop without increasing the on-resistance of the semiconductor device.
  • the first hole injection layer 61 below the gate G factors such as the thickness, doping concentration, and distribution ratio of the first hole injection layer 61 below the gate G should be considered to ensure When the semiconductor device is in the on state, the depletion effect of the first hole injection layer 61 on the channel below the first hole injection layer 61 can be ignored, otherwise it will affect the on-resistance, on-state current, threshold and other parameters of the semiconductor device. , will also increase the swing of the gate drive voltage.
  • Example 2 The main difference between Example 2 and Example 1 is that the first hole injection layer 61 is not provided under the gate electrode G, and the second hole injection layer 62 is provided under the drain electrode D.
  • the semiconductor device mainly includes: a substrate 10 and a nucleation layer 20 sequentially stacked on the substrate 10 , the buffer layer 30, the channel layer 40 and the barrier layer 50, the source S and the drain D arranged side by side on the side of the barrier layer 50 away from the substrate 10, and the source electrode S and the drain D arranged on the side of the barrier layer 50 away from the substrate 10 and
  • the gate G is located between the source S and the drain D, and the second hole injection layer 62 is provided on the side of the barrier layer 50 away from the substrate 10 .
  • the drain D is wrapped around the periphery of the second hole injection layer 62 .
  • the structures of the substrate 10 , the nucleation layer 20 , the buffer layer 30 , the channel layer 40 and the barrier layer 50 are the same as those in Example 1. Please refer to the relevant description in Example 1 and will not be repeated here.
  • the second hole injection layer 62 is disposed on the side of the barrier layer 50 away from the substrate 10 .
  • the second hole injection layer 62 is provided on the surface of the barrier layer 50 .
  • the second hole injection layer 62 can be formed by forming a hole injection film by MOCVD growth or MBE growth after forming the barrier layer 50 , and then selectively removing holes in unnecessary areas by ICP etching. The film is implanted to form second hole injection layer 62 .
  • the second hole injection layer 62 is formed by epitaxial growth combined with an etching process, without requiring a further growth process and without increasing process complexity.
  • the second hole injection layer 62 may also be formed by directly forming the second hole injection layer 62 through a selective epitaxial growth process under the drain electrode D after the barrier layer 50 is formed.
  • the material of the second hole injection layer 62 may be, for example, a P-type semiconductor material.
  • the P-type semiconductor material can be P-type doped (such as magnesium (Mg) doped) P-type gallium nitride (p-GaN), P-type aluminum nitride (p-AlN), P-type indium nitride (p- InN), P-type aluminum gallium nitride (p-AlGaN), P-type indium aluminum nitride (p-InAlN), P-type indium gallium nitride (p-InGaN), P-type indium aluminum gallium nitride (p-InGaN), P-type indium aluminum gallium nitride (p-In x Al x Ga 1-xy N) (where x+y ⁇ 1), or other P-type semiconductor materials (such as nickel oxide (NiO), etc.).
  • P-type doped such as magnesium (Mg) doped
  • the cross-sectional shape of the second hole injection layer 62 may be a rectangular shape, a trapezoid shape, or the like.
  • the second hole injection layer 62 has a planar structure.
  • the shape of the second hole injection layer 62 may be a square, a rectangle, a circle, an ellipse, a trapezoid, etc.
  • the second hole injection layer 62 has a planar structure, which is simple in structure and easy to prepare.
  • the second hole injection layer 62 includes a plurality of spaced-apart block structures.
  • each block structure can be square, rectangular, circular, elliptical, trapezoidal, etc.
  • the shapes of the plurality of block structures may be the same, or the shapes of the plurality of block structures may be different.
  • Multiple block structures may be arranged in a row along the extending direction of the drain electrode D. As shown in FIG. 4C , multiple block structures may also be arranged in multiple rows along the extending direction of the drain electrode D. Multiple block structures can be arranged regularly, and multiple block structures can also be arranged irregularly.
  • the source S and the drain D are disposed on the barrier layer 50 and form ohmic contact with the barrier layer 50 .
  • the source electrode S and the drain electrode D can be formed, for example, through photolithography and etching processes, and the source electrode S and the drain electrode D can be formed simultaneously, for example.
  • the source electrode S and the drain electrode D have a single-layer structure.
  • the structure is simple and easy to prepare.
  • the source electrode S and the drain electrode D have a double-layer structure.
  • the source S includes a coupled source ohmic contact layer S1 and a source thickened electrode layer S2.
  • the source ohmic contact layer S1 is disposed close to the barrier layer 50 relative to the source thickened electrode layer S2.
  • the source ohmic contact Layer S1 forms ohmic contact with barrier layer 50 .
  • the drain D includes a coupled drain ohmic contact layer D1 and a drain thickened electrode layer D2.
  • the drain ohmic contact layer D1 is disposed close to the barrier layer 50 relative to the drain thickened electrode layer D2.
  • the drain ohmic contact layer D1 and Barrier layer 50 forms an ohmic contact.
  • the embodiment of the present application does not limit the shape and size of the source ohmic contact layer S1 and the source thickened electrode layer S2.
  • the shapes and sizes of the drain ohmic contact layer D1 and the drain thickened electrode layer D2 are not limited. There is no limit on size.
  • the structure in Figure 4D is only an illustration without any limitation.
  • the material work functions of the source ohmic contact layer S1 and the drain ohmic contact layer D1 are smaller, and the ohmic contact resistance at the contact surface with the barrier layer 50 is smaller. , thereby reducing the resistance of the semiconductor device and improving the current conduction capability of the semiconductor device.
  • the drain electrode D is also wrapped around the periphery of the second hole injection layer 62 . Or it can be understood that the second hole injection layer 62 is buried in the drain D.
  • the second hole injection layer 62 is disposed on the surface of the barrier layer 50 , and the drain D wraps The surface of the second hole injection layer 62 that is not in contact with the barrier layer 61 .
  • the drain electrode D wraps the side and top surfaces of the second hole injection layer 62 .
  • the side surface of the second hole injection layer 62 can be understood as the intersection surface of the second hole injection layer 62 and the barrier layer 50
  • the top surface of the second hole injection layer 62 can be understood as the second hole injection layer 62 .
  • Layer 62 is remote from the surface of barrier layer 50 .
  • the growth process can be directly continued to form the second hole injection layer 62 , and then the drain electrode D is formed.
  • the process is simple and easy to implement.
  • the drain D includes a drain ohmic contact layer D1 and a drain thickened electrode layer D2, the second hole The injection layer 62 is provided between the drain ohmic contact layer D1 and the drain thickened electrode layer D2.
  • the drain electrode D wraps the side surfaces, top surfaces, and bottom surfaces of the second hole injection layer 62 .
  • the bottom surface of the second hole injection layer 62 is in contact with the drain ohmic contact layer D1, and the side and top surfaces of the second hole injection layer 62 are covered by the drain thickening electrode layer D2.
  • the bottom surface of the drain ohmic contact layer D1 is all in contact with the barrier layer 50 , and the two-dimensional electron gas under the second hole injection layer 62 can be continuously disconnected, reducing the impact of the second hole injection layer 62 on the barrier layer 50 . Effect of channel resistance.
  • the drain D covers the second hole injection layer 62.
  • the second hole injection layer 62 receives the signal from the drain D and injects holes to the surface and interior of the barrier layer 50 to balance the defects. Traps captured electrons.
  • the semiconductor device further includes a passivation layer 70 and a field plate 80.
  • the structures of the passivation layer 70 and the field plate 80 may be the same as in Example 1. Please refer to the relevant description in Example 1, which will not be described again here. .
  • the preparation steps of the semiconductor device shown in FIG. 4D may be, for example: first forming the nucleation layer 20, the buffer layer 30, the channel layer 40 and the barrier layer 50 on the substrate 10 in sequence, and then forming a current collapse suppressing and barrier layer.
  • the second hole injection layer 62 where the static current drops is then formed with a passivation layer 70 to perform surface passivation protection on the barrier layer 50, and then the source ohmic contact layer S1, the drain ohmic contact layer D1 and the gate G are formed, and then Form an interlayer insulating layer (or passivation layer) covering the gate G, then form the field plate 80, then form the source thickened electrode layer S2 and the drain thickened electrode layer D2, and then form the surface passivation of the semiconductor device. passivation layer.
  • the drain D is wrapped around the periphery of the second hole injection layer 62 , that is to say, the drain D is wrapped around the outer circle of the second hole injection layer 62 . Then, the second hole injection layer 62 is in direct contact with the drain D to form equipotential coupling, and part of the structure of the drain D is located on the side of the second hole injection layer 62 close to the gate G.
  • the high voltage of the drain D causes the second hole injection layer 62 to inject holes into the surface of the barrier layer 50 and into the channel, modulating the electric field between the gate G and the drain D to reduce The probability of channel electrons being captured by material traps, and balancing the electrons captured by material traps (surface or body traps), so that the channel depleted of trapped electrons can quickly recover to reduce the sensitivity of the channel current to the off-state drain voltage degree, thus playing the role of suppressing current collapse and static current drop during the switching process of semiconductor devices.
  • the second hole injection layer 62 has a depletion effect on the two-dimensional electron gas below the second hole injection layer 62.
  • the semiconductor device provided in this example achieves the function of suppressing current collapse and static current drop without affecting the on-state on-resistance of the semiconductor device.
  • the semiconductor device provided by the embodiment of the present application can be applied to radio frequency devices and power devices.
  • Example 3 provides a metal-insulator-semiconductor field transistor (MISFET), while Examples 1 and 2 provide a high electron mobility transistor (High Electron Mobility Transistor (HEMT).
  • MISFET metal-insulator-semiconductor field transistor
  • HEMT High Electron Mobility Transistor
  • the semiconductor device mainly includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, and a barrier layer 50 that are sequentially stacked on the substrate 10. and the insulating layer 90, the source electrode S and the drain electrode D arranged side by side on the side of the barrier layer 50 away from the substrate 10, and the source electrode S and the drain electrode D arranged on the side of the insulating layer 90 away from the substrate 10 and between the source electrode S and the drain electrode D.
  • the gate G and the first hole injection layer 61 are disposed on the side of the barrier layer 50 away from the substrate 10 .
  • the insulating layer 90 has an opening, and the first hole injection layer 61 is located within the opening. That is to say, the insulating layer 90 is located on the periphery of the first hole injection layer 61 .
  • the source electrode S and the drain electrode D form ohmic contact with the barrier layer 60 through the openings in the insulating layer 90 .
  • the embodiment of the present application does not limit the material of the insulating layer 90. For example, it may be SiO, SiN and other materials.
  • the structures of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the barrier layer 50, and the first hole injection layer 61 are the same as those in Example 1. Please refer to the relevant descriptions in Example 1, which are not discussed here. Again.
  • the semiconductor device mainly includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40 and a potential barrier that are sequentially stacked on the substrate 10.
  • the layer 50 and the insulating layer 90, the source electrode S and the drain electrode D are arranged side by side on the side of the barrier layer 50 away from the substrate 10, and are arranged on the side of the insulating layer 90 away from the substrate 10 and between the source electrode S and the drain electrode D.
  • the second hole injection layer 62 is disposed on the side of the barrier layer 50 away from the substrate 10 .
  • the insulating layer 90 has an opening, and the drain D is located in the opening. That is, the insulating layer 90 is located on the periphery of the drain electrode D.
  • the source electrode S and the drain electrode D form ohmic contact with the barrier layer 60 through the openings in the insulating layer 90 .
  • the embodiment of the present application does not limit the material of the insulating layer 90. For example, it may be SiO, SiN and other materials.
  • the structures of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the barrier layer 50, and the second hole injection layer 62 are the same as those in Example 2. Please refer to the relevant descriptions in Example 2, which are not discussed here. Again.
  • the semiconductor device can also include a passivation layer 70 and a field plate 80.
  • the structures of the passivation layer 70 and the field plate 80 are the same as in Example 1. Please refer to the relevant description in Example 1. No further details will be given here.
  • the structures shown in Figures 5A and 5B also have the effect of suppressing current collapse and static current drop.
  • the hole injection layer 62 in the structure shown in Figure 5B does not affect the on-state conduction of the semiconductor device. pass resistance.
  • Example 4 provides an enhancement mode (normally off) HEMT device, while Example 2 provides a depletion mode (normally on) HEMT device.
  • the semiconductor device mainly includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40 and a potential barrier that are sequentially stacked on the substrate 10.
  • the working principle of the HEMT device is as follows: the source S and the drain D respectively form conductive ohmic contacts with the barrier layer 50 , and the gate G forms Schottky contact with the barrier layer 50 .
  • the dotted line in the channel layer 40 represents the 2DEG generated by polarization in the heterojunction formed by the channel layer 40 and the barrier layer 50 in the HEMT device. 2DEG is used to efficiently conduct electrons under the action of an electric field.
  • the source S and the drain D are used to make 2DEG flow in the channel layer 40 between the source S and the drain D under the action of the electric field.
  • the conduction between the source S and the drain D occurs in the channel. at the two-dimensional electron gas in layer 40.
  • the gate G is disposed between the source S and the drain D and is used to allow or block the passage of the two-dimensional electron gas.
  • the third hole injection layer 63 can adjust the energy band structure of the heterojunction formed by the channel layer 40 and the barrier layer 50 so that electrons directly below the third hole injection layer 63 are depleted. As shown in Figure 6, the existence of the third hole injection layer 63 makes 2DEG in a pinch-off state without bias, and 2DEG cannot flow in the channel layer 40 between the source S and the drain D. , the HEMT device is off.
  • the third hole injection layer 63 may be made of the same material as the second hole injection layer 62 , and the third hole injection layer 63 and the second hole injection layer 62 may be formed in the same preparation process.
  • the third hole injection layer 63 can be formed by forming a hole injection film by MOCVD growth or MBE growth after forming the barrier layer 50 , and then selectively removing holes in unnecessary areas by ICP etching. The film is implanted to form the second hole injection layer 62 and the third hole injection layer 63.
  • the third hole injection layer 63 is formed through epitaxial growth combined with an etching process, without requiring a further growth process and without increasing process complexity.
  • the third hole injection layer 63 can also be formed by directly forming the third hole injection layer 63 through a selective epitaxy growth (SEG) process under the gate G and the drain D after forming the barrier layer 50.
  • SEG selective epitaxy growth
  • the structural relationship between the gate G and the third hole injection layer 63 is: the gate G faces the bottom surface of the substrate 10 and contacts the third hole injection layer 63 without contacting the third hole injection layer 63 .
  • the barrier layer 50 is in contact.
  • the structural relationship between the gate G and the first hole injection layer 61 is: the gate G faces the bottom surface of the substrate 10 , partially in contact with the first hole injection layer 61 , and partially in contact with the barrier layer 50 . Therefore, the role played by the third hole injection layer 63 in the semiconductor device is different from the role played by the first hole injection layer 61 in the semiconductor device.
  • the cross-sectional shape of the third hole injection layer 63 is rectangular. In this way, compared with the enhancement mode semiconductor device shown in FIG. 2B, the third hole injection layer 63 does not need to consider the recessed-gate structure and the regrowth (regrow) process when preparing the third hole injection layer 63, which reduces the process complexity. .
  • the structures of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the barrier layer 50, and the second hole injection layer 62 are the same as those in Example 2. Please refer to the relevant descriptions in Example 2, which are not discussed here. Again.
  • the semiconductor device may also include a passivation layer 70 and a field plate 80.
  • the structures of the passivation layer 70 and the field plate 80 are the same as those in Example 2. Please refer to the relevant descriptions in Example 2, which are not discussed here. Again.
  • the semiconductor device When the semiconductor device is an enhancement-mode HEMT device, it also has the effect of suppressing current collapse and static current drop without affecting the on-state on-resistance of the semiconductor device.
  • Example 5 The main difference between Example 5 and Example 1 is that the semiconductor device provided in Example 5 not only includes the first hole injection layer 61 under the gate G, but also includes the second hole injection layer 62 under the drain D.
  • the semiconductor device mainly includes: a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40 and a barrier layer 50 that are sequentially stacked on the substrate 10. , the source S and the drain D arranged side by side on the side of the barrier layer 50 away from the substrate 10 , the gate G arranged on the side of the barrier layer 50 away from the substrate 10 and between the source electrode S and the drain D , the first hole injection layer 61 and the second hole injection layer 62 are provided on the side of the barrier layer 50 away from the substrate 10, the gate G covers at least part of the first hole injection layer 61, and the drain D is wrapped in The periphery of the second hole injection layer 62 .
  • the semiconductor device may also include an insulating layer 90 , and the transistor included in the semiconductor device is a MISFET.
  • the structures of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the barrier layer 50, and the second hole injection layer 62 are the same as those in Example 2. Please refer to the relevant descriptions in Example 2, which are not discussed here. Again.
  • Example 1 For the structural relationship between the gate G and the first hole injection layer 61, please refer to the relevant description in Example 1, which will not be described again here.
  • Example 2 For the structural relationship between the drain D and the second hole injection layer 62, please refer to the relevant description in Example 2, which will not be described again here.
  • the insulating layer 90 is located between the gate electrode G and the barrier layer 50 , and is located around the first hole injection layer 61 and the drain electrode D.

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Abstract

本申请实施例提供一种半导体器件及其工作方法、电子设备，涉及半导体技术领域，用于提高半导体器件的性能。半导体器件可以用作射频器件，也可以用作功率器件。半导体器件包括：衬底；依次层叠设置于衬底上的沟道层和势垒层；设置于势垒层远离衬底一侧的栅极、源极、漏极以及第一空穴注入层；栅极位于源极和漏极之间；栅极的部分底面覆盖于第一空穴注入层的顶面上，栅极的部分底面与势垒层形成肖特基接触。半导体器件可以抑制电流崩塌和静态电流跌落。

Description

半导体器件及其工作方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其工作方法、电子设备。
背景技术
随着半导体科技的发展，具有高热导率、耐高温、宽禁带宽度、高临界击穿电场、高电子迁移率、高二维电子气浓度、化学性质稳定的半导体器件，被广泛应用于射频器件及功率电子器件领域。
但是，受半导体器件材料特性的限制，导致半导体器件容易出现电流崩塌和静态电流跌落的问题，从而影响半导体器件的性能。
发明内容
本申请实施例提供一种半导体器件及其工作方法、电子设备，用于提高半导体器件的性能。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体器件，半导体器件可以用作射频器件，也可以用作功率器件。半导体器件包括衬底；沟道层和势垒层，依次层叠设置于衬底一侧；栅极、源极、漏极以及第一空穴注入层，设置于势垒层远离衬底一侧；栅极位于源极和漏极之间；栅极的部分底面覆盖于第一空穴注入层的顶面上，栅极的部分底面与势垒层接触。其中，在衬底为导电衬底时，半导体器件可以用作功率器件。在衬底为半绝缘衬底时，半导体器件可以用作射频器件。
本申请实施例提供的半导体器件，当半导体器件开态时，在栅极高压作用下，第一空穴注入层向势垒层的表面及沟道内注入空穴，平衡被材料表面或体内陷阱俘获的电子，使被俘获电子耗尽的二维电子气沟道迅速恢复，从而抑制电流崩塌和静态电流跌落问题。而且，虽然第一空穴注入层对第一空穴注入层下方的二维电子气具有耗尽作用，但是由于栅极有部分结构直接与势垒层形成肖特基接触，因此栅极上的信号可直接传输至沟道内，不受第一空穴注入层的影响。因此，本示例提供的半导体器件可以实现抑制电流崩塌和静态电流跌落的作用。
在一种可能的实现方式中，栅极覆盖第一空穴注入层的顶面和侧面。一种可能的实现方式。
在一种可能的实现方式中，栅极覆盖第一空穴注入层的部分顶面。一种可能的实现方式。
在一种可能的实现方式中，半导体器件还包括第二空穴注入层，第二空穴注入层设置于势垒层远离衬底一侧；漏极包裹第二空穴注入层。漏极包裹在第二空穴注入层的外围。那么，第二空穴注入层与漏极直接接触形成等电位耦接，且漏极有部分结构位于第二空穴注入层靠近栅极一侧。这样一来，在半导体器件关态时，漏极高压使第 二空穴注入层向势垒层表面及沟道内注入空穴，调制栅极和漏极间的电场，来降低沟道电子被材料陷阱俘获的几率，以及平衡被材料陷阱(表面或体内陷阱)俘获的电子，使被俘获电子耗尽的沟道迅速恢复，以降低沟道电流对关态漏极电压的敏感程度，从而起到抑制半导体器件开关过程中的电流崩塌和静态电流跌落的作用。而且，虽然第二空穴注入层对第二空穴注入层下方的二维电子气具有耗尽作用。但是由于漏极有部分结构位于第二空穴注入层靠近栅极一侧，半导体器件中的电流可通过第二空穴注入层靠近栅极一侧的漏极结构进入漏极内，而不经过第二空穴注入层下方的二维电子气耗尽区。因此，本示例提供的半导体器件在实现抑制电流崩塌和静态电流跌落的作用的同时，不影响半导体器件的开态导通电阻。且本申请实施例提供的半导体器件可以应用于射频器件，也可以应用于功率器件。
在一种可能的实现方式中，漏极包括欧姆接触层和加厚电极层；第一空穴注入层设置在势垒层的表面上。一种实现方式。
在一种可能的实现方式中，漏极包括欧姆接触层和加厚电极层；第一空穴注入层设置在欧姆接触层与加厚电极层之间。一种实现方式。
在一种可能的实现方式中，第一空穴注入层包括多个间隔设置的块状结构。这样一来，在相邻块状结构之间填充有栅极，可增加栅极与势垒层的接触面积，栅极与势垒层的接触效果好。
在一种可能的实现方式中，第一空穴注入层为面状结构。面状的第一空穴注入层可注入更多的空穴，抑制电流崩塌和静态电流跌落的效果更好。
在一种可能的实现方式中，第二空穴注入层包括多个间隔设置的块状结构。这样一来，在相邻块状结构之间填充有漏极，可增加漏极与势垒层的接触面积，漏极与势垒层的接触电阻较小。
在一种可能的实现方式中，第二空穴注入层为面状结构。面状的第二空穴注入层可注入更多的空穴，抑制电流崩塌和静态电流跌落的效果更好。
在一种可能的实现方式中，半导体器件还包括绝缘层，绝缘层设置于栅极与势垒层之间，绝缘层位于第一空穴注入层和漏极的外围。半导体器件可为MISFET器件。
在一种可能的实现方式中，第一空穴注入层的材料包括P型半导体材料。
本申请实施例的第二方面，提供一种半导体器件，包括：衬底；沟道层和势垒层，依次层叠设置于衬底一侧；栅极、源极、漏极以及第二空穴注入层，设置于势垒层远离衬底一侧；栅极位于源极和漏极之间；漏极包裹第二空穴注入层。
本申请实施例提供的半导体器件，在半导体器件关态时，漏极高压使第二空穴注入层向势垒层表面及沟道内注入空穴，调制栅极和漏极间的电场，来降低沟道电子被材料陷阱俘获的几率，以及平衡被材料陷阱(表面或体内陷阱)俘获的电子，使被俘获电子耗尽的沟道迅速恢复，以降低沟道电流对关态漏极电压的敏感程度，从而起到抑制半导体器件开关过程中的电流崩塌和静态电流跌落的作用。而且，虽然第二空穴注入层对第二空穴注入层下方的二维电子气具有耗尽作用。但是由于漏极有部分结构位于第二空穴注入层靠近栅极一侧，半导体器件中的电流可通过第二空穴注入层靠近栅极一侧的漏极结构进入漏极内，而不经过第二空穴注入层下方的二维电子气耗尽区。因此，本示例提供的半导体器件在实现抑制电流崩塌和静态电流跌落的作用的同时， 不影响半导体器件的开态导通电阻。且本申请实施例提供的半导体器件可以应用于射频器件，也可以应用于功率器件。
在一种可能的实现方式中，半导体器件还包括第三空穴注入层，栅极设置在第三空穴注入层上，栅极的底面与第三空穴注入层接触。半导体器件可为增强型半导体器件。
在一种可能的实现方式中，半导体器件还包括绝缘层，绝缘层设置于栅极与势垒层之间，绝缘层位于漏极的外围。半导体器件可为MISFET器件。
本申请实施例的第三方面，提供一种电子设备，包括半导体器件及天线；半导体器件用于将射频信号放大后输出至天线向外辐射；其中，半导体器件为第一方面任一项或者第二方面任一项的半导体器件。
本申请实施例第三方面提供的电子设备包括第一方面或第二方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
本申请实施例的第四方面，提供一种电子设备，包括半导体器件及与半导体器件电连接的印刷电路板；其中，所半导体器件为第一方面任一项或者第二方面任一项的半导体器件。
本申请实施例第四方面提供的电子设备包括第一方面或第二方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
本申请实施例的第五方面，提供一种半导体器件的工作方法，包括半导体器件，半导体器件包括衬底；沟道层和势垒层，依次层叠设置于衬底一侧；栅极、源极、漏极以及第一空穴注入层，设置于势垒层远离衬底一侧；栅极位于源极和漏极之间；栅极的部分底面覆盖于第一空穴注入层的顶面上，栅极的部分底面与势垒层接触；半导体器件的工作方法包括：第一空穴注入层接收栅极的信号，向势垒层注入空穴。
本申请实施例第五方面提供的半导体器件的工作方法的有益效果与第一方面提供的半导体器件的有益效果相同，此处不再赘述。
在一种可能的实现方式中，半导体器件还包括第二空穴注入层，第二空穴注入层设置于势垒层远离衬底一侧；漏极包裹第二空穴注入层；半导体器件的工作方法还包括：第二空穴注入层接收漏极的信号，向势垒层注入空穴。
本申请实施例的第六方面，提供一种半导体器件的工作方法，包括半导体器件，衬底；沟道层和势垒层，依次层叠设置于衬底一侧；栅极、源极、漏极以及第二空穴注入层，设置于势垒层远离衬底一侧；栅极位于源极和漏极之间；漏极包裹第二空穴注入层；半导体器件的工作方法还包括：第二空穴注入层接收漏极的信号，向势垒层注入空穴。
本申请实施例第六方面提供的半导体器件的工作方法的有益效果与第二方面提供的半导体器件的有益效果相同，此处不再赘述。
附图说明
图1A为本申请实施例提供的一种基站的结构示意图；
图1B为本申请实施例提供的一种有源天线单元的结构示意图；
图1C为本申请实施例提供的一种充电器的结构示意图；
图2A-图2D为本申请实施例提供的一种半导体器件的结构示意图；
图3A为本申请实施例提供的一种半导体器件的俯视示意图；
图3B为一种图3A中沿A1-A2向的剖视图；
图3C为本申请实施例提供的另一种半导体器件的俯视示意图；
图3D为另一种图3A中沿A1-A2向的剖视图；
图3E为又一种图3A中沿A1-A2向的剖视图；
图3F为又一种半导体器件的结构示意图；
图4A为本申请实施例提供的又一种半导体器件的俯视示意图；
图4B为一种图4A中沿B1-B2向的剖视图；
图4C为本申请实施例提供的又一种半导体器件的俯视示意图；
图4D为又一种半导体器件的结构示意图；
图4E为又一种半导体器件的结构示意图；
图5A-图5B为又一种半导体器件的结构示意图；
图6为又一种半导体器件的结构示意图；
图7A为又一种半导体器件的结构示意图；
图7B为又一种半导体器件的结构示意图。
附图标记：
1-基站；2-充电器；11-基带处理单元；12-有源天线单元；121-计算单元；122-第一传输单元；123-天线单元；124-电源；1210-控制单元；1211-第二传输单元；1212-基带单元；1213-供电单元；1221-RF单元；1222-PA；10-衬底；20-成核层；30-缓冲层；40-沟道层；50-势垒层；61-第一空穴注入层；62-第二空穴注入层；63-第三空穴注入层；70-钝化层；80-场板；90-绝缘层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如， 描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本申请实施例中，术语“半绝缘(semi-insulating，SI)”指的是：电阻率大于10 5Ω·cm。例如，半绝缘SiC衬底指的是SiC衬底的电阻率大于10 5Ω·cm。
在本申请实施例中，术语“二维电子气(two-dimensional electron gas，2DEG)”指的是：电子在垂直于界面方向的运动被势阱束缚而被量子化，而其平行于表面的运动仍然是自由的，这样的二维方向的自由电子被称为二维电子气。
在本申请实施例中，术语“电流崩塌现象”指的是：当半导体器件从关态变成开态时，被俘获的电子还来不及从陷阱中被释放，沟道中的电子仍然处于被陷阱中电子耗尽的状态，导致沟道导电能力下降而呈现出电流下降的现象。电流崩塌现象直观表现为当给半导体器件施加一定时间的关态电压后，半导体器件开启瞬间沟道电流有所降低的现象。
在本申请实施例中，术语“静态电流(Idq)跌落”指的是：在半导体器件用作射频器件时，半导体器件被施加一定的静态直流电流Idq以改善器件的线性度特性，器件接收到射频信号后(RF on)开始工作，一段时间后射频信号结束(RF off)，此时会出现静态电流跌落，会导致下一次工作(RF on)时器件线性度恶化，需要在一定时间后Idq才会恢复到初始值，这个跌落现象就是静态电流跌落。静态电流跌落也是跟半导体器件中的一些缺陷陷阱相关，在射频信号(RF)开关过程中被捕获的电子并不能迅速恢复导致的。
本申请实施例提供一种电子设备，该电子设备例如可以为充电器、充电家用小型电器、无人机、激光雷达驱动器、激光器、探测器、雷达、第五代移动通信技术(the5th generation mobile network，5G)通信设备等不同类型的用户设备或终端设备；该电子设备也可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
近三十年来，高热导率、耐高温、宽禁带宽度、高临界击穿电场、高电子迁移率、 高二维电子气浓度、化学性质稳定的半导体器件，被广泛用作射频器件或功率器件，应用于功率电子领域、微波射频领域、光电器件领域等。
例如，第三代半导体氮化镓(GaN)材料具有优异的特性，如较大的禁带宽度(3.4eV)、高的击穿电场(3.3MV/cm)、大的饱和速率(2.5e7cm/s)、以及极化效应带来的铝镓氮(AlGaN)/GaN异质结构界面处的2DEG密度高，使得碳化硅(SiC)衬底或硅(Si)等衬底制备的AlGaN/GaN高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件可以工作在较高电压、较高温度和较高频率中，因而被广泛用于作为射频器件或功率器件。
在半导体器件用于作为射频器件的情况下，以电子设备为基站为例，对电子设备的结构进行说明。如图1A所示，基站1包括基带处理单元(base band unit，BBU)11和有源天线单元(active antenna unit，AAU)12。其中，BBU11主要负责基带数字信号处理，例如，FFT(fast fourier transform，快速傅立叶变换)/IFFT(inverse fast fourier transform，逆快速傅立叶变换)、调制/解调、信道编码/解码等。如图1B所示，AAU12包括计算单元121、第一传输单元122和天线单元123。其中，计算单元121包括控制单元1210、第二传输单元1211、基带单元1212和供电单元1213，控制单元1210、第二传输单元1211、基带单元1212和供电单元1213相互电连接，控制单元1210用于负责射频信号的控制，第二传输单元1211用于负责射频信号的传输，基带单元1212用于负责数字信号和模拟信号的转换，基带单元1212例如以是DAC(digital to analog converter，数字模拟转换器)，DAC可以将BBU 11输出的数字信号转换为模拟信号，供电单元1213与电源124电连接，用于为计算单元121中的控制单元1210、第二传输单元1211和基带单元1212供电。第一传输单元122用于负责射频信号的传输和放大。第一传输单元122包括RF(radio frequency，射频)单元1221和PA(power amplifier，功率放大器)1222，RF单元1221用于将模拟信号转化为小功率的射频信号，PA1222用于将小功率的射频信号进行功率放大后输出至天线单元123。天线单元123负责将射频信号向外辐射。如图1B所示，AAU12可以包括多个RF单元1221、多个PA1222以及多个天线单元123。需要说明的是，上述PA1222可以为半导体器件。
应当理解到，在半导体器件用于作为PA时，本申请实施例提供的电子设备不限于图1A和图1B所示的基站，任意需要使用功率放大器对信号进行放大的电子设备均属于本申请的实施例的应用场景。
在半导体器件用于作为功率器件的情况下，以电子设备为充电器为例，对电子设备的结构进行说明。如图1C所示，充电器2可以包括功率器件、电阻R、电感L、电容C等，功率器件例如可以为半导体器件。其中，半导体器件、电阻R、电感L和电容C可以通过印刷电路板(printed circuit board，PCB)实现互连。
应当理解到，在半导体器件用于作为功率器件时，本申请实施例提供的电子设备不限于图1C所示的充电器，任意需要使用功率器件的电子设备均属于本申请的实施例的应用场景。
由于在SiC或Si等衬底上制作的AlGaN/GaN异质结时，由于AlGaN/GaN异质结的晶格与衬底的晶格存在不匹配的问题，导致AlGaN/GaN异质结材料缺陷密度较高，由此制作的半导体器件有明显的电流崩塌问题。产生电流崩塌的原理是当半导体器件 关断时，在栅极高场的作用下，沟道中的电子被AlGaN/GaN异质结表面或异质结下方的缓冲层材料中的缺陷陷阱俘获，当半导体器件从关态变成开态时，被俘获的电子还来不及从缺陷陷阱中被释放，沟道中的电子仍然处于被缺陷陷阱中电子耗尽的状态，导致沟道导电能力下降而呈现出电流下降的现象。这种电流崩塌现象对射频器件和功率器件在高功率和高频应用方面产生了明显的不利影响。
此外，射频器件工作时通常会设置一定的静态电流(Idq)以保证放大倍数的线性度，但是通常遇到的问题是，当射频器件施加一段时间的射频应力后，静态电流会明显的跌落，需要一定的时间才能恢复至设定值。静态电流跌落是与电流崩塌相似的一种物理现象，静态电流跌落也是跟射频器件中的一些缺陷陷阱相关，在射频信号(RF)开关过程中被捕获的电子并不能迅速恢复导致的。静态电流跌落的幅度以及恢复时间与材料的缺陷密度和种类相关。而静态电流跌落会导致系统线性度的预失真(digital pre-distortion，DPD)校准困难甚至无法校正。虽然可以通过提高静态电流的设定值来达到射频器件的线性度要求，但是这样就牺牲了射频器件的静态功耗。
基于此，如何抑制电流崩塌和静态电流跌落成为本领域技术人员需要解决的技术问题。
在一些实施例中，提供一种半导体器件，如图2A所示，半导体器件包括衬底、依次层叠设置于衬底上的缓冲层、沟道层以及势垒层，沟道层和势垒层形成半导体器件的异质结。半导体器件还包括源极S、漏极D和栅极G，栅极G与势垒层形成肖特基接触，源极S和漏极D与势垒层形成欧姆接触。
在此基础上，半导体器件还包括钝化层和场板(field plate，FP)，钝化层设置在势垒层的表面上。场板设置在栅极G上方，场板位于栅极G靠近漏极D一侧，场板与源极S耦接。且在垂直于衬底的方向上，场板与栅极G交叠。
采用表面钝化技术，在势垒层表面通过化学气象沉积(chemical vapor deposition，CVD)工艺形成钝化层。钝化层的材料例如可以是氮化硅(SiN)或者氧化硅(SiO)等材料。钝化层的钝化作用可以减弱势垒层的表面陷阱对沟道中电子的俘获作用，从而抑制电流崩塌和静态电流跌落。
采用场板电场调制技术，在栅极G靠近漏极D一侧的钝化层上方形成场板。场板结构的存在，可以减弱栅极G边缘以及场板下方(栅极G和漏极D之间)的电场强度。电场减弱后，沟道中的电子便不容易被表面陷阱俘获。场板的电场调制作用可以降低沟道中电子受强电场激发被表面陷阱俘获的概率，从而抑制电流崩塌和静态电流跌落。
然而，即使同时在半导体器件中形成钝化层和场板，也无法完全消除电流崩塌现象和静态电流跌落现象。尤其在功率器件应用中漏极高压情况下(通常漏极电压>650V)，通过表面钝化技术及场板电场调制技术无法有效解决漏极高压时的电流崩塌问题。因此，电流崩塌问题仍然是限制氮化物半导体器件发挥其理论极限性能的关键制约因素之一。
在另一些实施例中，还提供一种半导体器件，如图2B所示，半导体器件包括衬底、依次层叠设置于衬底上的缓冲层、沟道层以及势垒层，沟道层和势垒层形成半导体器件的异质结。半导体器件还包括源极S、漏极D和栅极G，栅极G与势垒层形成 肖特基接触，源极S和漏极D与势垒层形成欧姆接触。
在此基础上，半导体器件还包括空穴注入层一，空穴注入层一设置在势垒层上，空穴注入层一位于漏极D靠近栅极一侧，且与漏极D耦接，空穴注入层一用于向半导体器件内部注入空穴。
关于空穴注入层一与漏极D耦接的方式，在一种可能的实现方式中，如图2B所示，空穴注入层一远离势垒层一侧设置有导电层，导电层通过引线与漏极D耦接，以实现漏极D与空穴注入层一的耦接。
在另一种可能的实现方式中，如图2C所示，空穴注入层一远离势垒层一侧设置有导电层，导电层与漏极D接触耦接，以实现漏极D与空穴注入层一的耦接。
在又一种可能的实现方式中，如图2D所示，漏极D与空穴注入层一搭接，以实现漏极D与空穴注入层一的耦接。
通过在漏极D端设置空穴注入层一，在半导体器件开关过程中，空穴注入层一向势垒层表面及势垒层、沟道层、缓冲层内注入空穴，通过空穴平衡被俘获的沟道电子，从而抑制电流崩塌和静态电流跌落。
然而，空穴注入层一的设置，会耗尽空穴注入层一下方沟道中的二维电子气，导致沟道载流子浓度降低，沟道导通电阻(Rdson)增大。也就是说，当半导体器件开启时，空穴注入层一对沟道二维电子气的耗尽作用会导致沟道导通电阻增大，会牺牲半导体器件的导通特性。而且，如图2B-图2D所示，作为增强型半导体器件应用时，栅极G下方会设置有空穴注入层二，T型空穴注入层二的结构导致T型空穴注入层二制备时需要结合凹栅槽(recessed-gate)和再生长(regrow)工艺，增加了工艺复杂度。
因此，需要提出一种既可以抑制电流崩塌和静态电流跌落问题，同时又不恶化沟道的导通电阻的半导体器件，并且尽量不增加工艺复杂度，且在射频器件及功率器件中均可以，才能满足当下的需求。
下面，以几个详细的示例对本申请实施例提供的半导体器件进行示意说明。
示例一
本示例提供一种半导体器件，如图3A和图3B所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40和势垒层50、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于势垒层50远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第一空穴注入层61，栅极G的部分底面覆盖于第一空穴注入层61的顶面上，栅极G的部分底面与势垒层50接触。
在一些实施例中，半导体器件中的衬底10为硅(Si)或碳化硅(SiC)衬底。
其中，在衬底10为导电型衬底(Si衬底)的情况下，半导体器件作为功率器件应用于电子设备中，与电子设备中的PCB实现互连。在衬底10为半绝缘衬底(SiC衬底)的情况下半导体器件作为射频器件应用于电子设备中，与电子设备中的天线实现信号互通。
如图3B所示，在一些实施例中，成核层20设置于衬底10上，例如，成核层20设置于衬底10的表面上。
其中，形成成核层20的方法，例如可以通过金属有机化合物化学气相沉淀 (metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。
成核层20的材料，例如可以包括GaN、AlGaN、氮化铝(AlN)中一种或多种。
此处，成核层20可以提供成核中心，促进缓冲层30的外延生长。
请继续参考图3B，在一些实施例中，缓冲层30设置于成核层20远离衬底10一侧，例如，缓冲层30设置于成核层20远离衬底10的表面上。
其中，缓冲层30例如可以是渐变缓冲层。形成缓冲层30的方法，例如可以采用MOCVD工艺外延生长Al(铝)组分逐渐降低的AlGaN渐变层。示例的，通过MOCVD工艺，在成核层20远离衬底10一侧依次形成Al 0.8Ga 0.2N层、Al 0.5Ga 0.5N层、Al 0.2Ga 0.8N层，以形成缓冲层30。
缓冲层30也可以是GaN层、AlN/GaN超晶格结构层、或者前述几种结构的组合层。
可以理解的是，半导体器件用于作为射频器件时上述缓冲层30的成分，和，半导体器件用于作为功率器件时上述缓冲层30的成分可以不同。
缓冲层30的作用是，缓冲层30和沟道层40的禁带宽度不同，可以使得势垒层50与沟道层40形成的异质结的势阱深度更深，从而提高二维电子气(two-dimensional electron gas，2DEG)的浓度。另外，为了减少电子的散射带来的迁移率降低，缓冲层30一般采用不掺杂的结构。
请继续参考图3B，在一些实施例中，沟道层40设置于衬底10的一侧。例如，沟道层40设置于缓冲层30的表面上。
其中，形成沟道层40的方法，例如可以通过MOCVD生长法或MBE生长法等。
上述沟道层40的材料例如可以包括GaN、AlGaN、铟氮化铝(InAlN)、氮化铝(AlN)、钪氮化铝(ScAlN)中一种或多种。
在一些实施例中，半导体器件还包括插入层。
插入层设置于沟道层40上，插入层位于沟道层40和势垒层50之间。例如，插入层设置于沟道层40的表面上。其中，形成插入层的方法，例如可以采用MOCVD生长法或MBE生长法等。
在沟道层40和势垒层50之间设置插入层，可以提高二维电子气的浓度。
在一些实施例中，势垒层50与沟道层40层叠设置。示例的，如图3B所示，势垒层50设置于沟道层40的表面上。或者，示例的，在半导体器件还包括插入层的情况下，势垒层50设置于插入层的表面上。
其中，形成势垒层50的方法，例如可以通过MOCVD生长法或MBE生长法等。势垒层50的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。
可以理解的是，沟道层40和势垒层50构成半导体器件的异质结，沟道层40的上方产生二维电子气。因此，沟道层40和势垒层50的材料不相同。示例的，沟道层40的材料包括GaN，势垒层50的材料包括AlGaN。
请继续参考图3B，在一些实施例中，第一空穴注入层61设置在势垒层50远离衬底10一侧。例如，第一空穴注入层61设置在势垒层50的表面上。
第一空穴注入层61的形成，可以是在形成势垒层50后，通过MOCVD生长法或 MBE生长法形成空穴注入膜，然后通过感应耦合等离子体(inductively coupled plasma，ICP)刻蚀的方式选择性去除不需要区域的空穴注入膜，以形成第一空穴注入层61。
第一空穴注入层61通过外延生长结合刻蚀工艺形成，无需再生长工艺，不会增加工艺复杂度。
第一空穴注入层61的形成，也可以是在形成势垒层50后，通过在栅极G下方选择性外延生长(selective epitaxy growth，SEG)工艺，直接形成第一空穴注入层61。
第一空穴注入层61的材料，例如可以是P型半导体材料。P型半导体材料可以为P型掺杂(如镁(Mg)掺杂)的P型氮化镓(p-GaN)，P型氮化铝(p-AlN)，P型氮化铟(p-InN)，P型铝镓氮(p-AlGaN)，P型铟氮化铝(p-InAlN)，P型铟氮化镓(p-InGaN)，P型氮化铟铝镓(p-In xAl xGa 1-x-yN)(其中x+y≤1)，或其他P型半导体材料(如氧化镍(NiO)等)。
关于第一空穴注入层61的形状，图3B视角的截面图来看，第一空穴注入层61的截面形状可以为矩形。
此外，可选的，如图3A所示，第一空穴注入层61为面状结构。
从图3A视角的俯视图来看，第一空穴注入层61的形状可以为正方形、长方形、圆形、椭圆形、梯形等形状。
第一空穴注入层61为面状结构，结构简单，便于制备。
或者，可选的，如图3C所示，第一空穴注入层61包括多个间隔设置的块状结构。
从图3C视角的俯视图来看，每个块状结构的形状可以为正方形、长方形、圆形、椭圆形、梯形等形状。多个块状结构的形状可以相同，多个块状结构的形状也可以不相同。如图3C所示，多个块状结构沿漏极D的延伸方向可以排布成一排，多个块状结构沿漏极D的延伸方向也可以排布成多排。多个块状结构可以有规律的排布，多个块状结构也可以没有规律的排布。
请继续参考图3B，在一些实施例中，半导体器件还包括钝化层70，钝化层70覆盖在势垒层50的表面上，钝化层70上具有开口，开口露出第一空穴注入层61，源极S、漏极D通过钝化层70上的开口与势垒层50形成欧姆接触，栅极G通过钝化层70上的开口与势垒层50形成肖特基接触。
钝化层70的材料例如可以是氮化硅(SiN)或者氧化硅(SiO)等材料。钝化层70的钝化作用可以减弱势垒层的表面陷阱对沟道中电子的俘获作用，从而抑制电流崩塌和静态电流跌落。
请继续参考图3B，在一些实施例中，栅极G设置于势垒层50远离衬底10一侧，栅极G与势垒层50形成肖特基接触。
其中，栅极G例如可以通过光刻和刻蚀工艺形成。栅极G的材料，例如可以是Au或者Pd。
可选的，栅极G的截面形状为矩形。这样一来，结构简单，便于制作。
或者，可选的，如图3B所示，栅极G的截面形状为T型。这样一来，栅极G位于钝化层70上方的部分，一方面可以等效为场板，具有调节电场的作用。另一方面，相当于对栅极G进行加厚和加宽，减小栅极G的电阻，从而减小半导体器件的电阻。
栅极G与势垒层50肖特基接触的基础上，栅极G朝向势垒层50的底面中的部分 底面覆盖于第一空穴注入层61的顶面上，栅极G的部分还与势垒层50接触。
关于栅极G与第一空穴注入层61的结构关系，在一些实施例中，如图3B所示，栅极G包裹第一空穴注入层61的顶面和侧面。
或者理解为，第一空穴注入层61埋于栅极G内。第一空穴注入层61的外围一周都围绕有栅极结构。
其中，第一空穴注入层61的侧面可以理解为是第一空穴注入层61与势垒层50相交的表面，第一空穴注入层61的顶面可以理解为是第一空穴注入层61远离势垒层50的表面。
在另一些实施例中，如图3D和图3E所示，栅极G覆盖第一空穴注入层61的部分顶面，第一空穴注入层61的部分顶面被钝化层70覆盖。
或者理解为，第一空穴注入层61部分位于栅极G下方，第一空穴注入层61部分位于钝化层70下方。
也就是说，本示例中，栅极G覆盖第一空穴注入层61的至少部分，栅极G还与势垒层50接触。在半导体器件工作过程中，第一空穴注入层61接收栅极G的信号，向势垒层50的表面和内部注入空穴，以平衡被缺陷陷阱俘获的电子。
请继续参考图3B，在一些实施例中，源极S和漏极D设置于势垒层50上，与势垒层50形成欧姆接触。
其中，源极S、漏极D例如可以通过光刻和刻蚀工艺形成，源极S、漏极D例如可以同步形成。
可选的，如图3B所示，源极S和漏极D为单层结构。这样一来，结构简单，便于制备。
源极S、漏极D的材料，例如可以为依次层叠的钛(Ti)层、Al层、镍(Ni)层和金(Au)层，即Ti/Al/Ni/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、Al层、铂(Pt)层和Au层，即Ti/Al/Pt/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、钽(Ta)层和Ti层，即Ti/Ta/Ti。或者源极S、漏极D的材料可以为Au或者钯(Pd)。
或者，可选的，如图3F所示，源极S和漏极D为双层结构。
示例的，源极S包括耦接的源极欧姆接触层S1和源极加厚电极层S2，源极欧姆接触层S1相对源极加厚电极层S2靠近势垒层50设置，源极欧姆接触层S1与势垒层50形成欧姆接触。
源极欧姆接触层S1的材料的功函数小于源极加厚电极层S2的材料的功函数，通过设置源极欧姆接触层S1，来降低源极S与势垒层50接触面处的欧姆接触电阻。在此基础上，由于源极欧姆接触层S1的厚度通常比较薄，通过设置源极加厚电极层S2，来降低源极S整体的电阻。
示例的，漏极D包括耦接的漏极欧姆接触层D1和漏极加厚电极层D2，漏极欧姆接触层D1相对漏极加厚电极层D2靠近势垒层50设置，漏极欧姆接触层D1与势垒层50形成欧姆接触。
漏极欧姆接触层D1的材料的功函数小于漏极加厚电极层D2的材料的功函数，通过设置漏极欧姆接触层D1，来降低漏极D与势垒层50接触面处的欧姆接触电阻。在 此基础上，由于漏极欧姆接触层D1的厚度通常比较薄，通过设置漏极加厚电极层D2，来降低漏极D整体的电阻。
示例的，源极欧姆接触层S1和漏极欧姆接触层D1的材料，例如可以为Ti/Al/Ni/Au、Ti/Al/Pt/Au、Ti/Al/Ti等，源极加厚电极层S2和漏极加厚电极层D2的材料，例如可以为Au、Al、Cu等低电阻率的材料。其中，栅极G例如可以和源极欧姆接触层S1和漏极欧姆接触层D1同步形成。
值得注意的是，本申请实施例对源极欧姆接触层S1和源极加厚电极层S2的形状和大小不做限定，对漏极欧姆接触层D1和漏极加厚电极层D2的形状和大小也不做限定。图3F中的结构仅为一种示意，不做任何限定。
通过将源极S和漏极D设置为双层结构，源极欧姆接触层S1和漏极欧姆接触层D1的材料功函数较小，与势垒层50的接触面处的欧姆接触电阻较小，从而可以减小半导体器件的电阻，提高半导体器件的电流导通能力。
请继续参考图3B，在一些实施例中，半导体器件还包括场板80，场板80设置于栅极G远离衬底10一侧，与源极S耦接。
当然，根据需要，可以在场板80与栅极G之间设置一层或者多层层间绝缘层或者钝化层。
在一些实施例中，如图3B所示，沿垂直于衬底10的方向(或者理解为衬底10的厚度方向)，场板80靠近栅极G一侧与栅极G交叠。或者理解为，场板80在衬底10上的正投影，在靠近栅极G一侧处，与栅极G在衬底10上的正投影交叠。
通过只在栅极G靠近漏极D一侧处设置场板80，可减小场板80和栅极G的正对面积，从而降低半导体器件的栅源寄生电容(Cgs)，以降低场板80对半导体器件频率特性的影响。
在另一些实施例中，沿垂直于衬底10的方向场板80靠近栅极G一侧与栅极G不交叠。当然，为了提高场板80对栅极G边缘电场强度的减弱效果，可以尽量减小栅极G与场板80之间的间隙。
通过使栅极G与场板80不交叠，可尽量避免产生栅源寄生电容(Cgs)以降低场板80对半导体器件频率特性的影响。
其中，半导体器件可以包括一层场板80，半导体器件也可以包括多层场板80，多层场板80之间通过介质层隔离，多层场板80均与源极S耦接。图3B示意的场板80的结构仅为一种示意，不做任何限定。
当然，本申请实施例提供的半导体器件，可以根据需要设置绝缘层、钝化层以及平坦层等膜层。例如，半导体器件还包括覆盖源极加厚电极层S2、漏极加厚电极层D2以及场板80，对半导体器件进行表面钝化的钝化层，钝化层上设置有露出栅极G、源极S以及漏极D的开口，以实现焊盘与栅极G、源极S以及漏极D的信号互通。
其中，图3F所示的半导体器件的制备步骤，例如可以是：先在衬底10上依次形成成核层20、缓冲层30、沟道层40和势垒层50，然后形成抑制电流崩塌和静态电流跌落的第一空穴注入层61，再形成钝化层70对势垒层50进行表面钝化保护，再形成源极欧姆接触层S1、漏极欧姆接触层D1以及栅极G，再形成覆盖栅极G的层间绝缘层(或者钝化层)，再形成场板80，再形成源极加厚电极层S2以及漏极加厚电极层 D2，再形成对半导体器件进行表面钝化的钝化层。
由于半导体器件关断时，栅极G拐角处的电场强度较高，此处的高电场容易使半导体器件发生击穿，导致半导体器件漏电增大甚至永久性失效。而当半导体器件开启时，受材料表面及内部缺陷陷阱的影响，半导体器件会表现出电流崩塌及静态电流跌落问题。
而本示例提供的耗尽型(常开型)半导体器件，栅极G的部分底面与第一空穴注入层61接触形成等电位耦接，栅极G的部分底面与势垒层50接触形成肖特基接触。在图3D和图3E所示的结构中，在半导体器件关断时，第一空穴注入层61可以降低栅极G拐角处的电场强度，减少电子从栅极G流出以及被材料陷阱俘获的几率，起到平衡栅极G拐角处电场的作用，从而降低栅极G漏电，提升半导体器件栅极G稳定性。在图3B、图3D、图3E和图3F所示结构中，当半导体器件开态时，在栅极高压作用下，第一空穴注入层61向势垒层50的表面及沟道内注入空穴，平衡被材料表面或体内陷阱俘获的电子，使被俘获电子耗尽的二维电子气沟道迅速恢复，从而抑制电流崩塌和静态电流跌落问题。而且，虽然第一空穴注入层61对第一空穴注入层61下方的二维电子气具有耗尽作用，但是由于栅极G有部分结构直接与势垒层50形成肖特基接触，因此栅极G上的信号可直接传输至沟道内，不受第一空穴注入层61的影响。因此，本示例提供的半导体器件可以实现抑制电流崩塌和静态电流跌落的作用，且不增大半导体器件的导通电阻。
需要强调的是，在设计栅极G下方的第一空穴注入层61层时，应考虑第一空穴注入层61的厚度、掺杂浓度及在栅极G下方的分布比例等因素，确保第一空穴注入层61在半导体器件处于开态时，对第一空穴注入层61下方沟道的耗尽作用可以忽略，否则会影响半导体器件的导通电阻、开态电流及阈值等参数，还会增加栅驱动电压的摆幅。
示例二
示例二与示例一的主要不同在于：栅极G下方未设置第一空穴注入层61，漏极D的下方设置有第二空穴注入层62。
本示例提供一种半导体器件，结合图4A和图4B(图4A沿B1-B2向的剖视图)所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40和势垒层50、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于势垒层50远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第二空穴注入层62，漏极D包裹在第二空穴注入层62的外围。
衬底10、成核层20、缓冲层30、沟道层40、势垒层50的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
请继续参考图4B，在一些实施例中，第二空穴注入层62设置在势垒层50远离衬底10一侧。例如，第二空穴注入层62设置在势垒层50的表面上。
第二空穴注入层62的形成，可以是在形成势垒层50后，通过MOCVD生长法或MBE生长法形成空穴注入膜，然后通过ICP刻蚀的方式选择性去除不需要区域的空穴 注入膜，以形成第二空穴注入层62。
第二空穴注入层62通过外延生长结合刻蚀工艺形成，无需再生长工艺，不会增加工艺复杂度。
第二空穴注入层62的形成，也可以是在形成势垒层50后，通过在漏极D下方选择性外延生长工艺，直接形成第二空穴注入层62。
第二空穴注入层62的材料，例如可以是P型半导体材料。P型半导体材料可以为P型掺杂(如镁(Mg)掺杂)的P型氮化镓(p-GaN)，P型氮化铝(p-AlN)，P型氮化铟(p-InN)，P型铝镓氮(p-AlGaN)，P型铟氮化铝(p-InAlN)，P型铟氮化镓(p-InGaN)，P型氮化铟铝镓(p-In xAl xGa 1-x-yN)(其中x+y≤1)，或其他P型半导体材料(如氧化镍(NiO)等)。
关于第二空穴注入层62的形状，图4B视角的截面图来看，第二空穴注入层62的截面形状可以为矩形或者梯形等形状。
此外，可选的，如图4A所示，第二空穴注入层62为面状结构。
从图4A视角的俯视图来看，第二空穴注入层62的形状可以为正方形、长方形、圆形、椭圆形、梯形等形状。
第二空穴注入层62为面状结构，结构简单，便于制备。
或者，可选的，如图4C所示，第二空穴注入层62包括多个间隔设置的块状结构。
从图4C视角的俯视图来看，每个块状结构的形状可以为正方形、长方形、圆形、椭圆形、梯形等形状。多个块状结构的形状可以相同，多个块状结构的形状也可以不相同。多个块状结构沿漏极D的延伸方向可以排布成一排，如图4C所示，多个块状结构沿漏极D的延伸方向也可以排布成多排。多个块状结构可以有规律的排布，多个块状结构也可以没有规律的排布。
请继续参考图4B，在一些实施例中，源极S和漏极D设置于势垒层50上，与势垒层50形成欧姆接触。
其中，源极S、漏极D例如可以通过光刻和刻蚀工艺形成，源极S、漏极D例如可以同步形成。
可选的，如图4B所示，源极S和漏极D为单层结构。这样一来，结构简单，便于制备。
或者，可选的，如图4D所示，源极S和漏极D为双层结构。
示例的，源极S包括耦接的源极欧姆接触层S1和源极加厚电极层S2，源极欧姆接触层S1相对源极加厚电极层S2靠近势垒层50设置，源极欧姆接触层S1与势垒层50形成欧姆接触。
漏极D包括耦接的漏极欧姆接触层D1和漏极加厚电极层D2，漏极欧姆接触层D1相对漏极加厚电极层D2靠近势垒层50设置，漏极欧姆接触层D1与势垒层50形成欧姆接触。
值得注意的是，本申请实施例对源极欧姆接触层S1和源极加厚电极层S2的形状和大小不做限定，对漏极欧姆接触层D1和漏极加厚电极层D2的形状和大小也不做限定。图4D中的结构仅为一种示意，不做任何限定。
通过将源极S和漏极D设置为双层结构，源极欧姆接触层S1和漏极欧姆接触层 D1的材料功函数较小，与势垒层50的接触面处的欧姆接触电阻较小，从而可以减小半导体器件的电阻，提高半导体器件的电流导通能力。
在此基础上，如图4B所示，漏极D还包裹在第二空穴注入层62的外围。或者理解为，第二空穴注入层62埋于漏极D内。
关于漏极D与第二空穴注入层62的结构关系，可选的，如图4B和图4D所示，第二空穴注入层62设置在势垒层50的表面上，漏极D包裹第二空穴注入层62的未与势垒层61接触的表面。
也就是说，漏极D包裹第二空穴注入层62的侧面和顶面。其中，第二空穴注入层62的侧面可以理解为是第二空穴注入层62与势垒层50相交的表面，第二空穴注入层62的顶面可以理解为是第二空穴注入层62远离势垒层50的表面。
基于图4B所示的结构，在形成势垒层50后，可直接继续采用生长工艺形成第二空穴注入层62，然后形成漏极D。工艺简单，易于实现。
关于漏极D与第二空穴注入层62的结构关系，或者可选的，如图4E所示，漏极D包括漏极欧姆接触层D1和漏极加厚电极层D2，第二空穴注入层62设置在漏极欧姆接触层D1与漏极加厚电极层D2之间。
也就是说，漏极D包裹第二空穴注入层62的侧面、顶面和底面。第二空穴注入层62的底面与漏极欧姆接触层D1接触，第二空穴注入层62的侧面和顶面被漏极加厚电极层D2覆盖。
基于图4E所示的结构，漏极欧姆接触层D1的底面全部与势垒层50接触，第二空穴注入层62下方的二维电子气可以不断开，降低第二空穴注入层62对沟道电阻的影响。
也就是说，本示例中漏极D覆盖第二空穴注入层62，第二空穴注入层62接收漏极D的信号，向势垒层50的表面及内部注入空穴，以平衡被缺陷陷阱俘获的电子。
在一些实施例中，半导体器件还包括钝化层70和场板80，钝化层70和场板80的结构可以和示例一中相同，可参考示例一中的相关描述，此处不再赘述。
其中，图4D所示的半导体器件的制备步骤，例如可以是：先在衬底10上依次形成成核层20、缓冲层30、沟道层40和势垒层50，然后形成抑制电流崩塌和静态电流跌落的第二空穴注入层62，再形成钝化层70对势垒层50进行表面钝化保护，再形成源极欧姆接触层S1、漏极欧姆接触层D1以及栅极G，再形成覆盖栅极G的层间绝缘层(或者钝化层)，再形成场板80，再形成源极加厚电极层S2以及漏极加厚电极层D2，再形成对半导体器件进行表面钝化的钝化层。
本示例提供的耗尽型(常开型)半导体器件，漏极D包裹在第二空穴注入层62的外围，也就是说，第二空穴注入层62的外圈包裹有漏极D。那么，第二空穴注入层62与漏极D直接接触形成等电位耦接，且漏极D有部分结构位于第二空穴注入层62靠近栅极G一侧。这样一来，在半导体器件关态时，漏极D高压使第二空穴注入层62向势垒层50表面及沟道内注入空穴，调制栅极G和漏极D间的电场，来降低沟道电子被材料陷阱俘获的几率，以及平衡被材料陷阱(表面或体内陷阱)俘获的电子，使被俘获电子耗尽的沟道迅速恢复，以降低沟道电流对关态漏极电压的敏感程度，从而起到抑制半导体器件开关过程中的电流崩塌和静态电流跌落的作用。而且，虽然第 二空穴注入层62对第二空穴注入层62下方的二维电子气具有耗尽作用。但是由于漏极D有部分结构位于第二空穴注入层62靠近栅极G一侧，半导体器件中的电流可通过第二空穴注入层62靠近栅极G一侧的漏极D结构进入漏极D内，而不经过第二空穴注入层62下方的二维电子气耗尽区。因此，本示例提供的半导体器件在实现抑制电流崩塌和静态电流跌落的作用的同时，不影响半导体器件的开态导通电阻。且本申请实施例提供的半导体器件可以应用于射频器件，也可以应用于功率器件。
示例三
示例三与示例一和示例二的主要不同在于：示例三提供一种金属-绝缘体-半导体场效应晶体管(metal insulator semiconductor field transistors，MISFET)，示例一和示例二提供一种高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)。
本示例提供一种半导体器件，如图5A所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40、势垒层50以及绝缘层90、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于绝缘层90远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第一空穴注入层61。
绝缘层90具有开口，第一空穴注入层61位于开口内。也就是说，绝缘层90位于第一空穴注入层61的外围。源极S和漏极D通过绝缘层90上的开口与势垒层60形成欧姆接触。本申请实施例对绝缘层90的材料不做限定，例如可以是SiO、SiN等材料。
衬底10、成核层20、缓冲层30、沟道层40、势垒层50、第一空穴注入层61的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
或者，本示例提供一种半导体器件，如图5B所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40和势垒层50以及绝缘层90、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于绝缘层90远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第二空穴注入层62。
绝缘层90具有开口，漏极D位于开口内。也就是说，绝缘层90位于漏极D的外围。源极S和漏极D通过绝缘层90上的开口与势垒层60形成欧姆接触。本申请实施例对绝缘层90的材料不做限定，例如可以是SiO、SiN等材料。
衬底10、成核层20、缓冲层30、沟道层40、势垒层50、第二空穴注入层62的结构与示例二中相同，可参考示例二中的相关描述，此处不再赘述。
当然，如图5A和图5B所示，半导体器件还可以包括钝化层70和场板80，钝化层70和场板80的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
半导体器件为MISFET器件时，图5A和图5B所示的结构也具有在实现抑制电流崩塌和静态电流跌落的作用，图5B所示结构中的空穴注入层62不影响半导体器件的开态导通电阻。
示例四
示例四与示例二的主要不同在于：示例四提供一种增强型(常关型)HEMT器件，示例二提供的为一种耗尽型(常开型)HEMT器件。
本申请实施例提供一种半导体器件，如图6所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40和势垒层50、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于势垒层50远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第二空穴注入层62和第三空穴注入层63，漏极D包裹在第二空穴注入层62的外围、栅极G设置在第三空穴注入层63上。
HEMT器件的工作原理为：源极S和漏极D分别与势垒层50形成导电欧姆接触，栅极G与势垒层50形成肖特基接触。沟道层40中虚线代表HEMT器件中沟道层40和势垒层50形成的异质结中通过极化作用产生的2DEG。2DEG用于在电场的作用下，高效地传导电子。源极S和漏极D用于在电场的作用下使2DEG在源极S和漏极D之间的沟道层40内流动，源极S和漏极D之间的导通发生在沟道层40中的二维电子气处。栅极G设置在源极S和漏极D之间，用于允许或阻碍二维电子气的通过。第三空穴注入层63可以调节沟道层40和势垒层50形成的异质结的能带结构，使第三空穴注入层63正下方的电子耗尽。如图6所示，第三空穴注入层63的存在，使得2DEG在无偏压的情况下处于夹断状态，2DEG在源极S和漏极D之间的沟道层40内无法连通流动，HEMT器件处于关闭状态。
第三空穴注入层63可以和第二空穴注入层62的材料相同，第三空穴注入层63可以和第二空穴注入层62也可以在同一次制备工艺中形成。
第三空穴注入层63的形成，可以是在形成势垒层50后，通过MOCVD生长法或MBE生长法形成空穴注入膜，然后通过ICP刻蚀的方式选择性去除不需要区域的空穴注入膜，以形成第二空穴注入层62和第三空穴注入层63。
第三空穴注入层63通过外延生长结合刻蚀工艺形成，无需再生长工艺，不会增加工艺复杂度。
第三空穴注入层63的形成，也可以是在形成势垒层50后，通过在栅极G下方及漏极D下方选择性外延生长(selective epitaxy growth，SEG)工艺，直接形成第三空穴注入层63和第二空穴注入层62。
此处释明的是，本示例中，栅极G与第三空穴注入层63的结构关系为：栅极G朝向衬底10的底面与第三空穴注入层63接触，而不会与势垒层50接触。示例一中，栅极G与第一空穴注入层61的结构关系为：栅极G朝向衬底10的底面，部分与第一空穴注入层61接触，部分与势垒层50接触。所以，第三空穴注入层63在半导体器件中发挥的作用和第一空穴注入层61在半导体器件中发挥的作用不同。
请继续参考图6，在一些实施例中，第三空穴注入层63的截面形状为矩形。这样一来，与图2B所示的增强型半导体器件相比，第三空穴注入层63制备时无需考虑凹栅槽(recessed-gate)结构和再生长(regrow)工艺，降低了工艺复杂度。
衬底10、成核层20、缓冲层30、沟道层40、势垒层50、第二空穴注入层62的结构与示例二中相同，可参考示例二中的相关描述，此处不再赘述。
当然，如图6所示，半导体器件还可以包括钝化层70和场板80，钝化层70和场 板80的结构与示例二中相同，可参考示例二中的相关描述，此处不再赘述。
半导体器件为增强型HEMT器件时，也具有在实现抑制电流崩塌和静态电流跌落的作用的同时，不影响半导体器件的开态导通电阻的效果。
示例五
示例五与示例一的主要不同之处在于：示例五提供的半导体器件不仅包括栅极G下方的第一空穴注入层61，还包括漏极D下方的第二空穴注入层62。
本示例提供一种半导体器件，如图7A所示，半导体器件主要包括：衬底10、依次层叠设置于衬底10上的成核层20、缓冲层30、沟道层40和势垒层50、并排设置于势垒层50远离衬底10一侧的源极S和漏极D、设置于势垒层50远离衬底10一侧且位于源极S和漏极D之间的栅极G、设置于势垒层50远离衬底10一侧的第一空穴注入层61和第二空穴注入层62，栅极G覆盖第一空穴注入层61的至少部分，漏极D包裹在第二空穴注入层62的外围。
当然，如图7B所示，半导体器件还可以包括绝缘层90，半导体器件包括的晶体管为MISFET。
衬底10、成核层20、缓冲层30、沟道层40、势垒层50、第二空穴注入层62的结构与示例二中相同，可参考示例二中的相关描述，此处不再赘述。
栅极G与第一空穴注入层61的结构关系，可参考示例一中的相关描述，此处不再赘述。漏极D与第二空穴注入层62的结构关系，可参考示例二中的相关描述，此处不再赘述。
绝缘层90位于栅极G与势垒层50之间，绝缘层90位于第一空穴注入层61和漏极D的外围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    沟道层和势垒层，依次层叠设置于所述衬底一侧；
    栅极、源极、漏极以及第一空穴注入层，设置于所述势垒层远离所述衬底一侧；所述栅极位于所述源极和所述漏极之间；
    所述栅极的部分底面覆盖于所述第一空穴注入层的顶面上，所述栅极的部分底面与所述势垒层接触。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述栅极覆盖所述第一空穴注入层的顶面和侧面。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述栅极覆盖所述第一空穴注入层的部分顶面。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，所述半导体器件还包括第二空穴注入层，所述第二空穴注入层设置于所述势垒层远离所述衬底一侧；所述漏极包裹所述第二空穴注入层。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述漏极包括欧姆接触层和加厚电极层；
    所述第二空穴注入层设置在所述势垒层的表面上；
    或者，
    所述第二空穴注入层设置在所述欧姆接触层与所述加厚电极层之间。
  6. 根据权利要求1-5任一项所述的半导体器件，其特征在于，
    所述第一空穴注入层包括多个间隔设置的块状结构；
    或者，
    所述第一空穴注入层为面状结构。
  7. 根据权利要求4或5所述的半导体器件，其特征在于，
    所述第二空穴注入层包括多个间隔设置的块状结构；
    或者，
    所述第二空穴注入层为面状结构。
  8. 根据权利要求1-7任一项所述的半导体器件，其特征在于，所述半导体器件还包括绝缘层，所述绝缘层设置于所述栅极与所述势垒层之间，所述绝缘层位于所述第一空穴注入层和所述漏极的外围。
  9. 根据权利要求1-8任一项所述的半导体器件，其特征在于，所述第一空穴注入层的材料包括P型半导体材料。
  10. 一种半导体器件，其特征在于，包括：
    衬底；
    沟道层和势垒层，依次层叠设置于所述衬底一侧；
    栅极、源极、漏极以及第二空穴注入层，设置于所述势垒层远离所述衬底一侧；所述栅极位于所述源极和所述漏极之间；所述漏极包裹所述第二空穴注入层。
  11. 根据权利要求10所述的半导体器件，其特征在于，所述半导体器件还包括第 三空穴注入层，所述第三空穴注入层与所述势垒层接触；所述栅极设置在所述第三空穴注入层上，所述栅极的底面与所述第三空穴注入层接触。
  12. 根据权利要求10所述的半导体器件，其特征在于，所述半导体器件还包括绝缘层，所述绝缘层设置于所述栅极与所述势垒层之间，所述绝缘层位于所述漏极的外围。
  13. 一种电子设备，其特征在于，包括半导体器件及天线；所述半导体器件用于将射频信号放大后输出至所述天线向外辐射；
    其中，所述半导体器件为如权利要求1-9任一项或者权利要求10-12任一项所述的半导体器件。
  14. 一种电子设备，其特征在于，包括半导体器件及与所述半导体器件电连接的印刷电路板；
    其中，所半导体器件为如权利要求1-9任一项或者权利要求10-12任一项所述的半导体器件；所述半导体器件的衬底为导电型衬底。
  15. 一种半导体器件的工作方法，其特征在于，包括半导体器件，所述半导体器件包括衬底；沟道层和势垒层，依次层叠设置于所述衬底一侧；栅极、源极、漏极以及第一空穴注入层，设置于所述势垒层远离所述衬底一侧；所述栅极位于所述源极和所述漏极之间；所述栅极的部分底面覆盖于所述第一空穴注入层的顶面上，所述栅极的部分底面与所述势垒层接触；
    所述半导体器件的工作方法包括：所述第一空穴注入层接收所述栅极的信号，向所述势垒层注入空穴。
  16. 根据权利要求15所述的半导体器件的工作方法，其特征在于，所述半导体器件还包括第二空穴注入层，所述第二空穴注入层设置于所述势垒层远离所述衬底一侧；所述漏极包裹所述第二空穴注入层；
    所述半导体器件的工作方法还包括：所述第二空穴注入层接收所述漏极的信号，向所述势垒层注入空穴。
  17. 一种半导体器件的工作方法，其特征在于，包括半导体器件，衬底；沟道层和势垒层，依次层叠设置于所述衬底一侧；栅极、源极、漏极以及第二空穴注入层，设置于所述势垒层远离所述衬底一侧；所述栅极位于所述源极和所述漏极之间；所述漏极包裹所述第二空穴注入层；
    所述半导体器件的工作方法还包括：所述第二空穴注入层接收所述漏极的信号，向所述势垒层注入空穴。
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