WO2023097520A1 - 半导体器件及电子设备 - Google Patents

半导体器件及电子设备 Download PDF

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Publication number
WO2023097520A1
WO2023097520A1 PCT/CN2021/134648 CN2021134648W WO2023097520A1 WO 2023097520 A1 WO2023097520 A1 WO 2023097520A1 CN 2021134648 W CN2021134648 W CN 2021134648W WO 2023097520 A1 WO2023097520 A1 WO 2023097520A1
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Prior art keywords
gate
field plate
semiconductor device
source
drain
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PCT/CN2021/134648
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English (en)
French (fr)
Inventor
乐伶聪
仲正
李海军
胡荟兰
马平
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华为技术有限公司
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Priority to PCT/CN2021/134648 priority Critical patent/WO2023097520A1/zh
Publication of WO2023097520A1 publication Critical patent/WO2023097520A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the technical field of semiconductors, and in particular to a semiconductor device and electronic equipment.
  • semiconductor devices with high thermal conductivity, high electron drift rate, high temperature resistance, and stable chemical properties are widely used in high frequency, high temperature, and microwave fields.
  • Embodiments of the present application provide a semiconductor device and electronic equipment, which are used to increase the working voltage of the semiconductor device.
  • a semiconductor device is provided, and the semiconductor device may be, for example, a high electron mobility transistor device.
  • the semiconductor device includes: a substrate; a channel layer and a barrier layer sequentially stacked on the substrate; a source and a drain on the barrier layer; a first gate and a second gate on the barrier layer The gate, the first gate and the second gate are located between the source and the drain, the second gate is arranged between the first gate and the drain; the first gate field plate is at least partially arranged on the first gate The side very close to the drain electrode; the first source field plate, the first source field plate covers the first gate field plate.
  • the electric field distribution between the first gate and the drain can be changed, and the electric field at the side of the first gate close to the drain can be reduced. Electric field strength. Therefore, the possibility of breakdown of the material of the potential barrier layer can be reduced, the breakdown voltage of the semiconductor device can be increased, and the working voltage of the semiconductor device can be further increased.
  • the second gate can reduce the feedback path between the first gate and the drain, and play a certain shielding role, which can reduce
  • the gate-to-drain parasitic capacitance between the first gate and the drain reduces the influence of the gate-to-drain parasitic capacitance on the performance of the semiconductor device, so as to improve the operating voltage of the semiconductor device and reduce the influence on other performances of the semiconductor device.
  • the semiconductor device further includes a second gate field plate; the second gate field plate is at least partially located on a side of the second gate close to the drain.
  • the electric field intensity in the vicinity of the second gate can be greatly reduced. Therefore, the possibility of breakdown of the material of the barrier layer can be reduced, the breakdown voltage of the semiconductor device can be further improved, and the performance of the semiconductor device can be guaranteed.
  • the second gate field plate can play a certain shielding effect, further expand the depletion region, and reduce the gate-to-drain parasitic capacitance between the first gate and the drain.
  • the semiconductor device further includes a second source field plate, and the second source field plate covers the second gate field plate.
  • the existence of the conductive structure of the second source field plate can adjust the electric field distribution between the second gate field plate and the drain, thereby reducing the The electric field strength of the semiconductor device can be reduced to reduce the peak electric field of the semiconductor device and further increase the breakdown voltage of the semiconductor device.
  • the first source field plate covers the second gate field plate.
  • the first source field plate can overlap the second gate, so that even if the distance between the first gate and the second gate is reduced, the process of the first source field plate will not be excessively increased. Difficulty, easy to achieve.
  • the first source field plate is connected to the second source field plate.
  • the first source field plate and the second source field plate can be prepared using the existing process without changing the preparation process of the first source field plate.
  • the gap between the first source field plate and the second source field plate there is a gap between the first source field plate and the second source field plate.
  • the gap provided between the first source field plate and the second source field plate can improve the small signal gain of the semiconductor device compared to connecting the first source field plate and the second source field plate.
  • the distance between the first grid field plate and the second grid is 0.5 ⁇ m-2.7 ⁇ m.
  • the saturation current of the semiconductor device can be significantly increased, so as to increase the power of the semiconductor device.
  • the knee point voltage of the semiconductor device will be increased, resulting in a decrease in the efficiency of the semiconductor device.
  • the gate-to-drain parasitic capacitance of the semiconductor device will be increased, resulting in a decrease in the gain characteristic of the semiconductor device. Therefore, by setting the distance between the first gate field plate and the second gate within the range of 0.5 ⁇ m-2.7 ⁇ m, the performance and reliability requirements of the semiconductor device can be comprehensively met.
  • the first gate field plate includes a first part disposed on the side of the first gate close to the drain and a second part disposed on the side of the first gate close to the source, the first part and the second The two parts are contacted and connected with the first gate respectively.
  • the semiconductor device further includes a third gate, and the third gate is disposed between the second gate and the drain.
  • the third gate is disposed between the second gate and the drain.
  • the semiconductor device further includes a third gate field plate; the third gate field plate is at least partially disposed on a side of the third gate close to the drain.
  • the semiconductor device further includes a third source field plate; the third source field plate covers the third gate field plate.
  • a semiconductor device in a second aspect of the embodiments of the present application, and the semiconductor device may be, for example, a high electron mobility transistor device.
  • the semiconductor device includes: a substrate; a channel layer and a barrier layer sequentially stacked on the substrate; a source and a drain on the barrier layer; a first gate and a second gate on the barrier layer The gate, the first gate and the second gate are located between the source and the drain, the first gate is arranged between the second gate and the drain; the first gate field plate is at least partially arranged on the first gate The side very close to the drain electrode; the first source field plate, the first source field plate covers the first gate field plate.
  • the electric field distribution between the second gate and the drain can be changed, and the electric field at the side of the second gate close to the drain can be reduced. Electric field strength. Therefore, the possibility of breakdown of the material of the potential barrier layer can be reduced, the breakdown voltage of the semiconductor device can be increased, and the working voltage of the semiconductor device can be further increased.
  • the first gate can reduce the feedback path between the second gate and the drain, and play a certain shielding role, which can reduce
  • the gate-drain parasitic capacitance between the second gate and the drain reduces the influence of the gate-drain parasitic capacitance on the performance of the semiconductor device, so as to improve the operating voltage of the semiconductor device and reduce the influence on other performances of the semiconductor device.
  • the third aspect of the embodiments of the present application provides an electronic device, including a semiconductor device and an antenna; the semiconductor device is used to amplify a radio frequency signal and output it to the antenna for external radiation; wherein, the semiconductor device is any one of the first aspect or the first Two aspects of semiconductor devices.
  • the electronic device provided by the third aspect of the embodiment of the present application includes any one of the first aspect or the semiconductor device of the second aspect, and its beneficial effect is the same as that of the semiconductor device, and will not be repeated here.
  • the fourth aspect of the embodiments of the present application provides an electronic device, including a semiconductor device and a printed circuit board electrically connected to the semiconductor device; wherein, the semiconductor device is the semiconductor device according to any one of the first aspect or the second aspect;
  • the substrate of the semiconductor device is a conductive substrate.
  • the electronic device provided by the fourth aspect of the embodiment of the present application includes any one of the first aspect or the semiconductor device of the second aspect, and its beneficial effect is the same as that of the semiconductor device, so it will not be repeated here.
  • FIG. 1A is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 1B is a schematic structural diagram of an active antenna unit provided by an embodiment of the present application.
  • FIG. 1C is a schematic structural diagram of another electronic device provided by the embodiment of the present application.
  • FIG. 2A is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • FIG. 2B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 6A is an output curve diagram of a semiconductor device shown in FIG. 2B provided by an embodiment of the present application.
  • FIG. 6B is an output graph of the semiconductor device shown in FIG. 5 provided by the embodiment of the present application.
  • FIG. 7A is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 7B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 9 is an electric field distribution diagram at various positions of a semiconductor device provided by an embodiment of the present application.
  • FIG. 10A is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 10B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 11A is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 11B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 11C is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the term “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • two-dimensional electron gas (2DEG) refers to: the movement of electrons in the direction perpendicular to the interface is bound by the potential well and quantized, while its movement parallel to the surface Movement is still free, and such free electrons in two-dimensional directions are called two-dimensional electron gas.
  • the term "semi-insulating (SI)" refers to: the resistivity is greater than 10 5 ⁇ cm.
  • a semi-insulating SiC substrate means that the resistivity of the SiC substrate is greater than 10 5 ⁇ cm.
  • the term "current collapse effect” refers to the effect that when the drain voltage of a semiconductor device exceeds a certain value, the current begins to decrease as the drain voltage increases, and cannot reach an ideal value.
  • knee point voltage refers to the knee point voltage when a semiconductor device enters a saturation region from a linear region.
  • the term “depletion region” refers to: in semiconductor pn junctions, Schottky junctions, and heterojunctions, the energy band near the interface is bent due to the difference in the original chemical potential of the semiconductors on both sides of the interface, so that An interface region where the concentration of electrons or holes in the band-bending region decreases.
  • An embodiment of the present application provides an electronic device, which can be, for example, a charger, a charging small household appliance, a drone, aerospace equipment, a lidar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network , fifth-generation mobile communication technology) communication equipment and other different types of user equipment or terminal equipment; the electronic equipment can also be network equipment such as base stations.
  • the electronic device may also be a device such as a power amplifier used in the above-mentioned electronic device.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • the third-generation semiconductor gallium nitride (GaN) material has excellent characteristics, such as a large forbidden band width (3.4eV), a high breakdown electric field (3.3MV/cm), a large saturation rate (2.5e7cm/ s), and the high 2DEG density at the AlGaN/GaN heterostructure interface brought about by the polarization effect, so that the GaN high-electron-mobility transistor (HEMT) device can work in a relatively In high voltage, high temperature and high frequency, it is widely used as radio frequency device or power device.
  • HEMT GaN high-electron-mobility transistor
  • a base station 1 includes a base band processing unit (base band unit, BBU) 11 and an active antenna unit (active antenna unit, AAU) 12.
  • BBU11 is mainly responsible for baseband digital signal processing, for example, FFT (fast fourier transform, fast Fourier transform)/IFFT (inverse fast fourier transform, inverse fast Fourier transform), modulation/demodulation, channel coding/decoding, etc.
  • the AAU 12 includes a calculation unit 121 , a first transmission unit 122 and an antenna unit 123 .
  • the computing unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212 and a power supply unit 1213, the control unit 1210, the second transmission unit 1211, the baseband unit 1212 and the power supply unit 1213 are electrically connected to each other, and the control unit 1210 is used for Responsible for the control of radio frequency signals, the second transmission unit 1211 is used to be responsible for the transmission of radio frequency signals, and the baseband unit 1212 is used to be responsible for the conversion of digital signals and analog signals.
  • the baseband unit 1212 is, for example, a DAC (digital to analog converter, digital to analog converter) ), the DAC can convert the digital signal output by the BBU 11 into an analog signal, and the power supply unit 1213 is electrically connected to the power supply 124 for powering the control unit 1210, the second transmission unit 1211 and the baseband unit 1212 in the computing unit 121.
  • the first transmission unit 122 is used for transmitting and amplifying radio frequency signals.
  • the first transmission unit 122 includes an RF (radio frequency, radio frequency) unit 1221 and a PA (power amplifier, power amplifier) 1222, the RF unit 1221 is used to convert the analog signal into a low-power radio frequency signal, and the PA1222 is used to convert the low-power radio frequency
  • the signal is output to the antenna unit 123 after power amplification.
  • the antenna unit 123 is responsible for radiating the radio frequency signal to the outside.
  • the AAU 12 may include multiple RF units 1221 , multiple PAs 1222 and multiple antenna units 123 . It should be noted that the above PA1222 may be a semiconductor device.
  • the electronic equipment provided by the embodiment of the present application is not limited to the base station shown in Figure 1A and Figure 1B, any electronic equipment that needs to use a power amplifier to amplify the signal belongs to the scope of the present application The application scenario of the embodiment.
  • the charger 2 may include a power device, a resistor R, an inductor L, a capacitor C, etc.
  • the power device may be, for example, a semiconductor device.
  • the semiconductor device, the resistor R, the inductor L and the capacitor C may be interconnected through a printed circuit board (PCB).
  • PCB printed circuit board
  • the electronic device provided by the embodiment of the present application is not limited to the charger shown in FIG. 1C, any electronic device that needs to use a power device belongs to the application scenario of the embodiment of the present application .
  • Increasing the operating voltage of semiconductor devices can effectively improve the microwave power characteristics of semiconductor devices, and increasing the breakdown voltage of semiconductor devices is a prerequisite for increasing the operating voltage of semiconductor devices.
  • the semiconductor device includes a substrate 20, a channel layer 30 and a barrier layer 40 disposed on the substrate 20 (as a heterostructure in the semiconductor device), and a barrier layer disposed on the potential
  • the source S, the drain D and the gate G on the barrier layer 40 , the source S and the drain D form an ohmic contact with the barrier layer 40
  • the gate G forms a Schottky contact with the barrier layer 40
  • the semiconductor device further includes a gate field plate (gate field plate, GFP), and there is a distance between the gate field plate GFP and the barrier layer 40 .
  • GFP gate field plate
  • the gate field plate GFP is equivalent to extending the gate G to the drain D side, which can change the electric field distribution between the gate G and the drain D, and lead the concentration of the electric field to To the top corner of the gate field 50 close to the drain D, instead of being located at the sharp corner of the gate G close to the drain D, is equivalent to reducing the electric field intensity at the side of the gate G close to the drain D.
  • the electric field concentration point is located on the side of the gate field plate GFP close to the drain D, there is a distance between the gate field plate GFP and the barrier layer 40 . Therefore, the possibility of breakdown of the material of the barrier layer 40 can be reduced, the breakdown voltage of the semiconductor device can be improved, and the performance of the semiconductor device can be guaranteed.
  • gate-to-drain parasitic capacitance Cgd (or called feedback capacitance) between the gate G and the drain D.
  • the gate-to-drain parasitic capacitance Cgd will be further increased, resulting in a small signal of the semiconductor device. Gain, current gain cutoff frequency, and power gain cutoff frequency decrease.
  • the semiconductor device further includes a source field plate (source field plate, SFP), and the source field plate SFP is disposed above the gate field plate GFP and overlaps the gate field plate GFP.
  • source field plate source field plate
  • the feedback path between the gate G and the drain D can be blocked, thereby reducing the gate-drain parasitic capacitance Cgd of the semiconductor device, and improving the small signal gain and current gain cut-off frequency of the semiconductor device and the power gain cutoff frequency.
  • the existence of the conductive structure of the source field plate SFP can adjust the electric field distribution between the gate field plate GFP and the drain D, thereby reducing the electric field intensity at the side of the gate G close to the drain D, so as to reduce the peak electric field of the semiconductor device , to further increase the breakdown voltage of semiconductor devices. After the electric field intensity is reduced, the probability of electrons in the channel being excited by the strong electric field to enter the surface state can be reduced, thereby suppressing the current collapse effect of the semiconductor device.
  • the introduction of the source field plate SFP will increase the gate-source parasitic capacitance Cgs of the semiconductor device, which will deteriorate the frequency characteristics of the semiconductor device.
  • the source field plate SFP is extended toward the drain D side.
  • this approach has a limited improvement in small-signal gain, and on the other hand, it will significantly increase the gate-source parasitic capacitance Cgs of the semiconductor device, which in turn may reduce the drain efficiency of the semiconductor device (drain efficiency), resulting in The frequency characteristics of the semiconductor device deteriorate.
  • the gate-to-drain parasitic capacitance Cgd is reduced by reducing the gate length (the dimension from the source S to the drain D direction), so as to further improve the gain characteristics of the semiconductor device, such as using a gate length of 0.25 um, or a gate length process with a gate length of 0.1um, etc.
  • a shorter grid length requires higher precision lithography equipment (such as electron beam lithography equipment), or a more complex process (such as line width shrinking process).
  • a shorter gate length may also cause short channel effects, reduce the output impedance of the semiconductor device, and may cause poor turn-off characteristics under high drain voltage conditions.
  • the semiconductor device mainly includes: a substrate 20, a channel layer 30 and a barrier layer 40 stacked on the substrate 20 in sequence, and arranged side by side on the barrier layer 40
  • the aforementioned substrate 20 is a diamond substrate or a silicon carbide (SiC) substrate.
  • the grown SiC substrate is a conductive substrate if the purity of the raw material is not high.
  • the grown SiC substrate is a semi-insulating substrate.
  • the diamond substrate formed by normal growth is a semi-insulating substrate.
  • the formed diamond substrate is a conductive substrate.
  • the semiconductor device when the substrate 20 is a conductive substrate, the semiconductor device is used as a power device in an electronic device, and is interconnected with a PCB in the electronic device.
  • the semiconductor device In the case that the substrate 20 is a semi-insulating substrate, the semiconductor device is used as a radio frequency device in electronic equipment, and realizes signal communication with an antenna in the electronic equipment.
  • the thermal conductivity of the diamond substrate is generally 1000W ⁇ m -1 ⁇ K -1 to 2000W ⁇ m -1 ⁇ K -1
  • the thermal conductivity of the SiC substrate is generally about 370W ⁇ m -1 ⁇ K -1 .
  • the substrate 20 is a diamond substrate or a SiC substrate, the heat dissipation capability of the substrate 20 is relatively high, thereby improving the heat dissipation capability of the semiconductor device.
  • the semiconductor device further includes a nucleation layer 50 .
  • the nucleation layer 50 is disposed on the substrate 20 , for example, the nucleation layer 50 is disposed on the surface of the substrate 20 .
  • the method for forming the nucleation layer 50 may be, for example, metal-organic chemical vapor deposition (MOCVD) growth method or molecular beam epitaxy (molecular beam epitaxy, MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the material of the nucleation layer 50 may include, for example, one or more of GaN, AlGaN, and aluminum nitride (AlN).
  • the function of the nucleation layer 50 is to match the lattice structure of the substrate 20 with the lattice structure of the channel layer 30.
  • the nucleation layer 50 and then fabricate the channel layer 30 on the nucleation layer 50 with a smaller lattice structure difference from the nucleation layer 50, wherein the nucleation layer 50 may adopt a superlattice structure.
  • a repeating unit of a superlattice structure is composed of two different semiconductor material layers. When the thickness and period length of the two semiconductor material layers are smaller than the mean free path of electrons, quantum size effects can be generated in the superlattice structure. At this point, the wells sandwiched between the two semiconductor material layers of the superlattice structure are quantum wells.
  • the electrons move in a direction parallel to the interface of the nucleation layer 50, and the lateral migration of the electrons is improved, thereby avoiding or reducing the direct vertical entry of the electrons into the substrate parallel to the interface 20, thereby reducing the leakage of the substrate 20.
  • the semiconductor device further includes a graded buffer layer 60 .
  • the graded buffer layer 60 is disposed on the side of the nucleation layer 50 away from the substrate 20 , for example, the graded buffer layer 60 is disposed on the surface of the nucleation layer 50 away from the substrate 20 .
  • the method of forming the graded buffer layer 60 may, for example, adopt the MOCVD process to epitaxially grow an AlGaN graded layer whose Al (aluminum) composition gradually decreases.
  • an Al 0.8 Ga 0.2 N layer, an Al 0.5 Ga 0.5 N layer, and an Al 0.2 Ga 0.8 N layer are sequentially formed on the side of the nucleation layer 50 away from the substrate 20 by MOCVD process to form the graded buffer layer 60 .
  • the composition of the graded buffer layer 60 may be different from that when the semiconductor device is used as a power device.
  • the function of the graded buffer layer 60 is that the band gap between the graded buffer layer 60 and the channel layer 30 is different, which can make the potential well depth of the heterojunction formed by the barrier layer 40 and the channel layer 30 deeper, thereby improving the two-dimensional electron density.
  • Gas (two-dimensional electron gas, 2DEG) concentration In addition, in order to reduce the decrease in mobility caused by electron scattering, the graded buffer layer 60 generally adopts an undoped structure.
  • the channel layer 30 is disposed on the substrate 20 .
  • the channel layer 30 is disposed on the surface of the substrate 20 .
  • the channel layer 30 is disposed on the surface of the graded buffer layer 60 .
  • the method of forming the channel layer 30 may be, for example, MOCVD growth method or MBE growth method.
  • the material of the channel layer 30 may include, for example, one or more of GaN, AlGaN, indium aluminum nitride (InAlN), AlN, and scandium aluminum nitride (ScAlN).
  • the semiconductor device further includes an insertion layer 70 .
  • the insertion layer 70 is disposed on the channel layer 30 , for example, the insertion layer 70 is disposed on the surface of the channel layer 30 .
  • a method of forming the insertion layer 70 for example, an MOCVD growth method or an MBE growth method can be used.
  • Providing an insertion layer between the channel layer 30 and the barrier layer 40 can increase the concentration of 2DEG.
  • the barrier layer 40 is disposed on the channel layer 30 .
  • the barrier layer 40 is disposed on the surface of the channel layer 30 .
  • the barrier layer 40 is disposed on the surface of the insertion layer 70 .
  • the method of forming the barrier layer 40 may be, for example, MOCVD growth method or MBE growth method.
  • the material of the barrier layer 40 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.
  • the channel layer 30 and the barrier layer 40 constitute a heterojunction of the semiconductor device, and two-dimensional electron gas is generated above the channel layer 30 . Therefore, the materials of the channel layer 30 and the barrier layer 40 are different. Exemplarily, the material of the channel layer 30 includes GaN, and the material of the barrier layer 40 includes AlGaN.
  • the semiconductor device further includes a capping layer 80 .
  • the capping layer 80 is disposed on the barrier layer 40 , for example, the capping layer 80 is disposed on the surface of the barrier layer 40 .
  • the method of forming the capping layer 80 may be, for example, MOCVD growth method or MBE growth method combined with an etching process to form the capping layer.
  • the capping layer 80 has an opening for setting the source S and the drain D (positions where the source S and the drain D are set), and the opening exposes the barrier layer 40 .
  • the material of the capping layer 80 may be, for example, GaN or silicon nitride (Si 3 N 4 ).
  • the capping layer 80 By forming the capping layer 80 on the barrier layer 40, the barrier layer 40 can be protected, the surface of the barrier layer 40 can be prevented from being oxidized, and the surface state of the semiconductor device can be reduced. That is, the on-resistance of the semiconductor device is reduced, thereby reducing the gate leakage and power consumption of the semiconductor device, and improving the reliability of the semiconductor device.
  • a small amount of etching can be performed on the barrier layer 40 when the opening on the capping layer 80 is formed by etching. That is to say, finally, there will be recesses on the barrier layer 40 .
  • the source S and the drain D and the recesses on the barrier layer 40 can form a new ohmic contact surface, which is beneficial to the TiN (titanium nitride) formed on the surface of the source S and the drain D and the barrier layer 40 ) diffusion to form a second conductive channel, effectively reducing the ohmic contact resistance.
  • the maximum current of the drain D can be effectively increased, and the on-resistance of the semiconductor device can be reduced.
  • the source S and the drain D are disposed on the barrier layer 40 , located in the opening on the cap layer 80 , and form ohmic contact with the barrier layer 40 .
  • the source S and the drain D can be formed, for example, by photolithography and etching processes, and the source S and the drain D can be formed synchronously, for example.
  • the material of the source S and the drain D may be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer and a gold (Au) layer stacked in sequence, that is, Ti/Al/Ni/Au.
  • the material of the source S and the drain D may be Ti layer, Al layer, platinum (Pt) layer and Au layer stacked in sequence, that is, Ti/Al/Pt/Au.
  • the material of the source S and the drain D may be Ti layer, tantalum (Ta) layer and Ti layer stacked in sequence, that is, Ti/Ta/Ti.
  • the material of the source S and the drain D may be Au or palladium (Pd).
  • the first gate G1 and the second gate G2 are disposed on the barrier layer 40 between the source S and the drain D. Referring to FIG. 3 and FIG. 4 , the first gate G1 and the second gate G2 are disposed on the barrier layer 40 between the source S and the drain D.
  • the first gate G1 and the second gate G2 are disposed on the surface of the barrier layer 40 to form Schottky contacts with the barrier layer 40 .
  • the first gate G1 and the second gate G2 are disposed on the surface of the cap layer 80 to form Schottky contacts with the barrier layer 40 .
  • first gate G1 and the second gate G2 can be formed by, for example, photolithography and etching processes, and the first gate G1 and the second gate G2 can be formed synchronously, for example.
  • the material of the first gate G1 and the second gate G2 may be, for example, Au or Pd.
  • the first gate G1 is disposed close to the source S, and the second gate G2 is disposed close to the drain D. That is to say, the first gate G1 is disposed between the source S and the second gate G2.
  • the distance L1 between the first grid field plate GFP1 and the second grid G2 is between 0.5 ⁇ m-2.7 ⁇ m.
  • the distance L1 between the first gate field plate GFP1 and the second grid G2 is 0.7 ⁇ m, 1.0 ⁇ m, 1.3 ⁇ m, 1.5 ⁇ m, 1.7 ⁇ m, 2.0 ⁇ m, 2.3 ⁇ m or 2.5 ⁇ m.
  • the saturation current of the semiconductor device can be significantly increased, so as to increase the power of the semiconductor device. But at the same time, the knee point voltage of the semiconductor device will be increased, resulting in a decrease in the efficiency of the semiconductor device. Furthermore, the gate-to-drain parasitic capacitance Cgd of the semiconductor device is increased, resulting in a decrease in the gain characteristic of the semiconductor device. Therefore, by setting the distance L1 between the first gate field plate GFP1 and the second gate G2 within the range of 0.5 ⁇ m-2.7 ⁇ m, the performance and reliability requirements of the semiconductor device can be comprehensively met.
  • the first gate field plate GFP1 is at least partially located on the side of the first gate G1 close to the drain D, and the first gate field plate GFP1 is electrically connected to the first gate G1. , and there is a distance between the first gate field plate GFP1 and the barrier layer 40 .
  • the first gate field plate GFP1 only includes a portion on the side of the first gate G1 close to the drain D, and the first gate field plate GFP1 is in contact with the first gate G1 .
  • the first gate field plate GFP1 and the first gate G1 are integrally formed and formed synchronously in the same manufacturing process.
  • the first gate field plate GFP1 includes a first part GFP1-1 located on the side of the first gate G1 close to the drain D and a first part GFP1-1 located on the side of the first gate G1 close to the source S. Part II GFP1-2. Both the first part GFP1-1 and the second part GFP1-2 of the first gate field plate GFP1 are in contact with the first grid G1.
  • first part GFP1 - 1 and the second part GFP1 - 2 of the first grid field plate GFP1 and the first gate G1 are integrally formed and formed synchronously in the same manufacturing process.
  • the first The alignment boundary accuracy requirement of the grid field plate GFP1 may not be too high. Even if the alignment is inaccurate, the prepared first part GFP1-1 and the second part GFP1-2 are different in size, which has relatively little influence on the function of the first gate field plate GFP1. Moreover, if the alignment is not accurate, it will only affect the size of the first part GFP1-1 and the second part GFP1-2, and will not affect the width of the first grid G1, which can avoid the performance of the semiconductor device due to the size change of the first grid G1. coming impact.
  • the embodiment of the present application does not limit the shape of the first grid field plate GFP1 , and the shapes of the grid field plate shown in FIG. 3 , FIG. 4 and FIG. 5 are only illustrative.
  • the first source field plate SFP1 is disposed on the side of the first gate field plate GFP1 away from the substrate 20, and the first source field plate SFP1 and the source S electrode connect.
  • one or more layers of interlayer insulating layers can be provided between the first source field plate SFP1 and the first gate field plate GFP1, and the first source field plate SFP1 can communicate with the source through the via hole on the interlayer insulating layer. Pole S is electrically connected.
  • the side of the first source field plate SFP1 away from the first gate field plate GFP1 overlaps with the second gate G2.
  • the first source field plate SFP1 covers the first gate field plate GFP1. That is to say, along the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20 ), the first source field plate SFP1 overlaps the first gate field plate GFP1 .
  • the first source field plate SFP1 overlaps the first gate field plate GFP1 on a side close to the first gate field plate GFP1 .
  • the orthographic projection of the first source field plate SFP1 on the substrate 20 overlaps the orthographic projection of the first gate field plate GFP1 on the substrate 20 at a side close to the first gate field plate GFP1 .
  • the first source field plate SFP1 overlaps the first gate G1, but the first source field plate SFP1 does not cover the first gate G1. Alternatively, in some embodiments, the first source field plate SFP1 does not overlap with the first gate G1.
  • the side of the first source field plate SFP1 close to the first gate G1 does not extend above the first gate G1 .
  • the facing area of the first source field plate SFP1 and the first gate G1 can be reduced, thereby reducing the gate size of the semiconductor device.
  • the source parasitic capacitance Cgs is used to reduce the influence of the first source field plate SFP1 on the frequency characteristics of the semiconductor device.
  • the first source field plate SFP1 is in contact with the source S to realize electrical connection between the two. Wherein, the first source field plate SFP1 may bypass the first gate G1 and be in contact with the source S.
  • the material of the first source field plate SFP1 may be the same as that of the source S and the drain D, for example.
  • the first gate G1 and the second gate G2 are formed first, then the source S and the drain D are formed. Then, the first source field plate SFP1 may be formed synchronously with the source S and the drain D, for example.
  • structures such as an insulating layer or a flat layer may be provided on the side of the first source field plate SFP1 away from the substrate 20 , which is not limited in this embodiment of the present application.
  • the semiconductor device provided in this example includes a first gate G1 and a second gate G2.
  • the first gate G1 is used to receive the driving signal Vgate1 and the radio frequency signal RF
  • the second gate G2 is used to receive the fixed Voltage signal Vgate2.
  • FIG. 6A is an output curve of the single-gate semiconductor device shown in FIG. 2B
  • FIG. 6B is an output characteristic curve of the double-gate semiconductor device shown in FIG. 3 . Comparing FIG. 6A and FIG. 6B , it can be found that when the drain D voltage is low in FIG. 6B , the output voltage of the semiconductor device has reached a saturated state (the black dot in the figure indicates the knee point voltage).
  • the knee point voltage of the semiconductor device provided by this example is significantly lower than that of the semiconductor device shown in FIG. 2B .
  • the abscissa in FIG. 6A and FIG. 6B is the drain D voltage
  • the ordinate is the drain D current.
  • 6A and 6B are simulated under the condition that the fixed voltage signal Vgate2 received by the second gate G2 is a constant value (for example, 2V).
  • Vgate2 2V applied to the second grid G2, and the distance L1 between the first grid field plate GFP1 and the second grid G2 is 1.7 ⁇ m.
  • the second gate G2 can block the feedback path between the first gate G1 and the drain D, and the second gate G2 It can play a certain role in shielding to reduce when the semiconductor device is in the off state (for example, when bias is applied, the voltage of the first gate G1 is -6V, and the drain voltage is 50V to make the semiconductor device in the off state), the first gate
  • the gate-to-drain parasitic capacitance Cgd between G1 and drain D (the gate-to-drain parasitic capacitance Cgd can be reduced to 1/3 to 1/2 of that of the semiconductor device shown in Figure 2B) improves the small-signal gain of the semiconductor device (compared to that shown in Figure 2B
  • the small signal gain of the semiconductor device shown can be improved by about 5dB), the current gain cutoff frequency and the power gain cutoff frequency.
  • Example 2 The main difference between Example 2 and Example 1 is that the semiconductor device in Example 2 further includes a second gate field plate GFP2 on the basis of the structure of the semiconductor device in Example 1.
  • the semiconductor device mainly includes: a substrate 20, a channel layer 30 and a barrier layer 40 stacked on the substrate 20 in sequence, and a source layer arranged side by side on the barrier layer 40.
  • the second grid field plate GFP2 is at least partially located on the side of the second grid G2 close to the drain D, the second grid field plate GFP2 is electrically connected to the second grid G2, and the second grid field plate GFP2 and the barrier layer 40 with spacing.
  • the second gate field plate GFP2 only includes a portion on the side of the second gate G2 close to the drain D, and the second gate field plate GFP2 is in contact with the second gate G2.
  • the second gate field plate GFP2 and the second gate G2 are integrally formed and formed synchronously in the same manufacturing process.
  • the second gate field plate GFP2 includes a first part GFP2-1 located on the side of the second gate G2 close to the drain D and a first part GFP2-1 located on the side of the second gate G2 close to the source S. Part II GFP2-2. Both the first part GFP2-1 and the second part GFP2-2 of the second grid field plate GFP2 are in contact with the second grid G2.
  • the second part GFP2-1 and the second part GFP2-2 of the second gate field plate GFP2 and the second gate G2 are integrally formed, and are formed synchronously in the same manufacturing process.
  • the embodiment of the present application does not limit the shape of the second grid field plate GFP2, and the shape of the second grid field plate GFP2 shown in FIG. 7A is only a schematic representation.
  • the distance L2 between the first field plate GFP1 and the second field plate GFP2 ranges from 0.5 ⁇ m to 2.5 ⁇ m.
  • the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.7 ⁇ m, 1.0 ⁇ m, 1.3 ⁇ m, 1.5 ⁇ m, 1.7 ⁇ m, 2.0 ⁇ m or 2.3 ⁇ m.
  • the distance L2 between the first grid field plate GFP1 and the second grid field plate GFP2 is greater than the length of the part of the first source field plate SFP1 between the first grid field plate GFP1 and the second grid field plate GFP2 L3 is used as an example to illustrate.
  • the substrate 20 the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1 and the first source field plate
  • SFP1 the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1 and the first source field plate
  • the semiconductor device further includes a nucleation layer 50 , a graded buffer layer 60 , an insertion layer 70 and a capping layer 80 .
  • the structures of the nucleation layer 50 , the graded buffer layer 60 , the insertion layer 70 and the capping layer 80 are the same as those in the first example, and reference may be made to the relevant descriptions in the first example, and details will not be repeated here.
  • Example 3 The main difference between Example 3 and Example 2 is that the semiconductor device in Example 3 further includes a second source field plate SFP2 on the basis of the structure of the semiconductor device in Example 2.
  • the semiconductor device mainly includes: a substrate 20, a channel layer 30 and a barrier layer 40 stacked on the substrate 20 in sequence, and a source layer arranged side by side on the barrier layer 40.
  • the second source field plate SFP2 is disposed on the side of the second gate field plate GFP2 away from the substrate 20 , and is electrically connected to the source S.
  • one or more interlayer insulating layers may be provided between the second source field plate SFP2 and the second gate field plate GFP2 as required.
  • the second source field plate SFP2 is electrically connected to the source S.
  • the second source field plate SFP2 may be directly electrically connected to the source S, or the second source field plate SFP2 may be electrically connected to the first source field plate SFP1. In order to realize the electrical connection between the second source field plate SFP2 and the source S.
  • the second source field plate SFP2 covers the second gate field plate GFP2. That is to say, along the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20), the second source field plate SFP2 overlaps with the second gate field plate GFP2.
  • the second source field plate SFP2 overlaps the second gate field plate GFP2 on a side close to the second gate field plate GFP2 .
  • orthographic projection of the second source field plate SFP2 on the substrate 20 overlaps the orthographic projection of the second gate field plate GFP2 on the substrate 20 at the side close to the second gate field plate GFP2.
  • the second source field plate SFP2 overlaps the second gate G2, but the second source field plate SFP2 does not cover the second gate G2. Alternatively, in some embodiments, the second source field plate SFP2 does not overlap with the second gate G2.
  • the facing area of the second source field plate SFP2 and the second gate G2 can be reduced, thereby reducing the gate size of the semiconductor device.
  • the source parasitic capacitance Cgs is used to reduce the influence of the second source field plate SFP2 on the frequency characteristics of the semiconductor device.
  • the second source field plate SFP2 is in contact with the first source field plate SFP1, so as to realize the electrical connection between the second source field plate SFP2 and the first source field plate SFP1.
  • the second source field plate SFP2 may bypass the second gate G2, and be in contact with the first source field plate SFP1.
  • the material of the second source field plate SFP2 may be the same as that of the source S and the drain D, for example.
  • the second source field plate SFP2, for example, may be formed synchronously with the first source field plate SFP1.
  • the length of the second source field plate SFP2 (the dimension from the source S to the drain D direction) may be greater than or less than or equal to, for example, the length of the first source field plate SFP1 (the dimension from the source S to the drain D direction). ).
  • the embodiment of the present application does not limit the shape of the second source field plate SFP2, and the second source field plate SFP2 overlaps with the second gate G2 and extends to between the second gate G2 and the drain D.
  • the shape of the second source field plate SFP2 shown in FIG. 8 is only a schematic one.
  • the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1, the second gate field plate The structures of GFP2 and the first source field plate SFP1 are the same as those in Example 1, and reference may be made to related descriptions in Example 1, which will not be repeated here.
  • the first gate G1 and the second gate G2 have the same structure
  • the first gate field plate GFP1 and the second gate field plate GFP2 have the same structure
  • the first source field plate SFP1 and the second source field plate SFP2 has the same structure. In this way, the structure is simple and the preparation is convenient.
  • the distance L2 between the first field plate GFP1 and the second field plate GFP2 ranges from 0.5 ⁇ m to 1.5 ⁇ m.
  • the distance L2 between the first grid field plate GFP1 and the second grid field plate GFP2 is greater than or equal to that between the first source field plate SFP1 and the second grid field plate GFP1.
  • the second source field plate SFP2 can play a certain role of shielding and further expand the depletion region to reduce the gap between the first gate G1 and the drain D.
  • the gate-to-drain parasitic capacitance Cgd improves the small-signal gain of the semiconductor device (about 7 dB higher than that of the semiconductor device shown in FIG. 2B ), the cut-off frequency of the current gain, and the cut-off frequency of the power gain.
  • the second gate G2 is arranged between the first gate G1 and the drain D, with the second gate field plate GFP2 and the second source field plate corresponding to the second gate G2
  • the electric field strength between the first gate G1 and the drain D gradually decreases, and the breakdown voltage of the semiconductor device gradually increases.
  • the ordinate in FIG. 9 is the electric field intensity V/cm
  • the abscissa is the position in the semiconductor device.
  • the distance L2 between the first grid field plate GFP1 and the second grid field plate GFP2 is smaller than that between the first source field plate SFP1 and the second grid field plate GFP1.
  • the first source field plate SFP1 overlaps with the second gate field plate GFP2 .
  • the side of the first source field plate SFP1 close to the second gate G2 overlaps the second gate field plate GFP2 .
  • the semiconductor device including the first gate G1 and the second gate G2 shown in FIG. 3 can reduce the gate-to-drain parasitic capacitance Cgd of the semiconductor device. But it will also reduce the saturation current of the semiconductor device at the same time. By reducing the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2, the reduction of the saturation current can be alleviated.
  • the first source field plate SFP1 and the second source field plate SFP2 are not connected.
  • the first source field plate SFP1 and the second source field plate SFP2 can be realized on the basis of reducing the distance between the first gate field plate GFP1 and the second gate field plate GFP2. not connected.
  • the first source field plate SFP1 and the second source field plate SFP2 are connected.
  • the first source field plate SFP1 and the second source field plate SFP2 can be prepared by using the existing process without changing the preparation process of the first source field plate SFP1 .
  • Example 4 The difference between Example 4 and Examples 1 to 3 is that: on the basis of the semiconductor devices provided in Examples 1 to 3, the semiconductor device further includes a third gate G3.
  • the semiconductor device mainly includes: a substrate 20, a channel layer 30 and a barrier layer sequentially stacked on the substrate 20 Layer 40, the source S and the drain D arranged side by side on the barrier layer 40, the first gate G1 and the second gate G2 arranged on the barrier layer 40 and between the source S and the drain D And the third gate G3, the first gate field plate GFP1 and the second gate field plate GFP2, and the first source field plate SFP1 and the second source field plate SFP2.
  • the first gate G1 , the second gate G2 and the third gate G3 are disposed on the barrier layer 40 between the source S and the drain D. As shown in FIG. 11A , the first gate G1 , the second gate G2 and the third gate G3 are disposed on the barrier layer 40 between the source S and the drain D. As shown in FIG. 11A , the first gate G1 , the second gate G2 and the third gate G3 are disposed on the barrier layer 40 between the source S and the drain D. As shown in FIG. 11A , the first gate G1 , the second gate G2 and the third gate G3 are disposed on the barrier layer 40 between the source S and the drain D. As shown in FIG.
  • the first gate G1 , the second gate G2 and the third gate G3 are disposed on the surface of the barrier layer 40 to form Schottky contacts with the barrier layer 40 .
  • first gate G1, the second gate G2 and the third gate G3 can be formed by photolithography and etching process, for example, the first gate G1, the second gate G2 and the third gate G3 can be synchronously form.
  • a fourth gate or more gates may also be provided between the third gate G3 and the drain D, which is not limited in the embodiment of the present application, and can be reasonably set as required.
  • the principle of adding the second gate G2 in Example 1 is the same, by adding the third gate G3 between the second gate G2 and the drain D, the third gate G3 can play a certain shielding role to reduce the first
  • the gate-to-drain parasitic capacitance Cgd between the gate G1 and the drain D improves the small-signal gain, current gain cut-off frequency, and power gain cut-off frequency of the semiconductor device.
  • the semiconductor device further includes a third gate field plate GFP3.
  • the third gate field plate GFP3 is at least partly located on the side of the third gate G3 close to the drain D, the third gate field plate GFP3 is electrically connected to the third gate G3, and the third gate field plate GFP3 and the barrier layer 40 with spacing.
  • the third gate field plate GFP3 only includes a portion on the side of the third gate G3 close to the drain D, and the third gate field plate GFP3 is in contact with the third gate G3.
  • the third grid field plate GFP3 and the third grid G3 are integrally formed and formed synchronously in the same manufacturing process.
  • the third gate field plate GFP3 includes a first part GFP3-1 located on the side of the third gate G3 close to the drain D and a first part GFP3-1 located on the side of the third gate G3 close to the source S. Part II GFP3-2. Both the first part GFP3-1 and the second part GFP3-2 of the third grid field plate GFP3 are in contact with the third grid G3.
  • the second part GFP3-1 and the second part GFP3-2 of the third grid field plate GFP3 and the third grid G3 are integrally formed and formed synchronously in the same manufacturing process.
  • the embodiment of the present application does not limit the shape of the third grid field plate GFP3, and the shape of the third grid field plate GFP3 shown in FIG. 11B is only a schematic one.
  • the third gate field plate GFP3 By disposing the third gate field plate GFP3 in the semiconductor device, the electric field intensity in the vicinity of the third gate G3 can be greatly reduced. Therefore, the possibility of breakdown of the material of the barrier layer 40 can be reduced, the breakdown voltage of the semiconductor device can be further improved, and the performance of the semiconductor device can be guaranteed.
  • the third gate field plate GFP3 can play a certain shielding role, and further expand the depletion region to reduce the gate gap between the first gate G1 and the drain D.
  • the drain parasitic capacitance Cgd increases the small signal gain, current gain cutoff frequency and power gain cutoff frequency of the semiconductor device.
  • the semiconductor device further includes a third source field plate SFP3, the third source field plate SFP3 is disposed on the side of the third gate field plate GFP3 away from the substrate 20, and is electrically connected to the source S .
  • the third source field plate SFP3 covers the third gate field plate GFP3. That is to say, along the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20 ), the third source field plate SFP3 overlaps with the third gate field plate GFP3 .
  • the third source field plate SFP3 overlaps the third gate field plate GFP3 on a side close to the third gate field plate GFP3 .
  • the orthographic projection of the third source field plate SFP3 on the substrate 20 overlaps the orthographic projection of the third gate field plate GFP3 on the substrate 20 at the side close to the third gate field plate GFP3.
  • the second source field plate SFP2 and the distance between the second gate G2 and the third gate G3 may or may not be connected.
  • the connection between the second source field plate SFP2 and the third source field plate SFP3 is taken as an example for illustration.
  • the structures of the first grid G1, the second grid G2, and the third grid G3 are the same, and the structures of the first grid field plate GFP1, the second grid field plate GFP2, and the third grid field plate GFP3 are the same.
  • the structures of the first source field plate SFP1 , the second source field plate SFP2 and the third source field plate SFP3 are the same. In this way, the structure is simple and the preparation is convenient.
  • Vgate2 2V applied on the second gate G2
  • the distance L2 between the first field plate GFP1 and the second field plate GFP2 0.5 ⁇ m
  • the second field plate GFP2 and the third field plate GFP2 When the distance between the gate field plates GFP3 is 0.5 ⁇ m.
  • Example 5 The difference between Example 5 and Example 2 to Example 4 is that the first gate G1 is arranged closer to the drain D than the second gate G2 .
  • the semiconductor device mainly includes: a substrate 20, a channel layer 30 and a barrier layer stacked on the substrate 20 in sequence. layer 40, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1 and a second gate G2 arranged on the barrier layer 40 and between the source S and the drain D , and the first gate field plate GFP1 and the first source field plate SFP1.
  • the first gate G1 is disposed between the second gate G2 and the drain D. As shown in FIG. 12 , in the semiconductor device in this example, the first gate G1 is disposed between the second gate G2 and the drain D. As shown in FIG. 12 , in the semiconductor device in this example, the first gate G1 is disposed between the second gate G2 and the drain D. As shown in FIG. 12 , in the semiconductor device in this example, the first gate G1 is disposed between the second gate G2 and the drain D. As shown in FIG.
  • the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1, the second gate field plate The structures of GFP2 and the first source field plate SFP1 are the same as those in Example 2, and reference may be made to related descriptions in Example 2, and details will not be repeated here.
  • the semiconductor device provided in the embodiment of the present application can be applied not only to GaN HEMT devices, but also to other III-V semiconductor devices such as GaAs (gallium arsenide) HEMTs.

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Abstract

本申请实施例提供一种半导体器件及电子设备，涉及半导体技术领域，用于降低半导体器件的栅漏寄生电容。半导体器件包括：衬底；依次层叠设置于衬底上的沟道层和势垒层；设置于势垒层上的源极和漏极；设置于势垒层上的第一栅极和第二栅极，第一栅极和第二栅极位于源极和漏极之间，第二栅极设置于第一栅极与漏极之间；第一栅场板，至少部分设置于第一栅极靠近漏极一侧；第一源场板，第一源场板覆盖于第一栅场板。

Description

半导体器件及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及电子设备。
背景技术
随着半导体科技的发展，具有热导率高、电子漂移速率高、耐高温、化学性质稳定的半导体器件，被广泛应用于高频、高温、微波领域。
经研究发现，如何提高半导体器件的工作电压，从而有效提升半导体器件的微波功率特性，是目前半导体领域面临的重要挑战。
发明内容
本申请实施例提供一种半导体器件及电子设备，用于提升半导体器件的工作电压。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体器件，半导体器件例如可以是高电子迁移率晶体管器件。半导体器件包括：衬底；依次层叠设置于衬底上的沟道层和势垒层；设置于势垒层上的源极和漏极；设置于势垒层上的第一栅极和第二栅极，第一栅极和第二栅极位于源极和漏极之间，第二栅极设置于第一栅极与漏极之间；第一栅场板，至少部分设置于第一栅极靠近漏极一侧；第一源场板，第一源场板覆盖于第一栅场板。
本申请实施例中，通过在半导体器件中设置第一栅场板和第一源场板，可改变第一栅极与漏极之间的电场分布，降低第一栅极靠近漏极侧处的电场强度。从而可以降低势垒层的材料发生击穿的可能性，提高半导体器件的击穿电压，进而提升半导体器件的工作电压。在此基础上，通过在第一栅极与漏极之间设置第二栅极，第二栅极可以减少第一栅极和漏极之间的反馈路径，起到一定的屏蔽作用，可以降低第一栅极和漏极之间的栅漏寄生电容，从而降低栅漏寄生电容对半导体器件性能的影响，以实现既提高半导体器件的工作电压，又降低对半导体器件其他性能的影响。
在一种可能的实现方式中，半导体器件还包括第二栅场板；第二栅场板至少部分位于第二栅极靠近漏极一侧。通过在半导体器件中设置第二栅场板，可大幅降低第二栅极附近区域的电场强度。因此，可以降低势垒层的材料发生击穿的可能性，进一步提高半导体器件的击穿电压，保证半导体器件的性能。另外，通过在半导体器件中设置第二栅场板，第二栅场板可起到一定的屏蔽作用，进一步扩展耗尽区，以降低第一栅极和漏极之间的栅漏寄生电容。
在一种可能的实现方式中，半导体器件还包括第二源场板，第二源场板覆盖于第二栅场板。通过在半导体器件中设置第二源场板，第二源场板这个导电结构的存在，可以调整第二栅场板和漏极之间的电场分布，从而降低第二栅极靠近漏极侧处的电场强度，以降低半导体器件的峰值电场，进一步提高半导体器件的击穿电压。
在一种可能的实现方式中，第一源场板覆盖于第二栅场板。第一源场板可以与第 二栅极交叠，这样一来，即使减小了第一栅极和第二栅极之间的间距，也不会过分的增大第一源场板的工艺难度，易于实现。
在一种可能的实现方式中，第一源场板与第二源场板连接。通过将第一源场板和第二源场板连接，可以不用改变第一源场板的制备工艺，采用现有工艺制备第一源场板和第二源场板即可。
在一种可能的实现方式中，第一源场板与第二源场板之间具有间隙。第一源场板与第二源场板之间设置间隙，相比于将第一源场板与第二源场板连接，可提高半导体器件的小信号增益。
在一种可能的实现方式中，第一栅场板和第二栅极之间的间距为0.5μm-2.7μm。通过缩短第一栅场板和第二栅极之间的间距，可使得半导体器件的饱和电流明显提升，以提高半导体器件的功率。但是同时也会增大半导体器件的膝点电压，导致半导体器件的效率降低。而且会增大半导体器件的栅漏寄生电容，导致半导体器件的增益特性减低。因此，通过将第一栅场板和第二栅极之间的间距设置在0.5μm-2.7μm的区间范围内，可综合满足半导体器件的性能和可靠性要求。
在一种可能的实现方式中，第一栅场板包括设置于第一栅极靠近漏极一侧的第一部分和设置于第一栅极靠近源极一侧的第二部分，第一部分和第二部分分别与第一栅极接触连接。通过在第一栅极的两侧分别设置第一栅场板的第一部分和第二部分，在制备第一栅极和第一栅场板时，第一栅场板的对位边界精度要求可以无需太高。即使对位不准确，制备得到的第一部分和第二部分大小不同，对第一栅场板的功能影响也比较小。而且对位不准确，只会影响第一部分和第二部分的尺寸，不会影响第一栅极的宽度，可避免因第一栅极尺寸变化对半导体器件性能带来的影响。
在一种可能的实现方式中，半导体器件还包括第三栅极，第三栅极设置于第二栅极与漏极之间。通过进一步增加栅极的数量，可进一步减小栅漏寄生电容，提升半导体器件的小信号增益。
在一种可能的实现方式中，半导体器件还包括第三栅场板；第三栅场板至少部分设置于第三栅极靠近漏极一侧。通过进一步增加栅场板的数量，可以进一步提升半导体器件的击穿电压。
在一种可能的实现方式中，半导体器件还包括第三源场板；第三源场板覆盖于第三栅场板。通过进一步增加源场板的数量，可以进一步提升半导体器件的击穿电压。
本申请实施例的第二方面，提供一种半导体器件，半导体器件例如可以是高电子迁移率晶体管器件。半导体器件包括：衬底；依次层叠设置于衬底上的沟道层和势垒层；设置于势垒层上的源极和漏极；设置于势垒层上的第一栅极和第二栅极，第一栅极和第二栅极位于源极和漏极之间，第一栅极设置于第二栅极与漏极之间；第一栅场板，至少部分设置于第一栅极靠近漏极一侧；第一源场板，第一源场板覆盖于第一栅场板。
本申请实施例中，通过在半导体器件中设置第一栅场板和第一源场板，可改变第二栅极与漏极之间的电场分布，降低第二栅极靠近漏极侧处的电场强度。从而可以降低势垒层的材料发生击穿的可能性，提高半导体器件的击穿电压，进而提升半导体器件的工作电压。在此基础上，通过在第二栅极与漏极之间设置第一栅极，第一栅极可 以减少第二栅极和漏极之间的反馈路径，起到一定的屏蔽作用，可以降低第二栅极和漏极之间的栅漏寄生电容，从而降低栅漏寄生电容对半导体器件性能的影响，以实现既提高半导体器件的工作电压，又降低对半导体器件其他性能的影响。
本申请实施例的第三方面，提供一种电子设备，包括半导体器件及天线；半导体器件用于将射频信号放大后输出至天线向外辐射；其中，半导体器件为第一方面任一项或者第二方面的半导体器件。
本申请实施例第三方面提供的电子设备包括第一方面任一项或者第二方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
本申请实施例的第四方面，提供一种电子设备，包括半导体器件及与半导体器件电连接的印刷电路板；其中，所半导体器件为如第一方面任一项或者第二方面的半导体器件；半导体器件的衬底为导电型衬底。
本申请实施例第四方面提供的电子设备包括第一方面任一项或者第二方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
附图说明
为了更全面地理解本发明，现在参考下文结合附图和详细说明进行简要描述，但附图不一定按比例绘制。
图1A为本申请实施例提供的一种电子设备的结构示意图；
图1B为本申请实施例提供的一种有源天线单元的结构示意图；
图1C为本申请实施例提供的另一种电子设备的结构示意图；
图2A为本申请实施例提供的一种半导体器件的结构示意图；
图2B为本申请实施例提供的另一种半导体器件的结构示意图；
图3为本申请实施例提供的又一种半导体器件的结构示意图；
图4为本申请实施例提供的又一种半导体器件的结构示意图；
图5为本申请实施例提供的又一种半导体器件的结构示意图；
图6A为本申请实施例提供的一种图2B所示的半导体器件的输出曲线图；
图6B为本申请实施例提供的一种图5所示的半导体器件的输出曲线图；
图7A为本申请实施例提供的又一种半导体器件的结构示意图；
图7B为本申请实施例提供的又一种半导体器件的结构示意图；
图8为本申请实施例提供的又一种半导体器件的结构示意图；
图9为本申请实施例提供的一种半导体器件各位置处的电场分布图；
图10A为本申请实施例提供的又一种半导体器件的结构示意图；
图10B为本申请实施例提供的又一种半导体器件的结构示意图；
图11A为本申请实施例提供的又一种半导体器件的结构示意图；
图11B为本申请实施例提供的又一种半导体器件的结构示意图；
图11C为本申请实施例提供的又一种半导体器件的结构示意图；
图12为本申请实施例提供的又一种半导体器件的结构示意图。
附图标记：
1-基站；2-充电器；11-基带处理单元；12-有源天线单元；121-计算单元；122-第一传输单元；123-天线单元；124-电源；1210-控制单元；1211-第二传输单元；1212- 基带单元；1213-供电单元；1221-RF单元；1222-PA；20-衬底；30-沟道层；40-势垒层；50-成核层；60-渐变缓冲层；70-插入层；80-盖帽层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本申请实施例中，术语“二维电子气(two-dimensional electron gas，2DEG)”指的是：电子在垂直于界面方向的运动被势阱束缚而被量子化，而其平行于表面的运动仍然是自由的，这样的二维方向的自由电子被称为二维电子气。
在本申请实施例中，术语“半绝缘(semi-insulating，SI)”指的是：电阻率大于10 5Ω·cm。例如，半绝缘SiC衬底指的是SiC衬底的电阻率大于10 5Ω·cm。
在本申请实施例中，术语“电流崩塌效应”指的是：半导体器件的漏极电压超过一定值时，随着漏极电压的增加，电流开始下降，不能达到理想的值的效应。
本申请实施例中，术语“膝点电压”指的是：半导体器件从线性区进入饱和区时的拐点电压。
本申请实施例中，术语“耗尽区”指的是：在半导体pn结、肖特基结、异质结中，由于界面两侧半导体原有化学势的差异导致界面附近能带弯曲，从而形成能带弯曲区域电子或空穴浓度的下降的界面区域。
本申请实施例提供一种电子设备，该电子设备例如可以为充电器、充电家用小型电器、无人机、航空航天设备、激光雷达驱动器、激光器、探测器、雷达、5G(the 5th generation mobile network，第五代移动通信技术)通信设备等不同类型的用户设备或终端设备；该电子设备也可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
近三十年来，热导率高、电子漂移速率高、耐高温、化学性质稳定的半导体器件，被广泛用作射频器件或功率器件，应用于功率电子领域、微波射频领域、光电器件领域等。
例如，第三代半导体氮化镓(GaN)材料具有优异的特性，如较大的禁带宽度(3.4eV)、高的击穿电场(3.3MV/cm)、大的饱和速率(2.5e7cm/s)、以及极化效应带来的铝镓氮(AlGaN)/GaN异质结构界面处的2DEG密度高，使得GaN高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件可以工作在较高电压、较高温度和较高频率中，因而被广泛用于作为射频器件或功率器件。
在半导体器件用于作为射频器件的情况下，以电子设备为基站为例，对电子设备的结构进行说明。如图1A所示，基站1包括基带处理单元(base band unit，BBU)11和有源天线单元(active antenna unit，AAU)12。其中，BBU11主要负责基带数字信号处理，例如，FFT(fast fourier transform，快速傅立叶变换)/IFFT(inverse fast fourier transform，逆快速傅立叶变换)、调制/解调、信道编码/解码等。如图1B所示，AAU12包括计算单元121、第一传输单元122和天线单元123。其中，计算单元121包括控制单元1210、第二传输单元1211、基带单元1212和供电单元1213，控制单元1210、第二传输单元1211、基带单元1212和供电单元1213相互电连接，控制单元1210用于负责射频信号的控制，第二传输单元1211用于负责射频信号的传输，基带单元1212用于负责数字信号和模拟信号的转换，基带单元1212例如以是DAC(digital to analog converter，数字模拟转换器)，DAC可以将BBU 11输出的数字信号转换为模拟信号，供电单元1213与电源124电连接，用于为计算单元121中的控制单元1210、第二传输单元1211和基带单元1212供电。第一传输单元122用于负责射频信号的传输和放大。第一传输单元122包括RF(radio frequency，射频)单元1221和PA(power amplifier，功率放大器)1222，RF单元1221用于将模拟信号转化为小功率的射频信号，PA1222用于将小功率的射频信号进行功率放大后输出至天线单元123。天线单元123负责将射频信号向外辐射。如图1B所示，AAU12可以包括多个RF单元1221、多个PA1222以及多个天线单元123。需要说明的是，上述PA1222可以为半导体器件。
应当理解到，在半导体器件用于作为PA时，本申请实施例提供的电子设备不限于图1A和图1B所示的基站，任意需要使用功率放大器对信号进行放大的电子设备均属于本申请的实施例的应用场景。
在半导体器件用于作为功率器件的情况下，以电子设备为充电器为例，对电子设备的结构进行说明。如图1C所示，充电器2可以包括功率器件、电阻R、电感L、电容C等，功率器件例如可以为半导体器件。其中，半导体器件、电阻R、电感L和电容C可以通过印刷电路板(printed circuit board，PCB)实现互连。
应当理解到，在半导体器件用于作为功率器件时，本申请实施例提供的电子设备不限于图1C所示的充电器，任意需要使用功率器件的电子设备均属于本申请的实施例的应用场景。
提高半导体器件的工作电压可有效提升半导体器件微波功率特性，而提高半导体器件的击穿电压是提高半导体器件工作电压的前提。
在一些实施例中，如图2A所示，半导体器件包括衬底20、设置于衬底20上的沟道层30和势垒层40(作为半导体器件中的异质结构)、以及设置于势垒层40上的源极S、漏极D和栅极G，源极S和漏极D与势垒层40构成欧姆接触，栅极G与势垒层40构成肖特基接触。在此基础上，半导体器件还包括栅场板(gate field plate，GFP)，栅场板GFP，与势垒层40之间具有间距。
在半导体器件工作状态下，栅极G和漏极D之间会产生电场，电场集中处会位于栅极G靠近漏极D的尖角处，容易导致势垒层40的材料发生击穿(不可逆的物理性损坏)，而导致半导体器件失效。通过在栅极G上设置栅场板GFP，栅场板GFP相当于将栅极G向漏极D侧延伸，可改变栅极G与漏极D之间的电场分布，将电场的集中处引至栅场50板靠近漏极D的顶角处，而不再位于栅极G靠近漏极D的尖角处，相当于降低了栅极G靠近漏极D侧处的电场强度。虽然电场集中处位于栅场板GFP靠近漏极D一侧，但是由于栅场板GFP和势垒层40之间存在间距。因此，可以降低势垒层40的材料发生击穿的可能性，提高半导体器件的击穿电压，保证半导体器件的性能。
但是，栅极G与漏极D之间本身就存在栅漏寄生电容Cgd(或者称之为反馈电容)，设置栅场板GFP后，会进一步增大栅漏寄生电容Cgd，导致半导体器件小信号增益、电流增益截止频率以及功率增益截止频率下降。
基于此，在一些实施例中，如图2B所示，半导体器件还包括源场板(source field plate，SFP)，源场板SFP设置在栅场板GFP上方，与栅场板GFP交叠。
通过在半导体器件中设置源场板SFP，可以阻断栅极G和漏极D之间的反馈路径，从而降低半导体器件的栅漏寄生电容Cgd，提升半导体器件的小信号增益、电流增益截止频率以及功率增益截止频率。而且，源场板SFP这个导电结构的存在，可以调整栅场板GFP和漏极D之间的电场分布，从而降低栅极G靠近漏极D侧处的电场强度，以降低半导体器件的峰值电场，进一步提高半导体器件的击穿电压。电场强度降低后，可降低沟道中电子受强电场激发进入表面态的几率，从而抑制半导体器件的电流崩塌效应。
但是，源场板SFP的引入会增加半导体器件的栅源寄生电容Cgs，这将恶化半导体器件的频率特性。
在一些实施例中，为了提升半导体器件的增益特性，会向漏极D一侧延长源场板SFP。
但是这种做法一方面对小信号增益提升的幅度有限，另一方面会带来半导体器件的栅源寄生电容Cgs的显著增大，进而可能会降低半导体器件的漏极效率(drain efficieny)，导致半导体器件的频率特性恶化。
在一些实施例中，通过减小栅长(从源极S到漏极D方向上的尺寸)，来减小栅漏寄生电容Cgd，以进一步提升半导体器件的增益特性，如采用栅长为0.25um，或者栅长为0.1um的栅长工艺等。
然而，更短的栅长需要更高精度的光刻设备(如电子束光刻设备)，或更复杂的工艺(如线宽微缩工艺)。另外，更短的栅长也可能会带来短沟道效应，降低半导体器件的输出阻抗，并且在高漏压情况下可能会引起较差的关断特性。
因此，在半导体器件设计时，需要综合考虑半导体器件的击穿电压和增益等特性。如何在降低半导体器件击穿电压时，降低对半导体器件小信号增益、电流增益截止频率、功率增益等特性的影响，成为本领域技术人员需要解决的技术问题。
下面，以几个详细的示例对本申请实施例提供的半导体器件进行示意说明。
示例一
本示例提供一种半导体器件，如图3所示，半导体器件主要包括：衬底20、依次层叠设置于衬底20上的沟道层30和势垒层40、并排设置于势垒层40上的源极S和漏极D、设置于势垒层20上且位于源极S和漏极D之间的第一栅极G1和第二栅极G2、以及第一栅场板GFP1和第一源场板SFP1。
在一些实施例中，上述衬底20为金刚石衬底或碳化硅(SiC)衬底。
其中，在上述衬底20为SiC衬底的情况下，在原料纯度不高的情况下，生长得到的SiC衬底是导电型衬底。在原料纯度较高的情况下，生长得到的SiC衬底是半绝缘衬底。
在上述衬底20为金刚石衬底的情况下，正常生长形成的金刚石衬底为半绝缘衬底。在形成金刚石衬底的过程中，当杂质含量较高或者掺杂时，形成的金刚石衬底为导电型衬底。
其中，在衬底20为导电型衬底的情况下，半导体器件作为功率器件应用于电子设备中，与电子设备中的PCB实现互连。在衬底20为半绝缘衬底的情况下半导体器件作为射频器件应用于电子设备中，与电子设备中的天线实现信号互通。
金刚石衬底的热导率一般为1000W·m -1·K -1～2000W·m -1·K -1，SiC衬底的热导率一般为370W·m -1·K -1左右。当衬底20为金刚石衬底或SiC衬底时，衬底20的散热能力较高，从而可以提高半导体器件的散热能力。
在一些实施例中，如图4所示，半导体器件还包括成核层50。
成核层50设置于衬底20上，例如，成核层50设置于衬底20的表面上。
其中，形成成核层50的方法，例如可以通过金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。
成核层50的材料，例如可以包括GaN、AlGaN、氮化铝(AlN)中一种或多种。
成核层50的作用是将衬底20的晶格结构与沟道层30的晶格结构进行匹配，例如，可以先在衬底20上放置与衬底20的晶格结构差异较小的成核层50，然后再在成核层 50上制作与成核层50的晶格结构差异较小的沟道层30，其中成核层50可以采用超晶格结构。超晶格结构的一个重复单元是由两种不同的半导体材料层构成，当两种半导体材料层的厚度和周期长度小于电子平均自由程时，在该超晶格结构中可以产生量子尺寸效应。此时，夹在该超晶格结构两个半导体材料层之间的阱就是量子阱。利用量子阱产生的能量势阱对电子的束缚作用，使电子在平行于成核层50的界面的方向上运动，提升电子的横向迁移，从而避免或减少电子直接垂直进入与界面平行的衬底20的几率，从而降低衬底20的漏电。
在一些实施例中，如图4所示，半导体器件还包括渐变缓冲层60。
渐变缓冲层60设置于成核层50远离衬底20一侧，例如，渐变缓冲层60设置于成核层50远离衬底20的表面上。
其中，形成渐变缓冲层60的方法，例如可以采用MOCVD工艺外延生长Al(铝)组分逐渐降低的AlGaN渐变层。
示例的，通过MOCVD工艺，在成核层50远离衬底20一侧依次形成Al 0.8Ga 0.2N层、Al 0.5Ga 0.5N层、Al 0.2Ga 0.8N层，以形成渐变缓冲层60。
另外，可以理解的是，半导体器件用于作为射频器件时，上述渐变缓冲层60的成分，和，半导体器件用于作为功率器件时，上述渐变缓冲层60的成分可以不同。
渐变缓冲层60的作用是，渐变缓冲层60和沟道层30的禁带宽度不同，可以使得势垒层40与沟道层30形成的异质结的势阱深度更深，从而提高二维电子气(two-dimensional electron gas，2DEG)的浓度。另外，为了减少电子的散射带来的迁移率降低，渐变缓冲层60一般采用不掺杂的结构。
在一些实施例中，如图3和图4所示，沟道层30设置于衬底20上。
例如，如图3所示，沟道层30设置于衬底20的表面上。或者，如图4所示，沟道层30设置于渐变缓冲层60的表面上。
其中，形成沟道层30的方法，例如可以通过MOCVD生长法或MBE生长法等。
上述沟道层30的材料例如可以包括GaN、AlGaN、铟氮化铝(InAlN)、AlN、钪氮化铝(ScAlN)中一种或多种。
在一些实施例中，如图4所示，半导体器件还包括插入层70。
插入层70设置于沟道层30上，例如，插入层70设置于沟道层30的表面上。
其中，形成插入层70的方法，例如可以采用MOCVD生长法或MBE生长法等。
在沟道层30和势垒层40之间设置插入层，可以提高2DEG的浓度。
在一些实施例中，如图3和图4所示，势垒层40设置于沟道层30上。
示例的，如图3所示，势垒层40设置于沟道层30的表面上。或者，示例的，势垒层40设置于插入层70的表面上。
其中，形成势垒层40的方法，例如可以通过MOCVD生长法或MBE生长法等。
上述势垒层40的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。
可以理解的是，沟道层30和势垒层40构成半导体器件的异质结，沟道层30的上方产生二维电子气。因此，沟道层30和势垒层40的材料不相同。示例的，沟道层30的材料包括GaN，势垒层40的材料包括AlGaN。
在一些实施例中，如图4所示，半导体器件还包括盖帽层80。
盖帽层80设置于势垒层40上，例如，盖帽层80设置于势垒层40的表面上。
其中，形成盖帽层80的方法，例如可以通过MOCVD生长法或MBE生长法，结合刻蚀工艺形成盖帽层。
盖帽层80上具有用于设置源极S和漏极D的开口(设置源极S和漏极D的位置)，该开口露出势垒层40。
盖帽层80的材料，例如可以为GaN或者氮化硅(Si 3N 4)。
通过在势垒层40上形成盖帽层80，可对势垒层40起到保护作用，防止势垒层40表面被氧化，可降低半导体器件的表面态。即，降低半导体器件的导通电阻，从而降低半导体器件的栅极漏电和功耗，提高半导体器件的可靠性。
在一些实施例中，如图4所示，在刻蚀形成盖帽层80上的开口时，可以对势垒层40进行少量刻蚀。也就是说，最终势垒层40上会有凹陷部(recess)。
这样一来，源极S和漏极D和势垒层40上的凹陷部可以形成新的欧姆接触表面，有利于源极S和漏极D与势垒层40表面形成的TiN(氮化钛)的扩散，形成第二条导电通道，有效的降低欧姆接触电阻。另外，采用在势垒层40上形成凹陷部的结构，能有效的提高漏极D最大电流，降低半导体器件的导通电阻。
在一些实施例中，如图3和图4所示，源极S和漏极D设置于势垒层40上，位于盖帽层80上的开口内，与势垒层40形成欧姆接触。
其中，源极S、漏极D例如可以通过光刻和刻蚀工艺形成，源极S、漏极D例如可以同步形成。
源极S、漏极D的材料，例如可以为依次层叠的钛(Ti)层、Al层、镍(Ni)层和金(Au)层，即Ti/Al/Ni/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、Al层、铂(Pt)层和Au层，即Ti/Al/Pt/Au。或者源极S、漏极D的材料可以为依次层叠的Ti层、钽(Ta)层和Ti层，即Ti/Ta/Ti。或者源极S、漏极D的材料可以为Au或者钯(Pd)。
在一些实施例中，如图3和图4所示，第一栅极G1和第二栅极G2设置于势垒层40上，位于源极S和漏极D之间。
示例的，如图3所示，第一栅极G1和第二栅极G2设置于势垒层40的表面上，与势垒层40形成肖特基接触。或者，示例的，如图4所示，第一栅极G1和第二栅极G2设置于盖帽层80的表面上，与势垒层40形成肖特基接触。
其中，第一栅极G1和第二栅极G2例如可以通过光刻和刻蚀工艺形成，第一栅极G1和第二栅极G2例如可以同步形成。
第一栅极G1和第二栅极G2的材料，例如可以是Au或者Pd。
本示例中，如图3和图4所示，第一栅极G1靠近源极S设置，第二栅极G2靠近漏极D设置。也就是说，第一栅极G1设置于源极S与第二栅极G2之间。
在一些实施例中，第一栅场板GFP1和第二栅极G2之间的间距L1在0.5μm-2.7μm之间。
示例的，第一栅场板GFP1和第二栅极G2之间的间距L1为0.7μm、1.0μm、1.3μm、1.5μm、1.7μm、2.0μm、2.3μm或者2.5μm。
通过缩短第一栅场板GFP1和第二栅极G2之间的间距L1，可使得半导体器件的饱和电流明显提升，以提高半导体器件的功率。但是同时也会增大半导体器件的膝点电压，导致半导体器件的效率降低。而且会增大半导体器件的栅漏寄生电容Cgd，导致半导体器件的增益特性减低。因此，通过将第一栅场板GFP1和第二栅极G2之间的间距L1设置在0.5μm-2.7μm的区间范围内，可综合满足半导体器件的性能和可靠性要求。
在一些实施例中，如图3和图4所示，第一栅场板GFP1至少部分位于第一栅极G1靠近漏极D一侧，第一栅场板GFP1与第一栅极G1电连接，且第一栅场板GFP1与势垒层40之间具有间距。
示例的，如图3和图4所示，第一栅场板GFP1仅包括位于第一栅极G1靠近漏极D一侧的部分，第一栅场板GFP1和第一栅极G1接触连接。
例如，第一栅场板GFP1和第一栅极G1为一体成型结构，在同一次制备工艺中同步形成。
或者，示例的，如图5所示，第一栅场板GFP1包括位于第一栅极G1靠近漏极D一侧的第一部分GFP1-1和位于第一栅极G1靠近源极S一侧的第二部分GFP1-2。第一栅场板GFP1的第一部分GFP1-1和第二部分GFP1-2均与第一栅极G1接触连接。
例如，第一栅场板GFP1第一部分GFP1-1和第二部分GFP1-2和第一栅极G1为一体成型结构，在同一次制备工艺中同步形成。
通过在第一栅极G1的两侧分别设置第一栅场板GFP1的第一部分GFP1-1和第二部分GFP1-2，在制备第一栅极G1和第一栅场板GFP1时，第一栅场板GFP1的对位边界精度要求可以无需太高。即使对位不准确，制备得到的第一部分GFP1-1和第二部分GFP1-2大小不同，对第一栅场板GFP1的功能影响也比较小。而且对位不准确，只会影响第一部分GFP1-1和第二部分GFP1-2的尺寸，不会影响第一栅极G1的宽度，可避免因第一栅极G1尺寸变化对半导体器件性能带来的影响。
其中，本申请实施例对第一栅场板GFP1的形状不做限定，图3、图4以及图5中示意的栅场板的形状仅为一种示意。
在一些实施例中，如图3、图4以及图5所示，第一源场板SFP1设置于第一栅场板GFP1远离衬底20一侧，第一源场板SFP1与源极S电连接。
当然，根据需要，可以在第一源场板SFP1与第一栅场板GFP1之间设置一层或者多层层间绝缘层，第一源场板SFP1通过层间绝缘层上的过孔与源极S电连接。
根据第一栅极G1和第二栅极G2之间尺寸的不同，如图3所示，第一源场板SFP1远离第一栅场板GFP1一侧位于第一栅极G1和第二栅极G2之间。或者，第一源场板SFP1远离第一栅场板GFP1一侧与第二栅极G2交叠。
其中，第一源场板SFP1覆盖于第一栅场板GFP1。也就是说，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第一源场板SFP1与第一栅场板GFP1交叠。
示例的，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第一源场板SFP1靠近第一栅场板GFP1一侧与第一栅场板GFP1交叠。
或者理解为，第一源场板SFP1在衬底20上的正投影，在靠近第一栅场板GFP1 一侧处，与第一栅场板GFP1在衬底20上的正投影交叠。
在一些实施例中，第一源场板SFP1与第一栅极G1交叠，但第一源场板SFP1未覆盖第一栅极G1。或者，在一些实施例中，第一源场板SFP1与第一栅极G1未交叠。
或者理解为，第一源场板SFP1靠近第一栅极G1的一侧并未延伸至第一栅极G1上方。
通过只在第一栅场板GFP1靠近漏极D一侧处设置第一源场板SFP1，可减小第一源场板SFP1和第一栅极G1的正对面积，从而降低半导体器件的栅源寄生电容Cgs，以降低第一源场板SFP1对半导体器件频率特性的影响。
在一些实施例中，第一源场板SFP1与源极S接触连接以实现二者电连接。其中，第一源场板SFP1可以绕开第一栅极G1，与源极S接触连接。
第一源场板SFP1的材料，例如可以与源极S和漏极D的材料相同。在制备半导体器件时，若先形成第一栅极G1和第二栅极G2，再形成源极S和漏极D。那么，第一源场板SFP1例如可以与源极S和漏极D同步形成。
当然，根据需要，可以在第一源场板SFP1远离衬底20一侧设置绝缘层或者平坦层等结构，本申请实施例对此不做限定。
本示例提供的半导体器件包括第一栅极G1和第二栅极G2，在半导体器件工作时，第一栅极G1用于接收驱动信号Vgate1和射频信号RF，第二栅极G2用于接收固定电压信号Vgate2。基于此，图6A为图2B所示的单栅半导体器件的输出曲线图，图6B为图3所示的双栅半导体器件的输出特性曲线。对比图6A和图6B可以发现，图6B中在漏极D电压较低时，半导体器件的输出电压就已经达到饱和状态(图中的黑点表示膝点电压)。因此，本示例提供的半导体器件的膝点电压明显低于图2B所示的半导体器件的膝点电压。其中，图6A和图6B中的横坐标是漏极D电压，纵坐标是漏极D电流。图6A和图6B是在第二栅极G2接收的固定电压信号Vgate2为定值(例如2V)的情况下模拟的。不同曲线是第一栅极G1接收不同的驱动信号Vgate1时的曲线，在Vgate1＝-4.0V和Vgate1＝-6.0V的情况下，输出曲线与横坐标基本重合。
表1
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
如表1所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅极G2之间的间距L1在1.7μm时。经过模拟仿真发现，通过在半导体器件中设置第二栅极G2，可以改变沟道中载流子的分布，降低载流子浓度，从而降低半导体的电流，降低半导体器件的膝点电压，提高半导体器件的效率。其中，如图6B所示，Vgate1越小，半导体器件的膝点电压越低。而且，通过在第一栅极G1和漏极D之间设置第二栅极G2，第二栅极G2可以阻断第一栅极G1和漏极D之间的反馈路径，第二栅极G2可起到一定的屏蔽作用，以降低半导体器件处于关态时(例如施加偏置，第一栅极G1的电压为-6V，漏极电压为50V使半导体器件处于关态)，第一栅极G1和漏极D之间的栅漏寄生电容Cgd(栅漏寄生电容Cgd可下降至图2B所示的半导体器件的 1/3～1/2)，提升半导体器件小信号增益(比图2B所示的半导体器件小信号增益可提升约5dB)、电流增益截止频率以及功率增益截止频率。
示例二
示例二与示例一的主要不同之处在于：示例二中的半导体器件在示例一中的半导体器件结构的基础上，还包括第二栅场板GFP2。
如图7A所示，提供一种半导体器件，半导体器件主要包括：衬底20、依次层叠设置于衬底20上的沟道层30和势垒层40、并排设置于势垒层40上的源极S和漏极D、设置于势垒层40上且位于源极S和漏极D之间的第一栅极G1和第二栅极G2、第一栅场板GFP1和第二栅场板GFP2、以及第一源场板SFP1。
第二栅场板GFP2至少部分位于第二栅极G2靠近漏极D一侧，第二栅场板GFP2与第二栅极G2电连接，且第二栅场板GFP2与势垒层40之间具有间距。
示例的，第二栅场板GFP2仅包括位于第二栅极G2靠近漏极D一侧的部分，第二栅场板GFP2和第二栅极G2接触连接。
例如，第二栅场板GFP2和第二栅极G2为一体成型结构，在同一次制备工艺中同步形成。
或者，示例的，如图7A所示，第二栅场板GFP2包括位于第二栅极G2靠近漏极D一侧的第一部分GFP2-1和位于第二栅极G2靠近源极S一侧的第二部分GFP2-2。第二栅场板GFP2的第一部分GFP2-1和第二部分GFP2-2均与第二栅极G2接触连接。
例如，第二栅场板GFP2的第二部分GFP2-1和第二部分GFP2-2和第二栅极G2为一体成型结构，在同一次制备工艺中同步形成。
其中，本申请实施例对第二栅场板GFP2的形状不做限定，图7A中示意的第二栅场板GFP2的形状仅为一种示意。
在一些实施例中，如图7A所示，第一栅场板GFP1和第二栅场板GFP2之间的间距L2的取值范围在0.5μm-2.5μm之间。示例的，第一栅场板GFP1和第二栅场板GFP2之间的间距L2为0.7μm、1.0μm、1.3μm、1.5μm、1.7μm、2.0μm或者2.3μm。
本示例中以第一栅场板GFP1和第二栅场板GFP2之间的间距L2，大于第一源场板SFP1位于第一栅场板GFP1和第二栅场板GFP2之间的部分的长度L3为例进行示意。
本示例中，衬底20、沟道层30和势垒层40、源极S和漏极D、第一栅极G1和第二栅极G2、第一栅场板GFP1和第一源场板SFP1的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
在一些实施例中，如图7B所示，半导体器件还包括成核层50、渐变缓冲层60、插入层70以及盖帽层80。成核层50、渐变缓冲层60、插入层70以及盖帽层80的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
如表2所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝1.5μm时。经过模拟仿真发现，通过在半导体器件中设置第二栅场板GFP2，可大幅降低第二栅极G2附近区域的电场强度。因此，可以降低势垒层40的材料发生击穿的可能性，进一步提高半导体器件的击穿电压，保证半导体器件的 性能。另外，通过在半导体器件中设置第二栅场板GFP2，第二栅场板GFP2可起到一定的屏蔽作用，进一步扩展耗尽区，以降低第一栅极G1和漏极D之间的栅漏寄生电容Cgd，提升半导体器件小信号增益、电流增益截止频率以及功率增益截止频率。
表2
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
G1+G2+GFP2 图7A结构 0.86A 4.8V 30.5dB 0.007pF
示例三
示例三与示例二的主要不同之处在于：示例三中的半导体器件在示例二中的半导体器件结构的基础上，还包括第二源场板SFP2。
如图8所示，提供一种半导体器件，半导体器件主要包括：衬底20、依次层叠设置于衬底20上的沟道层30和势垒层40、并排设置于势垒层40上的源极S和漏极D、设置于势垒层40上且位于源极S和漏极D之间的第一栅极G1和第二栅极G2、第一栅场板GFP1和第二栅场板GFP2、以及第一源场板SFP1和第二源场板SFP2。
第二源场板SFP2设置于第二栅场板GFP2远离衬底20一侧，与源极S电连接。
当然，根据需要，可以在第二源场板SFP2与第二栅场板GFP2之间设置一层或者多层层间绝缘层。另外，第二源场板SFP2与源极S电连接，可以是第二源场板SFP2直接与源极S电连接，也可以是第二源场板SFP2与第一源场板SFP1电连接，以实现第二源场板SFP2与源极S电连接。
其中，第二源场板SFP2覆盖于第二栅场板GFP2。也就是说，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第二源场板SFP2与第二栅场板GFP2交叠。
示例的，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第二源场板SFP2靠近第二栅场板GFP2一侧与第二栅场板GFP2交叠。
或者理解为，第二源场板SFP2在衬底20上的正投影，在靠近第二栅场板GFP2一侧处，与第二栅场板GFP2在衬底20上的正投影交叠。
在一些实施例中，第二源场板SFP2与第二栅极G2交叠，但第二源场板SFP2未覆盖第二栅极G2。或者，在一些实施例中，第二源场板SFP2与第二栅极G2未交叠。
或者理解为，第二源场板SFP2靠近第二栅极G2的一侧并未延伸至第二栅极G2上方。
通过只在第二栅场板GFP2靠近漏极D一侧处设置第二源场板SFP2，可减小第二源场板SFP2和第二栅极G2的正对面积，从而降低半导体器件的栅源寄生电容Cgs，以降低第二源场板SFP2对半导体器件频率特性的影响。
在一些实施例中，第二源场板SFP2与第一源场板SFP1接触连接，以实现第二源场板SFP2和第一源场板SFP1电连接。其中，第二源场板SFP2可以绕开第二栅极G2， 与第一源场板SFP1接触连接。
第二源场板SFP2的材料，例如可以与源极S和漏极D的材料相同。第二源场板SFP2，例如可以和第一源场板SFP1同步形成。
第二源场板SFP2的长度(从源极S到漏极D方向上的尺寸)例如可以大于或者小于或者等于第一源场板SFP1的长度(从源极S到漏极D方向上的尺寸)。
其中，本申请实施例对第二源场板SFP2的形状不做限定，第二源场板SFP2与第二栅极G2交叠，并延伸至第二栅极G2和漏极D之间即可，图8中示意的第二源场板SFP2的形状仅为一种示意。
本示例中，衬底20、沟道层30和势垒层40、源极S和漏极D、第一栅极G1和第二栅极G2、第一栅场板GFP1、第二栅场板GFP2和第一源场板SFP1的结构与示例一中相同，可参考示例一中的相关描述，此处不再赘述。
在一些实施例中，第一栅极G1和第二栅极G2的结构相同，第一栅场板GFP1和第二栅场板GFP2的结构相同，第一源场板SFP1和第二源场板SFP2的结构相同。这样一来，结构简单，便于制备。
在一些实施例中，第一栅场板GFP1和第二栅场板GFP2之间的间距L2的取值范围在0.5μm-1.5μm之间。
示例的，如图8所示，第一栅场板GFP1和第二栅场板GFP2之间的间距L2，大于或者等于第一源场板SFP1位于第一栅场板GFP1和第二栅场板GFP2之间的部分的长度L3。也就是说，沿垂直于衬底20的方向，第一源场板SFP1与第二栅场板GFP2未交叠。
表3
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
G1+G2+GFP2 图7A结构 0.86A 4.8V 30.5dB 0.007pF
G1+G2+GFP2+SFP2 图8结构 0.86A 4.8V 32.3dB 0.005pF
如表3所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝1.5μm时。经过模拟仿真发现，通过在半导体器件中设置第二源场板SFP2，第二源场板SFP2这个导电结构的存在，可以调整第二栅场板GFP2和漏极D之间的电场分布，从而降低第二栅极G2靠近漏极D侧处的电场强度(比图2B所示的半导体器件电场强度可降低约55％)，以降低半导体器件的峰值电场，进一步提高半导体器件的击穿电压。而且，电场强度降低后，可降低沟道中电子受强电场激发进入表面态的几率，从而抑制半导体器件的电流崩塌效应。再者，通过在半导体器件中设置第二源场板SFP2，第二源场板SFP2可起到一定的屏蔽作用，进一步扩展耗尽区，以降低第一栅极G1和漏极D之间的栅漏寄生电容Cgd，提升半导体器件小信号增益(比图2B所示的半导体器件小信号增益可提升约7dB)、电流增益截止频率以及功率增益截止频率。
其中，如图9所示，在第一栅极G1和漏极D之间设置第二栅极G2后，随着与第二栅极G2对应的第二栅场板GFP2和第二源场板SFP2的增加，第一栅极G1和漏极D之间的电场强度逐渐降低，半导体器件的击穿电压逐渐升高。其中，图9中纵坐标为电场强度V/cm，横坐标为半导体器件中的位置。
或者，示例的，如图10A所示，第一栅场板GFP1和第二栅场板GFP2之间的间距L2，小于第一源场板SFP1位于第一栅场板GFP1和第二栅场板GFP2之间的部分的长度L3。也就是说，第一源场板SFP1覆盖于第二栅极板GFP2。或者理解为，沿垂直于衬底20的方向，第一源场板SFP1与第二栅场板GFP2交叠。
示例的，如图10A所示，沿垂直于衬底20的方向，第一源场板SFP1靠近第二栅极G2一侧与第二栅场板GFP2交叠。
通过表3可知，图3所示包括第一栅极G1和第二栅极G2的半导体器件，可以降低半导体器件的栅漏寄生电容Cgd。但是同时也会降低半导体器件的饱和电流。通过减小第一栅场板GFP1和第二栅场板GFP2之间的间距L2，可以缓解饱和电流的降低。
在一种实现方式中，如图10A所示，第一源场板SFP1和第二源场板SFP2未连接。
通过改变第一源场板SFP1的制备工艺，可实现在减小第一栅场板GFP1和第二栅场板GFP2之间间距的基础上，第一源场板SFP1和第二源场板SFP2未连接。
表4
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
G1+G2+GFP2 图7A结构 0.86A 4.8V 30.5dB 0.007pF
G1+G2+GFP2+SFP2 图8结构 0.86A 4.8V 32.3dB 0.005pF
G1+G2+GFP2+SFP2 图10A结构 0.97A 5.8V 31.4dB 0.007pF
如表4所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝0.5μm时。经过模拟仿真发现，图10A结构与图8结构相比，缩短第一栅场板GFP1和第二栅场板GFP2之间的间距，半导体器件的饱和电流明显提升，但是膝点电压和栅漏寄生电容Cgd也稍有变大，半导体器件的小信号增益也略有降低。因此，可以根据需要综合考虑半导体器件的小信号增益和膝点电压的要求，合理设置第一栅极G1和第二栅极G2之间的间距L2。
在另一种实现方式中，如图10B所示，第一源场板SFP1和第二源场板SFP2连接。
通过将第一源场板SFP1和第二源场板SFP2连接，可以不用改变第一源场板SFP1的制备工艺，采用现有工艺制备第一源场板SFP1和第二源场板SFP2即可。但是，如表5所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝0.5μm时。经过模拟仿真发现，图10A结构与图10B结构相比，第一源场板SFP1和第二源场板SFP2连接，半导体器件的小信号增益略有降低。
表5
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
G1+G2+GFP2 图7A结构 0.86A 4.8V 30.5dB 0.007pF
G1+G2+GFP2+SFP2 图8结构 0.86A 4.8V 32.3dB 0.005pF
G1+G2+GFP2+SFP2 图10A结构 0.97A 5.8V 31.4dB 0.007pF
G1+G2+GFP2+SFP2 图10B结构 0.97A 5.8V 31.2dB 0.007pF
示例四
示例四与示例一至示例三的不同之处在于：在示例一至示例三提供的半导体器件的基础上，半导体器件还包括第三栅极G3。
以与示例三提供的半导体器件进行对比为例，如图11A所示，提供一种半导体器件，半导体器件主要包括：衬底20、依次层叠设置于衬底20上的沟道层30和势垒层40、并排设置于势垒层40上的源极S和漏极D、设置于势垒层40上且位于源极S和漏极D之间的第一栅极G1、第二栅极G2以及第三栅极G3、第一栅场板GFP1和第二栅场板GFP2、以及第一源场板SFP1和第二源场板SFP2。
如图11A所示，第一栅极G1、第二栅极G2以及第三栅极G3设置于势垒层40上，位于源极S和漏极D之间。
示例的，如图11A所示，第一栅极G1、第二栅极G2以及第三栅极G3设置于势垒层40的表面上，与势垒层40形成肖特基接触。
其中，第一栅极G1、第二栅极G2以及第三栅极G3例如可以通过光刻和刻蚀工艺形成，第一栅极G1、第二栅极G2以及第三栅极G3例如可以同步形成。
当然，可以理解的是，还可以在第三栅极G3与漏极D之间设置第四栅极或者更多栅极，本申请实施例对此不做限定，根据需要合理设置即可。
与示例一中增加第二栅极G2原理相同，通过在第二栅极G2和漏极D之间增加第三栅极G3，第三栅极G3可起到一定的屏蔽作用，以降低第一栅极G1和漏极D之间的栅漏寄生电容Cgd，提升半导体器件小信号增益、电流增益截止频率以及功率增益截止频率。
在一些实施例中，如图11B所示，半导体器件还包括第三栅场板GFP3。
第三栅场板GFP3至少部分位于第三栅极G3靠近漏极D一侧，第三栅场板GFP3与第三栅极G3电连接，且第三栅场板GFP3与势垒层40之间具有间距。
示例的，第三栅场板GFP3仅包括位于第三栅极G3靠近漏极D一侧的部分，第三栅场板GFP3和第三栅极G3接触连接。
例如，第三栅场板GFP3和第三栅极G3为一体成型结构，在同一次制备工艺中同步形成。
或者，示例的，如图11B所示，第三栅场板GFP3包括位于第三栅极G3靠近漏极D一侧的第一部分GFP3-1和位于第三栅极G3靠近源极S一侧的第二部分GFP3-2。第三栅场板GFP3的第一部分GFP3-1和第二部分GFP3-2均与第三栅极G3接触连接。
例如，第三栅场板GFP3的第二部分GFP3-1和第二部分GFP3-2和第三栅极G3为一体成型结构，在同一次制备工艺中同步形成。
其中，本申请实施例对第三栅场板GFP3的形状不做限定，图11B中示意的第三栅场板GFP3的形状仅为一种示意。
通过在半导体器件中设置第三栅场板GFP3，可大幅降低第三栅极G3附近区域的电场强度。因此，可以降低势垒层40的材料发生击穿的可能性，进一步提高半导体器件的击穿电压，保证半导体器件的性能。另外，通过在半导体器件中设置第三栅场板GFP3，第三栅场板GFP3可起到一定的屏蔽作用，进一步扩展耗尽区，以降低第一栅极G1和漏极D之间的栅漏寄生电容Cgd，提升半导体器件小信号增益、电流增益截止频率以及功率增益截止频率。
在一些实施例中，如图11C所示，半导体器件还包括第三源场板SFP3，第三源场板SFP3设置于第三栅场板GFP3远离衬底20一侧，与源极S电连接。
其中，第三源场板SFP3覆盖于第三栅场板GFP3。也就是说，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第三源场板SFP3与第三栅场板GFP3交叠。
示例的，沿垂直于衬底20的方向(或者理解为衬底20的厚度方向)，第三源场板SFP3靠近第三栅场板GFP3一侧与第三栅场板GFP3交叠。
或者理解为，第三源场板SFP3在衬底20上的正投影，在靠近第三栅场板GFP3一侧处，与第三栅场板GFP3在衬底20上的正投影交叠。
其中，根据第二源场板SFP2结构以及第二栅极G2和第三栅极G3之间的距离的不同，第二源场板SFP2和第三源场板SFP3可以连接，也可以不连接。图11C中以第二源场板SFP2和第三源场板SFP3连接为例进行示意。
在一些实施例中，第一栅极G1、第二栅极G2以及第三栅极G3的结构相同，第一栅场板GFP1、第二栅场板GFP2以及第三栅场板GFP3的结构相同，第一源场板SFP1、第二源场板SFP2以及第三源场板SFP3的结构相同。这样一来，结构简单，便于制备。
如表6所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝0.5μm，第二栅场板GFP2和第三栅场板GFP3之间的间距为0.5μm时。经过模拟仿真发现，通过进一步增加栅极、栅场板、源场板的数量，可进一步减小栅漏寄生电容Cgd，提升半导体器件的小信号增益。
表6
描述 方案 饱和电流 膝点电压 小信号增益 Cgd
G1 图2B结构 1.09A 7.2V 24.9dB 0.023pF
G1+G2 图3结构 0.82A 4.0V 30.1dB 0.009pF
G1+G2+GFP2 图7A结构 0.86A 4.8V 30.5dB 0.007pF
表6续
Figure PCTCN2021134648-appb-000001
示例五
示例五与示例二至示例四的不同之处在于，第一栅极G1相对第二栅极G2靠近漏极D设置。
以与示例二提供的半导体器件进行对比为例，如图12所示，提供一种半导体器件，半导体器件主要包括：衬底20、依次层叠设置于衬底20上的沟道层30和势垒层40、并排设置于势垒层40上的源极S和漏极D、设置于势垒层40上且位于源极S和漏极D之间的第一栅极G1和第二栅极G2、以及第一栅场板GFP1和第一源场板SFP1。
需要强调的是，如图12所示，本示例中的半导体器件，第一栅极G1设置在第二栅极G2与漏极D之间。
本示例中，衬底20、沟道层30和势垒层40、源极S和漏极D、第一栅极G1和第二栅极G2、第一栅场板GFP1、第二栅场板GFP2以及第一源场板SFP1的结构与示例二中相同，可参考示例二中的相关描述，此处不再赘述。
表7
Figure PCTCN2021134648-appb-000002
如表7所示，在第二栅极G2上施加的Vgate2＝2V、第一栅场板GFP1和第二栅场板GFP2之间的间距L2＝0.5μm时。经过模拟仿真发现，通过在靠近漏极D的第一栅极G1上设置第一源场板SFP1，在远离漏极D的第二栅极G2上不设置第二源场板SFP2，半导体器件的饱和电流和小信号增益均比较大。而且，通过在靠近漏极D的第一栅极G1上设置第一源场板SFP1，在远离漏极D的第二栅极G2上不设置第二源场板SFP2。与图10B所示的半导体器件相比，半导体器件的饱和电流和小信号增益相同的前提下，半导体器件的结构简单，而且可以减小半导体器件的栅源寄生电容Cgs。
通过上述对本申请实施提供的半导体器件的描述可知，根据对半导体器件的实际要求，通过合理设计栅极数量、栅场板数量、源场板数量、源场板结构、栅场板之间的间距，可以有效平衡半导体器件的包括功率(和饱和电流相关)、小信号增益(和栅漏寄生电容Cgs相关)、以及效率(和膝点电压相关)等射频特性。
其中，本申请实施例提供的半导体器件，不仅可以应用于GaN HEMT器件，也可以应用于GaAs(砷化镓)HEMT等其他三五族半导体器件中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    沟道层和势垒层，依次层叠设置于所述衬底上；
    源极和漏极，设置于所述势垒层上；
    第一栅极和第二栅极，设置于所述势垒层上，位于所述源极和所述漏极之间；所述第二栅极设置于所述第一栅极与所述漏极之间；
    第一栅场板，至少部分设置于所述第一栅极靠近所述漏极一侧；
    第一源场板，所述第一源场板覆盖于所述第一栅场板。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件还包括第二栅场板；所述第二栅场板至少部分位于所述第二栅极靠近所述漏极一侧。
  3. 根据权利要求2所述的半导体器件，其特征在于，所述半导体器件还包括第二源场板，所述第二源场板覆盖于所述第二栅场板。
  4. 根据权利要求2或3所述的半导体器件，其特征在于，所述第一源场板覆盖于所述第二栅场板。
  5. 根据权利要求3或4所述的半导体器件，其特征在于，所述第一源场板与所述第二源场板连接。
  6. 根据权利要求1-5任一项所述的半导体器件，其特征在于，所述第一栅场板和所述第二栅极之间的间距为0.5μm-2.7μm。
  7. 根据权利要求1-6任一项所述的半导体器件，其特征在于，所述第一栅场板包括设置于第一栅极靠近漏极一侧的第一部分和设置于第一栅极靠近源极一侧的第二部分，所述第一部分和所述第二部分分别与所述第一栅极接触连接。
  8. 根据权利要求1-7任一项所述的半导体器件，其特征在于，所述半导体器件还包括第三栅极，所述第三栅极设置于所述第二栅极与所述漏极之间。
  9. 根据权利要求8所述的半导体器件，其特征在于，所述半导体器件还包括第三栅场板；
    所述第三栅场板至少部分设置于所述第三栅极靠近所述漏极一侧。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述半导体器件还包括第三源场板；所述第三源场板覆盖于所述第三栅场板。
  11. 一种电子设备，其特征在于，包括半导体器件及天线；所述半导体器件用于将射频信号放大后输出至所述天线向外辐射；
    其中，所述半导体器件为如权利要求1-10任一项所述的半导体器件。
  12. 一种电子设备，其特征在于，包括半导体器件及与所述半导体器件电连接的印刷电路板；
    其中，所半导体器件为如权利要求1-10任一项所述的半导体器件；所述半导体器件的衬底为导电型衬底。
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