WO2024103199A1

WO2024103199A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024103199A1
Application number: PCT/CN2022/131610
Authority: WO
Inventors: Sichao LI; Chunhua Zhou
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2024-05-23
Also published as: CN118235253A

Abstract

The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and extends along a first direction over the second nitride-based semiconductor layer. The doped III-V semiconductor layer comprises at least one modified portion extending from a first sidewall to a second sidewall of the doped III-V semiconductor layer, and the first and second sidewalls are opposite. The gate electrode is disposed over the doped III-V semiconductor layer and spans across the modified portion along a first direction.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Sichao LI; Chunhua ZHOU

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a modified doped nitride-based semiconductor layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and extends along a first direction over the second nitride-based semiconductor layer. The doped III-V semiconductor layer comprises at least one modified portion extending from a first sidewall to a second sidewall of the doped III-V semiconductor layer, and the first and second sidewalls are opposite. The gate electrode is disposed over the doped III-V semiconductor layer and spans across the modified portion along a first direction.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows: forming a first nitride-based semiconductor layer on a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a doped III-V semiconductor layer on the second nitride-based semiconductor layer; performing a treatment to modify at least one portion of the doped III-V semiconductor layer such that the portion of the doped III-V semiconductor layer has a character different than the rest of the doped III-V semiconductor layer and extends a first sidewall to a second sidewall of the doped III-V semiconductor layer, wherein the first and second sidewalls are opposite; and forming a gate electrode over the doped III-V semiconductor layer to span across the portion of the doped III-V semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and includes a plurality modified portions distributed to form a modified array over the second nitride-based semiconductor layer. The gate electrode is disposed over the doped III-V semiconductor layer and spanning across some of the modified portion.

By the configuration, the rest the doped III-V semiconductor layer (i.e., in addition to the modified portion) can serve as discontinuous depletion regions. Since each of the discontinuous depletion regions not only depletes a directly below area but also provides depletion laterally, the normally off character still can function. The modified portion are adjacent to the discontinuous depletion regions, which is advantageous to improve current density at on-state.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 1B is a top-view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 1C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 1D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 1E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 1F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 2A and FIG. 2B show different stages of a method for manufacturing the nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 3B is a top-view of a nitride-based semiconductor device without a gate electrode 32 according to some embodiments of the present disclosure;

FIG. 3C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 3D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 3E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 3F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 4A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 4B is a top-view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 4C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 4D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 4E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 4F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 5A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 5B is a top-view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 5C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 5D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 5E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 5F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 6A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 6B is a top-view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 6C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 6D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 6E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 6F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 6G is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line V-V’ according to some embodiments of the present disclosure;

FIG. 6H is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line VI-VI’ according to some embodiments of the present disclosure;

FIG. 7A is a top-view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 7B is a top-view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 7C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 7D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 7E is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 7F is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line IV-IV’ according to some embodiments of the present disclosure;

FIG. 7G is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line V-V’ according to some embodiments of the present disclosure; and

FIG. 7H is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line VI-VI’ according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a top-view of a nitride-based semiconductor device 1A with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 1B is a top-view of a nitride-based semiconductor device 1A without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 1B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 1A and FIG. 1B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 1A and the direction D2 is the vertical direction of FIG. 1A.

FIG. 1C is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 1D is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 1E is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 1F is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line IV-IV’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14,

electrodes

20 and 22, a doped III-V semiconductor layer 30, and a gate electrode 32.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the depletion mode device 1A may further include a buffer layer (not illustrated) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to or along the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

20 and 22 are disposed over the nitride-based semiconductor layer 14. The

electrodes

20 and 22 can extend along the direction D2 over the nitride-based semiconductor layer 14. Each of the

electrodes

20 and 22 can serve as a source electrode or a drain electrode. For example, the electrode 20 is a source electrode and the electrode 22 is the drain electrode. In some embodiments, the

electrodes

20 and 22 can be called ohmic electrodes.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20 and 22 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

In some embodiments, each of the

electrodes

20 and 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped III-V semiconductor layer 30 is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 can make contact with the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 can extend along the direction D2 over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 is located between the

electrodes

20 and 22.

The doped III-V semiconductor layer 30 includes at least one modified portion 302. The modified portions 302 can extend from one to another of sidewalls of the doped III-V semiconductor layer 30 which are opposite each other. More specifically, the modified portion 302 has a plurality of strips. As illustrated in FIG. 1A and FIG. 1B, the modified portion 302 includes horizontal strips extending along the direction D1 and vertical strips extending along the direction D2. As illustrated in FIG. 1A and FIG. 1B, the horizontal strips can extend from the left sidewall to the right sidewall of the doped III-V semiconductor layer 30; and the vertical strips can extend from the bottom sidewall to the top sidewall of the doped III-V semiconductor layer 30. As such, the modified portion 302 can have grid shape or be distributed to form a modified array.

In some embodiments, the modified portion 302 is formed by ion implantation. In some embodiments, after the formation of the doped III-V semiconductor layer 30, the doped type or concentration may be uniform, and then ion implantation can be performed on the doped III-V semiconductor layer 30. The ion implantation can act as anti-doping to those to be becoming the modified portion 302 so the modified portion 302 can have a different doped type or concentration than the rest of the doped III-V semiconductor layer 30. By controlling the conditions of the ion implantation, such as temperature, energy, angle, gas flow, or pressure, a doped region located at a top surface of the doped III-V semiconductor layer 30 is formed, which can serve as the modified portion 302.

In some embodiments, the modified portion 302 is formed by oxidation. In some embodiments, after the formation of the doped III-V semiconductor layer 30, the doped type or concentration may be uniform, and then oxidation can be performed on the doped III-V semiconductor layer 30. The oxidation can oxidize those to be becoming the modified portion 302 so the modified portion 302 can have at least one different character than the rest of the doped III-V semiconductor layer 30. By controlling the conditions of the oxidation, such as temperature, period, gas flow, or pressure, an oxide region located at a top surface of the doped III-V semiconductor layer 30 is formed, which can serve as the modified portion 302.

The rest the doped III-V semiconductor layer 30 (i.e., in addition to the modified portion 302) can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped p-type doped III-V semiconductor layer can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the modified portion 302 can be a p-type region which has a donor concentration less than the rest the doped III-V semiconductor layer 30.

The doped III-V semiconductor layer 30 including the modified portion 302 can bring the nitride-based semiconductor device 1A into an enhancement mode, which is called a normally off mode as well. In this regard, the rest the doped III-V semiconductor layer 30 (i.e., in addition to the modified portion 302) can serve as discontinuous depletion regions. Since each of the discontinuous depletion regions not only depletes a directly below area but also provides depletion laterally, the normally off character still can function. The modified portion 302 are adjacent to the discontinuous depletion regions, which is advantageous to improve current density at on-state. On the contrary, a continuous depletion region (i.e., an entirety of the p-type doped nitride-based semiconductor layer is continuous) will have lower current density at on-state. By the configuration of the present embodiment, the 2DEG concentration beneath the modified portion 302 can be improved, which results in the higher current density for the nitride-based semiconductor device 1A at on-state.

Furthermore, by the configuration of the modified portion 302, the device threshold voltage is adjustable. For example, the area ratio of the modified portion 302 to the entirety of the doped III-V semiconductor layer 30 can be adjusted to tune the device threshold voltage.

In order to maintain the normally off character with the higher current density improved, the dimension of the modified portion 302 can be designed further. For example, a spacing between the vertical strips is narrower than a spacing between the horizontal strips.

The gate electrode 32 is disposed over the doped III-V semiconductor layer 30. The gate electrode 32 can extend along the direction D2 over the doped III-V semiconductor layer 30. The gate electrode 32 can span across the modified portion 302 along the direction D2. Some of the modified portion 302 can get free from coverage of the gate electrode 32. The gate electrode 32 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. The

electrodes

20, 22, and the gate electrode 32 can constitute an enhancement mode HEMT with the doped III-V semiconductor layer 30.

Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A and FIG. 2B as described below. FIG. 2A and FIG. 2B are top views of the stages. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, nitride-based semiconductor layers (i.e., a channel layer and a barrier layer) are formed. A doped III-V semiconductor layer 30 is formed on the nitride-based semiconductor layer 14. The formation of the doped III-V semiconductor layer 30 may include a pattering process.

Referring to FIG. 2B, a treatment is performed to modify some portions of the doped III-V semiconductor layer 30 such that the portions of the doped III-V semiconductor layer 30 have a character different than the rest of the doped III-V semiconductor layer 30. Those treated portions of the doped III-V semiconductor layer 30 can become modified portion 302. In some embodiments, during the treatment, a mask layer is applied to the process. In some embodiments, the treatment includes ion implantation or oxidation. After the formation of the modified portion 302, a gate electrode as afore described can be formed over the doped III-V semiconductor layer 30 and the gate electrode span across the modified portion 302 of the doped III-V semiconductor layer 30.

FIG. 3A is a top-view of a nitride-based semiconductor device 1B with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 3B is a top-view of a nitride-based semiconductor device 1B without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 3B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 3A and FIG. 3B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 3A and the direction D2 is the vertical direction of FIG. 3A.

FIG. 3C is a vertical cross-sectional view of a nitride-based semiconductor device 1B taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 3D is a vertical cross-sectional view of a nitride-based semiconductor device 1B taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 3E is a vertical cross-sectional view of a nitride-based semiconductor device 1B taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 3F is a vertical cross-sectional view of a nitride- based semiconductor device 1B taken along a line IV-IV’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1F, except that the doped III-V semiconductor layer 30 is replaced by a doped III-V semiconductor layer 30B.

The doped III-V semiconductor layer 30B is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30B includes a modified portion 302B. In some embodiments, the modified portion 302B can be formed by a doped region embedded beneath a top surface of the doped III-V semiconductor layer 30B. In some embodiments, the modified portion 302B can be formed by an oxide region embedded beneath a top surface of the doped III-V semiconductor layer 30B. More specifically, the modified portion 302B is embedded between a bottom surface and a top surface of the doped III-V semiconductor layer 30B. As considered of complexity of the process, the top surface of the doped III-V semiconductor layer 30B is closer to the modified portion 302B than the bottom surface of the doped III-V semiconductor layer 30B. To obtain the structure of the nitride-based semiconductor device 1B, the ion implantation can be performed with the stronger energy. For the oxide region, oxygen atoms may be applied to the ion implantation. Such the configuration depends on delicate ion implantation control, which may result in high cost. However, since the modified portion 302 can get closer to the 2DEG region, the current density can get controlled well.

FIG. 4A is a top-view of a nitride-based semiconductor device 1C with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 4B is a top-view of a nitride-based semiconductor device 1C without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 4B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 4A and FIG. 4B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 4A and the direction D2 is the vertical direction of FIG. 4A.

FIG. 4C is a vertical cross-sectional view of a nitride-based semiconductor device 1C taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 4D is a vertical cross-sectional view of a nitride-based semiconductor device 1C taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 4E is a vertical cross-sectional view of a nitride-based semiconductor device 1C taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 4F is a vertical cross-sectional view of a nitride-based semiconductor device 1C taken along a line IV-IV’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1F, except that the doped III-V semiconductor layer 30 is replaced by a doped III-V semiconductor layer 30C.

The doped III-V semiconductor layer 30C is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30C includes a modified portion 302C. The modified portion 302C is located at a top surface of the doped III-V semiconductor layer 30C. The modified portion 302C has periodic patterns. The modified portion 302C is formed to have round shape. The round shape of the modified portion 302C can be distributed to form a modified array. The 2DEG concentration beneath the modified portion 302C of the modified array can be improved, which results in the higher average current density for the nitride-based semiconductor device 1C at on-state. The round shape can be applied to the situation that the current density is required as uniform distribution.

FIG. 5A is a top-view of a nitride-based semiconductor device 1D with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 5B is a top-view of a nitride-based semiconductor device 1D without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 5B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 5A and FIG. 5B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 5A and the direction D2 is the vertical direction of FIG. 5A.

FIG. 5C is a vertical cross-sectional view of a nitride-based semiconductor device 1D taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 5D is a vertical cross-sectional view of a nitride-based semiconductor device 1D taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 5E is a vertical cross-sectional view of a nitride-based semiconductor device 1D taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 5F is a vertical cross-sectional view of a nitride-based semiconductor device 1D taken along a line IV-IV’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1F, except that the doped III-V semiconductor layer 30 is replaced by a doped III-V semiconductor layer 30D.

The doped III-V semiconductor layer 30D is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30D includes a modified portion 302D. The modified portion 302D is embedded between a bottom surface and a top surface of the doped III-V semiconductor layer 30D. The modified portion 302D has periodic patterns. The modified portion 302C is formed to have round shape. The round shape of the modified portion 302C can be distributed to form a modified array. The 2DEG concentration beneath the modified portion 302C of the modified array can be improved, which results in the higher average current density for the nitride-based semiconductor device 1C at on-state. The round shape can be applied to the situation that the current density is required as uniform distribution.

FIG. 6A is a top-view of a nitride-based semiconductor device 1E with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 6B is a top-view of a nitride-based semiconductor device 1E without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 6B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 6A and FIG. 6B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 6A and the direction D2 is the vertical direction of FIG. 6A.

FIG. 6C is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 6D is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 6E is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 6F is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line IV-IV’ according to some embodiments of the present disclosure. FIG. 6G is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line V-V’ according to some embodiments of the present disclosure. FIG. 6H is a vertical cross-sectional view of a nitride-based semiconductor device 1E taken along a line VI-VI’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1F, except that the doped III-V semiconductor layer 30 is replaced by a doped III-V semiconductor layer 30E.

The doped III-V semiconductor layer 30E is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30E includes a modified portion 302E. The modified portion 302E is located at a top surface of the doped III-V semiconductor layer 30E. The modified portion 302E has periodic patterns. The modified portion 302E is formed to have rectangular shape. The rectangular shape of the modified portion 302E can be distributed to form a modified array. The 2DEG concentration beneath the modified portion 302E of the modified array can be improved. The doped III-V semiconductor layer 30E including modified portion 302E can provide strongly modulation to the current density at on-state due to the modified portion 302E extending to edges of the doped III-V semiconductor layer 30E. The round shape can be applied to the situation that the high voltage device is applied.

FIG. 7A is a top-view of a nitride-based semiconductor device 1F with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 7B is a top-view of a nitride-based semiconductor device 1F without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 7B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in FIG. 7A and FIG. 7B. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 7A and the direction D2 is the vertical direction of FIG. 7A.

FIG. 7C is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 7D is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 7E is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line III-III’ according to some embodiments of the present disclosure. FIG. 7F is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line IV-IV’ according to some embodiments of the present disclosure. FIG. 7G is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line V-V’ according to some embodiments of the present disclosure. FIG. 7H is a vertical cross-sectional view of a nitride-based semiconductor device 1F taken along a line VI-VI’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1F, except that the doped III-V semiconductor layer 30 is replaced by a doped III-V semiconductor layer 30F.

The doped III-V semiconductor layer 30F is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30F includes a modified portion 302F. The modified portion 302F is embedded between a bottom surface and a top surface of the doped III-V semiconductor layer 30F. The modified portion 302F has periodic patterns. The modified portion 302F is formed to have rectangular shape. The rectangular shape of the modified portion 302F can be distributed to form a modified array. The 2DEG concentration beneath the modified portion 302F of the modified array can be improved. The doped III-V semiconductor layer 30E including modified portion 302F can provide strongly modulation to the current density at on-state due to the modified portion 302F extending to edges of the doped III-V semiconductor layer 30F. The round shape can be applied to the situation that the high voltage device is applied.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped III-V semiconductor layer disposed over the second nitride-based semiconductor layer and extending along a first direction over the second nitride-based semiconductor layer, wherein the doped III-V semiconductor layer comprises at least one modified portion extending from a first sidewall to a second sidewall of the doped III-V semiconductor layer, and the first and second sidewalls are opposite; and

a gate electrode disposed over the doped III-V semiconductor layer and spanning across the modified portion along a first direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion comprises a doped region located at a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion comprises a doped region embedded beneath a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion comprises an oxide region located at a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion comprises an oxide region embedded beneath a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion has grid shape.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion has rectangular shape.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion is free from coverage of the gate electrode.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion has a plurality of first strips extending along the first direction and a plurality of second strips extending along a second direction different than the first direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second strips extend from the first sidewall to the second sidewall.
The nitride-based semiconductor device of any one of the preceding claims, wherein a spacing between the first strips is narrower than a spacing between the second strips.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion has periodic patterns.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified portion is embedded between a bottom surface and a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the top surface is closer to the modified portion than the bottom surface.
The nitride-based semiconductor device of any one of the preceding claims, further comprising:

a source electrode and a drain electrode disposed over the doped III-V semiconductor layer and extending along the first direction over the doped III-V semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode.
A method for manufacturing a semiconductor device, comprising:

forming a first nitride-based semiconductor layer on a substrate;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a doped III-V semiconductor layer on the second nitride-based semiconductor layer;

performing a treatment to modify at least one portion of the doped III-V semiconductor layer such that the portion of the doped III-V semiconductor layer has a character different than the rest of the doped III-V semiconductor layer and extends a first sidewall to a second sidewall of the doped III-V semiconductor layer, wherein the first and second sidewalls are opposite; and

forming a gate electrode over the doped III-V semiconductor layer to span across the portion of the doped III-V semiconductor layer.
The method of any one of the preceding claims6, wherein the treatment comprises ion implantation such that the portion of the doped III-V semiconductor layer becomes a doped region located at a top surface of the doped III-V semiconductor layer.
The method of any one of the preceding claims, wherein the treatment comprises ion implantation such that the portion of the doped III-V semiconductor layer becomes a doped region embedded beneath a top surface of the doped III-V semiconductor layer.
The method of any one of the preceding claims, wherein the treatment comprises an oxidizing process such that the portion of the doped III-V semiconductor layer becomes an oxide region located at a top surface of the doped III-V semiconductor layer.
The method of any one of the preceding claims, wherein the treatment comprises an oxidizing process such that the portion of the doped III-V semiconductor layer becomes an oxide region embedded beneath a top surface of the doped III-V semiconductor layer.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped III-V semiconductor layer disposed over the second nitride-based semiconductor layer and comprising a plurality modified portions distributed to form a modified array over the second nitride-based semiconductor layer; and

a gate electrode disposed over the doped III-V semiconductor layer and spanning across some of the modified portion.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified array forms a doped region located at a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified array forms a doped region embedded beneath a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified array forms an oxide region located at a top surface of the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the modified array forms an oxide region embedded beneath a top surface of the doped III-V semiconductor layer.