WO2024026816A1

WO2024026816A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024026816A1
Application number: PCT/CN2022/110467
Authority: WO
Inventors: Yi-Lun Chou; King Yuen Wong
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2024-02-08

Abstract

A nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a group III oxide layer, and a gate electrode. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer. The group III oxide layer is attached to the second III-V nitride-based semiconductor layer and laterally overlaps with the second III-V nitride-based semiconductor layer. The gate electrode is disposed over the second III-V nitride-based semiconductor layer and in contact with the group III oxide layer and the second III-V nitride-based semiconductor layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Yi-Lun CHOU, King Yuen WONG

Field of the Invention:

The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a high electron mobility transistor (HEMT) nitride-based semiconductor device having a gate opening formed through ultra-high etch selectivity ratio.

Background of the Invention:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent for semiconductor devices, such as high power switching and high frequency applications. The HEMT utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) . At present, there is a need to improve the yield rate for HEMT devices, thereby making them suitable for mass production.

Summary of the Invention:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a group III oxide layer, and a gate electrode. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer. The group III oxide layer is attached to the second III-V nitride-based semiconductor layer and laterally overlaps with the second III-V nitride-based semiconductor layer. The gate electrode is disposed over the second III-V nitride-based semiconductor layer and in contact with the group III oxide layer and the second III-V nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows. A first III-V nitride-based semiconductor layer is formed over a substrate. A second III-V nitride-based semiconductor layer is formed over the first III-V nitride-based semiconductor layer. A mask layer with an opening is formed over the second III-V nitride-based semiconductor layer, in which at least one portion of the second III-V nitride-based semiconductor layer is exposed from the opening. The portion of the second III-V nitride-based semiconductor layer is oxidized. The oxidized portion of the second III-V nitride-based semiconductor layer is etched such that the second III-V nitride-based semiconductor layer has an inner sidewall. The gate electrode is formed in contact with the inner sidewall of the second III-V nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a group III oxide layer, and gate electrode. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer. The group III oxide layer has opposite sidewalls which connect to the second III-V nitride-based semiconductor layer. The gate electrode is disposed over the second III-V nitride-based semiconductor layer and in contact with the group III oxide layer and is spaced apart from the first III-V nitride-based semiconductor layer by the group III oxide layer.

By applying the above configuration, high etch selectivity ratio with respect to channel layer can be achieved during formation of gate recess. As such, an enhancement mode HEMT device can be manufactured with high quality channel layer.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

In the following description, semiconductor devices, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A includes a substrate 10, a nucleation layer 12, a buffer layer 14, nitride-based

semiconductor layers

16 and 18, a gate electrode 20,

electrodes

30 and 32.

The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example but are not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example, but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxy (epi) layer, or combinations thereof.

The nucleation layer 12 is formed on the substrate 10. The nucleation layer 12 may form an interface with the substrate 10. The nucleation layer 12 is configured to provide a top surface for growth of III-nitride material thereon. In other words, the nucleation layer 12 forms an appropriate template to transition from lattice of the substrate to a template more suitable for growth of III-nitride material. The nucleation layer 12 can provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer to be formed on the top surface thereof (e.g., epitaxially formation) . The mismatch/difference may refer to different lattice constants or thermal expansion coefficients. The exemplary material of the nucleation layer 12 can include, for example but is not limited to AlN or any of its alloys.

The buffer layer 14 is formed on the nucleation layer 12. The buffer layer 14 may form an interface with the nucleation layer 12. The buffer layer 14 is configured to reduce lattice and thermal mismatches between the underlying layer and a layer to be formed on the buffer layer 14 (e.g., epitaxially formed thereon) , thereby curing defects due to the mismatches/difference. The buffer layer 14 includes a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitride, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 14 can further include, for example but are not limited to, AlN, AlGaN, InAlGaN, or combinations thereof.

The nitride-based semiconductor layer 16 is disposed over the buffer layer 14. The nitride-based semiconductor layer 16 can be a III-V nitride-based semiconductor layer. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InAlN, In _xAl _yGa _(1–x– _y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The nitride-based semiconductor layer 18 is disposed on the nitride-based semiconductor layer 16. The nitride-based semiconductor layer 18 can be a III-V nitride-based semiconductor layer. The exemplary materials of the nitride-based semiconductor layer 18 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InAlN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 16 and 18 are selected such that the nitride-based semiconductor layer 18 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 16, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. As such, the nitride-based semiconductor layers 16 and 18 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A can include at least one GaN-based high-electron-mobility transistor (HEMT) .

The nitride-based semiconductor layer 18 has a gate opening 182. The gate opening 182 can be formed by removing a portion of the nitride-based semiconductor layer 18. In some embodiments, the removing may be performed by using an etching process. In order to make the etching process smoothly remove object, high etch selectivity ratio serve an important factor. In some embodiments, the nitride-based semiconductor layer 18 includes InAlN. In some embodiments, aluminum concentration of InAlN in the nitride-based semiconductor layer 18 is greater than 80%, which is advantageous to etch.

Prior to the etching process, a portion of the nitride-based semiconductor layer 18 can get oxidized so as to become InAlO. InAlO can have high etch selectivity ratio with respect to GaN, so GaN can free from damage (e.g., over etching) during the etching process.

The gate electrode 20 is disposed over the nitride-based semiconductor layers 16 and 18. The gate electrode 20 makes contact with the nitride-based semiconductor layer 16 via the gate opening 182. The gate electrode 20 covers the nitride-based semiconductor layer 18 and makes contact with the nitride-based semiconductor layer 18. Such the configuration can be called gate recess as well. With the gate recess, the semiconductor device 1A can be designed as being an enhancement mode device.

In some embodiments, the gate electrode 20 may include metals or metal compounds. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrode 20 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

The

electrodes

30 and 32 are disposed on the nitride-based semiconductor layer 18. The

electrodes

30 and 32 can serve a combination of a source and a drain. The

electrodes

30 and 32 are located at two opposite sides of the gate electrode 20 (i.e., the gate electrode 20 is located between the electrodes 30 and 32) . The gate electrode 20 and the

electrodes

30 and 32 can collectively act as an enhancement GaN-based HEMT with the 2DEG region.

Although it is not shown in FIG. 1, the

electrodes

30 and 32 may be optionally asymmetrical about the gate electrode 20. In some embodiments, the gate electrode 20 is closer to the left electrode 30 than the right electrode 32. The present disclosure is not limited thereto, and the configuration of the

electrodes

30 and 32 is adjustable.

In some embodiments, each of the

electrodes

30 and 32 includes one or more conformal conductive layers. In some embodiments, the

electrodes

30 and 32 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

30 and 32 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. In some embodiments, each of the

electrodes

30 and 32 forms ohmic contact with the nitride-based semiconductor layer 18. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials for the S/

D electrodes

30 and 32.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG 2D, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A nucleation layer 12 is formed on/over/above the substrate 10. A buffer layer 14 is formed on/over/above the nucleation layer 12. A nitride-based semiconductor layer 16 is formed on the buffer layer 14. A nitride-based semiconductor layer 18 is formed on the nitride-based semiconductor layer 16.

Referring to FIG. 2B, a mask layer 40 with an opening 402 is formed over the nitride-based semiconductor layer 18. At least one portion of the nitride-based semiconductor layer 18 is exposed from the opening 402. Portions of the nitride-based semiconductor layer 18 covered by the mask layer 40 can get protection from the mask layer 40.

Referring to FIG. 2C, the portion of the nitride-based semiconductor layer 18is oxidized to become an oxidized portion 184. The oxidized portion 184 includes InAlO. In some embodiments, the oxidizing can be performed by a thermal oxidation process or an anodic oxidation process via the opening 402. Since portions of the nitride-based semiconductor layer 18 are covered by the mask layer 40, such the oxidizing act as selective oxidation. Thereafter, the oxidized portion 184 is etched for removal.

Referring to FIG. 2D, the mask layer 40 is removed. An entirety of the oxidized portion is removed after the etching such that the nitride-based semiconductor layer 18 has a gate opening 182 with inner sidewalls. The oxidized portion of the nitride-based semiconductor layer 18 can have high etch selectivity ratio with respect to underlying GaN, and thus Gan can keep free from damage caused by the etching. Then, a gate electrode is formed to make contact with the inner sidewall of the nitride-based semiconductor layer 18. As such, an enhancement mode HEMT device can be manufactured with high quality channel layer.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 18 and the gate electrode 20 of the semiconductor device 1A is replaced by a nitride-based semiconductor layer 18B and a gate electrode 20B.

The nitride-based semiconductor layer 18B has a gate opening 182B. The gate opening 182B can be defined by inner sidewalls of the nitride-based semiconductor layer 18B, in which the inner sidewalls are curved. Since the gate opening 182B is formed by etching an oxidized portion, the profile of the gate opening 182B can be defined by how the profile of the oxidized portion is. As the oxidized portion can have the profile tuned by recipes of the process directly, the curve profile can be achieved. The gate electrode 20B makes contact with the curved inner sidewalls of the nitride-based semiconductor layer 18B, and the gate electrode 20B has curved sidewalls correspondingly.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 18 and the gate electrode 20 of the semiconductor device 1A is replaced by a nitride-based semiconductor layer 18C and a gate electrode 20C. The nitride-based semiconductor device 1C further includes an oxide layer 50C.

The oxide layer 50C has opposite sidewalls connecting to the nitride-based semiconductor layer 18. The oxide layer 50C is attached to inner sidewalls of the nitride-based semiconductor layer 18C and laterally overlapping with the nitride-based semiconductor layer 18C. In some embodiments, the oxide layer 50C can be formed by oxidizing a portion of the nitride-based semiconductor layer 18C, as afore-described.

In some embodiments, the nitride-based semiconductor layer 18C includes indium, and the oxide layer 50C includes indium. For example, the nitride-based semiconductor layer 18C may include InAlN and the oxide layer 50C may include InAlO. The oxide layer 50C can serve as a group III oxide layer. In the manufacturing process, after the oxide layer is formed, the subsequent etching stage can be omitted. After the oxide layer is formed, the gate electrode 20C is formed to connect with the oxide layer 50C (e.g., the oxidized portion 184 of the nitride-based semiconductor layer 18 in FIG. 2C) .

The oxide layer 50C can have a top surface substantially coplanar with a top surface of the nitride-based semiconductor layer 18C. The oxide layer 50C can abut against the nitride-based semiconductor layer 18C.

The gate electrode 20C is disposed over the nitride-based semiconductor layer 18C and with the oxide layer 50C. The gate electrode 20C is in contact with the nitride-based semiconductor layer 18C and with the oxide layer 50C. The gate electrode 20C is separated/spaced apart from the nitride-based semiconductor layer 16 by the oxide layer 50C.

Since the nitride-based semiconductor layer 18C is divided by the oxide layer 50C (i.e., laterally separated) , the 2DEG region can get discontinuous, thereby achieving the enhance mode.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 18 and the gate electrode 20 of the semiconductor device 1A is replaced by a nitride-based semiconductor layer 18D and a gate electrode 20D. The nitride-based semiconductor device 1C further includes an oxide layer 50D.

The oxide layer 50D is disposed over the nitride-based semiconductor layer. 16. The oxide layer 50D abuts against inner sidewalls of the nitride-based semiconductor layer 18D. An entirety of the oxide layer 50D is in a position lower than a top surface of the nitride-based semiconductor layer 18D. That is, the oxide layer 50D is thinner than the nitride-based semiconductor layer 18D. With respect to the oxide layer 50D, the stage of etching the oxidized portion of the nitride-based semiconductor layer 18D can be terminated when the oxidized portion becomes thinner and the oxidized portion still covers the nitride-based semiconductor layer 16.

The nitride-based semiconductor layer 18D and the oxide layer 50D can collectively form a recess to serve as a gate recess. The gate electrode 20D can fill into the recess. The gate electrode 20D can extend downward to get close to the III-V nitride-based semiconductor layer 16.

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 18 and the gate electrode 20 of the semiconductor device 1A is replaced by a nitride-based semiconductor layer 18E and a gate electrode 20E. The nitride-based semiconductor device 1C further includes an oxide layer 50E.

The oxide layer 50E is disposed over the nitride-based semiconductor layer. 16. The oxide layer 50E abuts against inner sidewalls of the nitride-based semiconductor layer 18E. An entirety of the oxide layer 50E is in a position lower than a top surface of the nitride-based semiconductor layer 18D. The oxide layer 50E has a recess 502E over the nitride-based semiconductor layer 16. With respect to the oxide layer 50E, the stage of etching the oxidized portion of the nitride-based semiconductor layer 18D can have varied recipes such that a recess is formed in the oxidized portion of the nitride-based semiconductor layer 18D.

The gate electrode 20E can align with the recess 502E and fills into the recess 502E. The gate electrode 20E has an downward extending portion which gets close to the nitride-based semiconductor layer 16 so the nitride-based semiconductor device 1E can have switching ratio improved.

The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device comprising:

a first III-V nitride-based semiconductor layer;

a second III-V nitride-based semiconductor layer disposed over the first III-V nitride-based semiconductor layer and having a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer;

a group III oxide layer attached to the second III-V nitride-based semiconductor layer and laterally overlapping with the second III-V nitride-based semiconductor layer; and

a gate electrode disposed over the second III-V nitride-based semiconductor layer and in contact with the group III oxide layer and the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein an entirety of the group III oxide layer is in a position lower than a top surface of the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer is attached to an inner sidewall of the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the gate electrode is in contact with the first and second III-V nitride-based semiconductor layers.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer having a top surface substantially coplanar with a top surface of the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the gate electrode is separated from the first III-V nitride-based semiconductor layer by the group III oxide layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer abuts against the second III-V nitride-based semiconductor layer
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer is thinner than the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the gate electrode fills into a recess collectively formed by the group III oxide layer and the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer has a recess over the first III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the gate electrode aligns with the recess and fills into the recess.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second III-V nitride-based semiconductor layer comprises indium.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second III-V nitride-based semiconductor layer comprises InAlN.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer comprises indium.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer comprises InAlO.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first III-V nitride-based semiconductor layer over a substrate;

forming a second III-V nitride-based semiconductor layer over the first III-V nitride-based semiconductor layer;

forming a mask layer with an opening over the second III-V nitride-based semiconductor layer, wherein at least one portion of the second III-V nitride-based semiconductor layer is exposed from the opening;

oxidizing the portion of the second III-V nitride-based semiconductor layer;

etching the oxidized portion of the second III-V nitride-based semiconductor layer such that the second III-V nitride-based semiconductor layer has an inner sidewall; and

forming a gate electrode in contact with the inner sidewall of the second III-V nitride-based semiconductor layer.
The method of any one of the preceding claims, wherein an entirety of the oxidized portion of the second III-V nitride-based semiconductor layer is removed after the etching.
The method of any one of the preceding claims, wherein etching the oxidized portion of the second III-V nitride-based semiconductor layer is performed such that the oxidized portion becomes thinner.
The method of any one of the preceding claims, wherein etching the oxidized portion of the second III-V nitride-based semiconductor layer is performed such that a recess is formed in the oxidized portion.
The method of any one of the preceding claims, wherein the gate electrode is formed to connect with the oxidized portion of the second III-V nitride-based semiconductor layer.
A nitride-based semiconductor device comprising:

a first III-V nitride-based semiconductor layer;

a second III-V nitride-based semiconductor layer disposed over the first III-V nitride-based semiconductor layer and having a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer;

a group III oxide layer having opposite sidewalls which connect to the second III-V nitride-based semiconductor layer; and

a gate electrode disposed over the second III-V nitride-based semiconductor layer and in contact with the group III oxide layer and spaced apart from the first III-V nitride-based semiconductor layer by the group III oxide layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer is thinner than the second III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second III-V nitride-based semiconductor layer comprises indium.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer comprises indium.
The nitride-based semiconductor device of any one of the preceding claims, wherein the group III oxide layer comprises InAlO.