WO2024103198A1

WO2024103198A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024103198A1
Application number: PCT/CN2022/131609
Authority: WO
Inventors: Sichao LI; Hui Yan; Xinyu Li
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2024-05-23

Abstract

The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, a plurality of fillings, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and extends along a first direction over the second nitride-based semiconductor layer. The doped III-V semiconductor layer comprises a plurality of segments arranged along the first direction. The fillings are disposed over the second nitride-based semiconductor layer and arranged along the first direction with the segments of the doped III-V semiconductor layer. The gate electrode is disposed over the doped III-V semiconductor layer and extends along the first direction over the doped III-V semiconductor layer. The gate electrode spans across the fillings.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Sichao LI; Hui YAN; Xinyu LI

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a patterned doped nitride-based semiconductor layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, a plurality of fillings, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and extends along a first direction over the second nitride-based semiconductor layer. The doped III-V semiconductor layer comprises a plurality of segments arranged along the first direction. The fillings are disposed over the second nitride-based semiconductor layer and arranged along the first direction with the segments of the doped III-V semiconductor layer. The gate electrode is disposed over the doped III-V semiconductor layer and extends along the first direction over the doped III-V semiconductor layer. The gate electrode spans across the fillings.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows: forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a doped III-V semiconductor layer on the second nitride-based semiconductor layer; performing a treatment to modify some portions of the doped III-V semiconductor layer such that the portions of the doped III-V semiconductor layer have a character different than the rest of the doped III-V semiconductor layer and become fillings abutting against the rest of the doped III-V semiconductor layer; and forming a gate electrode over the doped III-V semiconductor layer to span across the fillings.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, and a plurality of fillings. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and extends along a first direction over the second nitride-based semiconductor layer. The doped III-V semiconductor layer defines a plurality of trenches arranged along the first direction. The fillings are disposed over the second nitride-based semiconductor layer and extend along the first direction over second nitride-based semiconductor layer. A distance between two of the adjacent fillings is greater than a dimension of the filling along the first direction.

By the above configuration, the segments of the doped III-V semiconductor layer can serve as discontinuous depletion regions. Since each of the discontinuous depletion regions not only depletes a directly below area but also provides depletion laterally, the normally off character still can function. The fillings are disposed among the discontinuous depletion regions, which is advantageous to improve current density at on-state. The 2DEG concentration beneath the fillings can be improved, which results in the higher current density for the nitride-based semiconductor device at on-state.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a top-view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure;

FIG. 1B is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line I-I’ according to some embodiments of the present disclosure;

FIG. 1C is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line II-II’ according to some embodiments of the present disclosure;

FIG. 1D is a vertical cross-sectional view of a nitride-based semiconductor device taken along a line III-III’ according to some embodiments of the present disclosure;

FIG. 2A and FIG. 2B show different stages of a method for manufacturing the nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 6A is a top view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 6B is a top view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 7A is a top view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 7B is a top view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 8A is a top view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 8B is a top view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 9A is a top view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure;

FIG. 9B is a top view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure;

FIG. 10A is a top view of a nitride-based semiconductor device with a gate electrode according to some embodiments of the present disclosure; and

FIG. 10B is a top view of a nitride-based semiconductor device without a gate electrode according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a top-view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. Directions D1 and D2 are labeled in the FIG. 1A. The direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction of FIG. 1A and the direction D2 is the vertical direction of FIG. 1A.

FIG. 1B is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line I-I’ according to some embodiments of the present disclosure. FIG. 1C is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line II-II’ according to some embodiments of the present disclosure. FIG. 1D is a vertical cross-sectional view of a nitride-based semiconductor device 1A taken along a line III-III’ according to some embodiments of the present disclosure.

The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14,

electrodes

20 and 22, a doped III-V semiconductor layer 30, a gate electrode, and fillings 40.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the depletion mode device 1A may further include a buffer layer (not illustrated) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to or along the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

20 and 22 are disposed over the nitride-based semiconductor layer 14. The

electrodes

20 and 22 can extend along the direction D2 over the nitride-based semiconductor layer 14. Each of the

electrodes

20 and 22 can serve as a source electrode or a drain electrode. For example, the electrode 20 is a source electrode and the electrode 22 is the drain electrode. In some embodiments, the

electrodes

20 and 22 can be called ohmic electrodes.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20 and 22 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

In some embodiments, each of the

electrodes

20 and 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped III-V semiconductor layer 30 is disposed over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 can make contact with the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 can extend along the direction D2 over the nitride-based semiconductor layer 14. The doped III-V semiconductor layer 30 is located between the

electrodes

20 and 22. The doped III-V semiconductor layer 30 include a plurality of segments 302 arranged along the direction D2. The segments 302 are separated from each other.

The doped III-V semiconductor layer 30 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped p-type doped III-V semiconductor layer can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.

The fillings 40 are disposed over the nitride-based semiconductor layer 14. The fillings 40 can make contact with the nitride-based semiconductor layer 14.. The fillings 40 are located between the

electrodes

20 and 22. The fillings 40 are arranged along the direction D2 over the nitride-based semiconductor layer 14. The fillings 40 are alternately arranged with the segments 302 of the doped III-V semiconductor layer 30 along the direction D2. To put it another way, the segments 302 of the doped III-V semiconductor layer 30 can define a plurality of trenches arranged along the direction D2, in which the trenches are filled with the fillings 40. The segments 302 of the doped III-V semiconductor layer 30 and the fillings 40 abut against each other. For example, one of the segments 302 is located between two fillings 40 and abuts against these two fillings 40. The segments 302 of the doped III-V semiconductor layer 30 and the fillings 40 may have the same thickness. The exemplary materials of the fillings 40 can include, for example but are not limited to, group III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof.

In some embodiments, the doped III-V semiconductor layer 30 and the fillings 40 have side surfaces which facing the

electrode

20 or 22 and are coplanar with each other. Accordingly, the doped III-V semiconductor layer 30 and the fillings 40 can have the same width along the direction D1. This is because the doped III-V semiconductor layer 30 and the fillings 40 can be formed from the same III-V semiconductor layer, which is advantageous to simplified the manufacturing process. In some embodiments, the doped III-V semiconductor layer 30 and the fillings 40 are made of the same III-V semiconductor material but different conductivities. The doped III-V semiconductor layer 30 may be made of p-type doped same III-V semiconductor compound and the fillings 40 may be made of intrinsic III-V semiconductor compound. For example, the doped III-V semiconductor layer 30 is made of p-type GaN, and the fillings 40 are made of intrinsic GaN.

The combination of the doped III-V semiconductor layer 30 and the fillings 40 can bring the nitride-based semiconductor device 1A into an enhancement mode, which is called a normally off mode as well. In this regard, the segments 302 of the doped III-V semiconductor layer 30 can serve as discontinuous depletion regions. Since each of the discontinuous depletion regions not only depletes a directly below area but also provides depletion laterally, the normally off character still can function. The filling 40 are disposed among the discontinuous depletion regions, which is advantageous to improve current density at on-state. On the contrary, a continuous depletion region (i.e., an entirety of the p-type doped nitride-based semiconductor layer is continuous) will have lower current density at on-state. By the configuration of the present embodiment, the 2DEG concentration beneath the fillings 40 can be improved, which results in the higher current density for the nitride-based semiconductor device 1A at on-state.

The gate electrode 32 is disposed over the doped III-V semiconductor layer 30. The gate electrode 32 can extend along the direction D2 over the doped III-V semiconductor layer 30. The gate electrode 32 can span across the fillings 40 such that the gate electrode 32 can extend along the direction D2 over the fillings 40 as well. As shown in FIG. 1A, the gate electrode 32 is narrower than the doped III-V semiconductor layer 30 as well as the fillings 40. The gate electrode 32 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. The

electrodes

20, 22, and the gate electrode 32 can constitute an enhancement mode HEMT with the doped III-V semiconductor layer 30.

In order to maintain the E-mode character with the higher current density improved, a relationship among the doped III-V semiconductor layer 30 and the fillings 40 is made. For example, as shown in FIG. 1A, a distance between two of the adjacent fillings 40 is greater than a dimension of the filling 40 along the direction D2 (i.e., a length along the direction D2) . More specifically, as shown in FIG. 1A and FIG. 1D, each of the fillings 40 has a length L1 along the direction D2; the adjacent fillings 40 are spaced apart from a length L2; and 1/4≤L1/L2≤1. The relationship can further make sure for placing the nitride-based semiconductor device 1A into an off-state condition. Furthermore, by adjusting the ratio of L1/L2, the device threshold voltage can be modulated, such that a desired value for the device threshold voltage is obtained.

Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A and FIG. 2B as described below. FIG. 2A and FIG. 2B are top views of the stages. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, nitride-based semiconductor layers (i.e., a channel layer and a barrier layer) are formed. A doped III-V semiconductor layer 30 is formed on the nitride-based semiconductor layer 14. The formation of the doped III-V semiconductor layer 30 may include a pattering process.

Referring to FIG. 2B, a treatment is performed to modify some portions of the doped III-V semiconductor layer 30 such that the portions of the doped III-V semiconductor layer 30 have a character different than the rest of the doped III-V semiconductor layer 30. Those treated portions of the doped III-V semiconductor layer 30 can become fillings 40 abutting against the rest of the doped III-V semiconductor layer 30. In some embodiments, the treatment includes ion implantation to the doped III-V semiconductor layer 30. For example, the ion implantation can act as anti-doping to the those treated portions of the doped III-V semiconductor layer 30 so doped portion can become intrinsic. After the formation of the fillings 40, a gate electrode as afore described can be formed over the doped III-V semiconductor layer 30 and the fillings 40.

Although the fillings are achieved by anti-doping so as to obtain intrinsic III-V semiconductor layer in the afore described, the fillings can be formed by other manners.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The position of the sectional view in FIG. 3 is taken as being identical with FIG. 1C. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40B.

The filling 40B is disposed over the nitride-based semiconductor layer 14. The filling 40B can make contact with the nitride-based semiconductor layer 14. The filling 40B can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped p-type doped III-V semiconductor layer can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.

The filling 40B is thinner than the doped III-V semiconductor layer (e.g., the doped III-V semiconductor layer 30 as shown in FIG. 1B) . That is, the thinner filling 40B provide weaker depletion effect than the doped III-V semiconductor layer (e.g., the doped III-V semiconductor layer 30 as shown in FIG. 1B) . The nitride-based semiconductor device 1B can be placed into an off-state condition. Further, the 2DEG concentration beneath the fillings 40 can be improved still due to the depletion effect weaker than the doped III-V semiconductor layer (e.g., the doped III-V semiconductor layer 30 as shown in FIG. 1B) , which results in the higher current density for the nitride-based semiconductor device 1B at on-state as well. To obtain the structure as shown in FIG. 3, the treatment as afore mentioned may include an etching process such that the filling 40 can get thinner than the doped III-V semiconductor layer (e.g., the doped III-V semiconductor layer 30 as shown in FIG. 1B) .

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The position of the sectional view in FIG. 4 is taken as being identical with FIG. 1C. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are omitted. The gate electrode 32 can directly makes contact with the nitride-based semiconductor layer 14. At the region that the gate electrode 32 directly make contact with the nitride-based semiconductor layer 14, no depletion effect is directly applied to the 2DEG region from the above of the 2DEG region, which results in the higher current density for the nitride-based semiconductor device 1C at on-state as well. To obtain the structure as shown in FIG. 4, the treatment as afore mentioned may include an etching process such that the treated portions of the doped III-V semiconductor layer are entirely removed.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The position of the sectional view in FIG. 5 is taken as being identical with FIG. 1C. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40D.

The filling 40D is disposed over the nitride-based semiconductor layer 14. The filling 40D can make contact with the nitride-based semiconductor layer 14. The filling 40B can be made of an insulator material, such as SiO ₂, Si ₃N ₄, or combinations thereof. At the region that the filling 40D directly makes contact with the nitride-based semiconductor layer 14, no depletion effect is directly applied to the 2DEG region from the above of the 2DEG region, which results in the higher current density for the nitride-based semiconductor device 1D at on-state as well. Moreover, the filling 40 made of at least one insulating material can suppress the device threshold voltage shift caused by the hybrid gate structure of the p-type doped nitride-based semiconductor layer and the gate electrode. This is because the insulator material can burden part of the gate voltage, reducing the negative shift of the device threshold voltage. To obtain the structure as shown in FIG. 5, the treatment as afore mentioned may include an etching process such that the treated portions of the doped III-V semiconductor layer are entirely removed, thereby forming trenches. Thereafter, the trenches are filled with at least one insulating material so as to from the filling 40.

FIG. 6A is a top view of a nitride-based semiconductor device 1E with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 6B is a top view of a nitride-based semiconductor device 1E without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 6B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in the FIGS. 6A and 6B. The direction D1 is the horizontal direction of FIGS. 6A and 6B and the direction D2 is the vertical direction of FIGS. 6A and 6B.

The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40E. The fillings 40E have a profile different than the fillings as afore mentioned. More specifically, each of the fillings 40E has a width varying along the direction D1. As illustrated in FIG. 6A and FIG. 6B, each of the fillings 40E has the width decreasing along the direction D1. Accordingly, each of the fillings 40E is in triangle shape in a top view thereof.

The filling 40E can be achieved by using embodiments as above, such as intrinsic III-V semiconductor layer, thinner doped III-V semiconductor layer, insulator, empty of III-V semiconductor layer. Such the profile of the filling 40E can be configured to modulate or adjust the device threshold voltage, since the current density in the 2DEG beneath the filling 40E is greater than others in the 2DEG.

FIG. 7A is a top view of a nitride-based semiconductor device 1F with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 7B is a top view of a nitride-based semiconductor device 1F without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 7B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in the FIGS. 7A and 7B. The direction D1 is the horizontal direction of FIGS. 7A and 7B and the direction D2 is the vertical direction of FIGS. 7A and 7B.

The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40F. The fillings 40F have a profile different than the fillings as afore mentioned. More specifically, each of the fillings 40F has a width varying along the direction D1. As illustrated in FIG. 7A and FIG. 7B, each of the fillings 40F has the width increasing along the direction D1. Accordingly, each of the fillings 40F is in triangle shape in a top view thereof.

The filling 40F can be achieved by using embodiments as above, such as intrinsic III-V semiconductor layer, thinner doped III-V semiconductor layer, insulator, empty of III-V semiconductor layer. Such the profile of the filling 40F can be configured to modulate or adjust the device threshold voltage, since the current density in the 2DEG beneath the filling 40E is greater than others in the 2DEG.

FIG. 8A is a top view of a nitride-based semiconductor device 1G with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 8B is a top view of a nitride-based semiconductor device 1G without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 8B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in the FIGS. 8A and 8B. The direction D1 is the horizontal direction of FIGS. 8A and 8B and the direction D2 is the vertical direction of FIGS. 8A and 8B.

The nitride-based semiconductor device 1G is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40G. The fillings 40G have a profile different than the fillings as afore mentioned. More specifically, each of the fillings 40G has a width varying along the direction D1. As illustrated in FIG. 8A and FIG. 8B, each of the fillings 40G has the width decreasing along the direction D1. Accordingly, each of the fillings 40F is in trapezoid shape in a top view thereof.

The filling 40G can be achieved by using embodiments as above, such as intrinsic III-V semiconductor layer, thinner doped III-V semiconductor layer, insulator, empty of III-V semiconductor layer. Such the profile of the filling 40G can be configured to modulate or adjust the device threshold voltage, since the current density in the 2DEG beneath the filling 40E is greater than others in the 2DEG.

FIG. 9A is a top view of a nitride-based semiconductor device 1H with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 9B is a top view of a nitride-based semiconductor device 1H without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 9B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in the FIGS. 9A and 9B. The direction D1 is the horizontal direction of FIGS. 9A and 9B and the direction D2 is the vertical direction of FIGS. 9A and 9B.

The nitride-based semiconductor device 1H is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40H. The fillings 40H have a profile different than the fillings as afore mentioned. More specifically, each of the fillings 40H has a width varying along the direction D1. As illustrated in FIG. 9A and FIG. 9B, each of the fillings 40H has the width increasing along the direction D1. Accordingly, each of the fillings 40H is in trapezoid shape in a top view thereof.

The filling 40H can be achieved by using embodiments as above, such as intrinsic III-V semiconductor layer, thinner doped III-V semiconductor layer, insulator, empty of III-V semiconductor layer. Such the profile of the filling 40H can be configured to modulate or adjust the device threshold voltage, since the current density in the 2DEG beneath the filling 40E is greater than others in the 2DEG.

FIG. 10A is a top view of a nitride-based semiconductor device 1I with a gate electrode 32 according to some embodiments of the present disclosure. FIG. 10B is a top view of a nitride-based semiconductor device 1I without a gate electrode 32 according to some embodiments of the present disclosure. FIG. 10B is made for convenient understanding to the structure. Directions D1 and D2 are labeled in the FIGS. 10A and 10B. The direction D1 is the horizontal direction of FIGS. 10A and 10B and the direction D2 is the vertical direction of FIGS. 10A and 10B.

The nitride-based semiconductor device 1I is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A-1D, except that the fillings 40 are replaced by fillings 40I. The fillings 40I have a profile that is in combination with different embodiments as afore mentioned. For example, the profile of the fillings 40I include trapezoid shape and triangle shape, which is advantageous to further modulation or adjustment of the device threshold voltage.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped III-V semiconductor layer disposed over the second nitride-based semiconductor layer and extending along a first direction over the second nitride-based semiconductor layer, wherein the doped III-V semiconductor layer comprises a plurality of segments arranged along the first direction;

a plurality of fillings disposed over the second nitride-based semiconductor layer and arranged along the first direction with the segments of the doped III-V semiconductor layer; and

a gate electrode disposed over the doped III-V semiconductor layer and extending along the first direction over the doped III-V semiconductor layer, wherein the gate electrode spans across the fillings.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings has a length L1 along the first direction, the adjacent fillings are spaced apart from a length L2, and 1/4≤L1/L2≤1.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings are made of intrinsic III-V semiconductors.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings are made of intrinsic GaN, and the doped III-V semiconductor layer is made of p-type GaN.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings is thinner than the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings and the doped III-V semiconductor layer are made of a doped III-V semiconductor material.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings are made of an insulator material.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings has a width varying along a second direction different than the first direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings has the width decreasing along the second direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings has the width increasing along the second direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings is in triangle shape in a top view thereof.
The nitride-based semiconductor device of any one of the preceding claims, wherein each of the fillings is in trapezoid shape in a top view thereof.
The nitride-based semiconductor device of any one of the preceding claims, wherein the doped III-V semiconductor layer and the fillings have side surfaces coplanar with each other.
The nitride-based semiconductor device of any one of the preceding claims, wherein the doped III-V semiconductor layer and the fillings have the same width along the first direction.
The nitride-based semiconductor device of any one of the preceding claims, further comprising:

a source electrode and a drain electrode disposed over the second nitride-based semiconductor layer and extending along the first direction over the second nitride-based semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode.
A method for manufacturing a semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a doped III-V semiconductor layer on the second nitride-based semiconductor layer;

performing a treatment to modify some portions of the doped III-V semiconductor layer such that the portions of the doped III-V semiconductor layer have a character different than the rest of the doped III-V semiconductor layer and become fillings abutting against the rest of the doped III-V semiconductor layer; and

forming a gate electrode over the doped III-V semiconductor layer to span across the fillings.
The method of any one of the preceding claims, wherein the treatment comprises ion implantation to the doped III-V semiconductor layer.
The method of any one of the preceding claims, wherein each of the fillings has a length L1, the adjacent fillings are spaced apart from a length L2, and 1/4≤L1/L2≤1.
The method of any one of the preceding claims, wherein the fillings are made of intrinsic III-V semiconductors.
The method of any one of the preceding claims, wherein the treatment comprises an etching process such that the fillings are thinner than the doped III-V semiconductor layer.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped III-V semiconductor layer disposed over the second nitride-based semiconductor layer and extending along a first direction over the second nitride-based semiconductor layer, wherein the doped III-V semiconductor layer defines a plurality of trenches arranged along the first direction; and

a plurality of fillings disposed over the second nitride-based semiconductor layer and extending along the first direction over second nitride-based semiconductor layer, wherein a distance between two of the adjacent fillings is greater than a dimension of the filling along the first direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings make contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the fillings abut against the doped III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the doped III-V semiconductor layer and the fillings have side surfaces coplanar with each other.
The nitride-based semiconductor device of any one of the preceding claims, wherein the doped III-V semiconductor layer and the fillings have the same width along the first direction.