WO2016208864A1

WO2016208864A1 - Nitride-based transistor for implementing normally-off

Info

Publication number: WO2016208864A1
Application number: PCT/KR2016/004501
Authority: WO
Inventors: 타케야모토노부; 요코가와도시야
Original assignee: 서울반도체 주식회사
Priority date: 2015-06-24
Filing date: 2016-05-12
Publication date: 2016-12-29
Also published as: KR20170000612A

Abstract

A nitride-based transistor for implementing normally-off, according to an embodiment, comprises: an n-type-doped first nitride-based first semiconductor layer grown on an m-surface; an insulating second nitride-based second semiconductor layer disposed on the first semiconductor layer; and a gate electrode layer disposed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer have different energy band gaps.

Description

A nitride-based transistor that implements normally-off

This disclosure relates generally to nitride-based transistors, and more particularly to nitride-based transistors that implement a normally-off.

BACKGROUND ART [0002] With the development of information and communication technologies, there is an increasing demand for high-voltage transistors operating in a high-speed switching environment or a high-voltage environment. Therefore, a gallium nitride transistor using a recently developed III-V semiconductor material is capable of high-speed switching operation as compared with a conventional silicon transistor, and is suitable not only for ultra-high speed signal processing but also for high voltage It has attracted the attention of the industry due to its applicability.

Such a gallium nitride-based transistor can be manufactured in a horizontal structure or a vertical structure. The horizontal structure means a structure in which the charge conduction from the source electrode layer to the drain electrode layer is formed in the lateral direction and generally has a structure in which the source electrode layer, the gate electrode layer, and the drain electrode layer are disposed on the same surface of the substrate .

Unlike the above-described horizontal structure, a vertical structure recently appeared means a structure in which charge conduction from the source electrode layer to the drain electrode layer is made in the vertical direction, and the structure disclosed in U.S. Patent Publication No. 2012-0319127 A Current Aperture Vertical Electron Transistor (CAVET) can be presented as an example. According to the CAVET, the source electrode layer and the drain electrode layer are arranged to face each other in the vertical direction, and a p-type gallium nitride (p-GaN) layer is disposed as a current barrier layer therebetween. Then, the current flows vertically from the source electrode layer to the drain electrode layer through the aperture provided by the p-type gallium nitride (p-GaN) layer.

On the other hand, in order to commercialize the above-described horizontal and vertical structures, there is still a demand for a technique for securing reliability in an on-off switching operation through a channel layer.

Embodiments of the present disclosure provide a structure of a nitride-based transistor that reliably implements a normally-off state.

The embodiment of the present disclosure provides a structure of a nitride-based transistor capable of improving the electric conductivity of a channel layer at the time of turning on.

A nitride-based transistor implementing a normally-off according to one aspect includes: an n-type doped first nitride based first semiconductor layer grown on an m-plane; An insulating second nitride based second semiconductor layer disposed on the first semiconductor layer; And a gate electrode layer disposed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer have different energy band gaps.

A nitride-based transistor implementing a normally-off according to another aspect comprises: an n-type doped first nitride based first semiconductor layer grown on a c-plane; A p-type doped first nitride based second semiconductor layer disposed on the first semiconductor layer; A first nitride based third semiconductor layer disposed along the inner wall of the trench passing through the second semiconductor layer to reach the inside of the first semiconductor layer and disposed on the second semiconductor layer outside the trench; An insulating second nitride-based fourth semiconductor layer disposed on the third semiconductor layer inside and outside the trench; And a gate electrode layer disposed on the fourth semiconductor layer. The third semiconductor layer and the fourth semiconductor layer have different energy band gaps.

According to one embodiment of the present disclosure, a nitride-based transistor can be manufactured using the first nitride-based semiconductor layer grown on the m-plane as a conductive layer. When the first nitride semiconductor layer is grown on the m-plane, spontaneous polarization in the first nitride semiconductor layer can be suppressed. As a result, formation of a charge high-conductivity layer such as a 2DEG layer due to various polarization phenomena can be effectively suppressed in the junction interface region with the second nitride-based semiconductor layer having different energy bandgaps. Thus, in the nitride-based transistor, the normally-off state can be effectively realized.

According to one embodiment of the present disclosure, a nitride-based transistor can be manufactured using the first nitride-based semiconductor layer grown on the c-plane as a conductive layer. When the first nitride-based semiconductor layer is grown on the c-plane, the 2DEG layer can be formed in the junction interface region with the second nitride-based semiconductor layer having a different energy bandgap. On the other hand, in this embodiment, a trench can be formed in the first nitride based semiconductor layer and a channel layer can be formed in the first nitride based semiconductor layer in a direction parallel to the side wall of the trench. The direction parallel to the sidewalls of the trench is perpendicular to the c-plane, and polarization can be suppressed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer. Thus, the formation of the 2DEG layer can be suppressed. As a result, in the nitride-based transistor, the normally-off state can be effectively realized. In addition, a 2DEG layer is formed in the interface region of the first and second nitride based semiconductor layers except the channel layer at the time of turning on, thereby increasing the amount of charge supplied to the channel layer and increasing the amount of current flowing through the channel layer .

The effects of the disclosed techniques described above are to illustrate any of the various effects derived from the configuration of one embodiment of the present disclosure and not to preclude other various effects that may be apparently derived from the configuration of the presented embodiments.

1 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the first embodiment of the present disclosure;

2 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to a second embodiment of the present disclosure;

3A-3F are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to one embodiment of the present disclosure.

4A through 4H are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to another embodiment of the present disclosure.

5A and 5B are cross-sectional views schematically illustrating a nitride-based transistor implementing a normally-off according to a third embodiment of the present disclosure.

6 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the fourth embodiment of the present disclosure;

Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device.

Where an element is referred to herein as being located on another element "above" or "below", it is to be understood that the element is directly on the other element "above" or "below" It means that it can be intervened. In this specification, the terms 'upper' and 'lower' are relative concepts set at the observer's viewpoint. When the viewer's viewpoint is changed, 'upper' may mean 'lower', and 'lower' It may mean.

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In this specification, the source electrode layer and the drain electrode layer are referred to for convenience in consideration of the direction of current. When the direction of current changes due to a change in the applied voltage polarity, the source electrode layer becomes a drain electrode layer, It may mean an electrode layer.

In this specification, the interfacial region between one thin film layer and another thin film layer is interpreted to include not only the interface between one thin film layer and another thin film layer but also an inner region of a predetermined depth from the surface of one thin film layer or another thin film layer adjacent to the interface .

In this specification, the nitride-based semiconductor layer or the nitride-based material layer may include a nitride such as AlxInyGa1-x-yN (0? X? 1, 0? Y? The nitride-based semiconductor layer or the nitride-based material layer may be formed by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MIB), hydride vapor phase epitaxy And the like can be used to form the epitaxial film. The method of forming the epitaxial layer is an example and may be performed at a temperature of 1000 ° C to 1100 ° C.

In this specification, the n-type or p-type doping implies that the n-type dopant is doped into the nitride-based semiconductor layer or the nitride-based material layer by about 1E16 / cm ³ or more and the p-type dopant is doped with 1E17 / cm ³ or more can do. Also, the expression 'doping with a high concentration of n-type' means that the n-type dopant is doped into the nitride-based semiconductor at a concentration of about 1E19 / cm ³ or more.

In this specification, when doping the nitride-based semiconductor layer into n-type or p-type, for example, when doping to the n-type, silicon (Si), germanium (Ge), selenium (Se), tellurium Te, etc. may be applied. When doping to p-type, beryllium (Be), magnesium (Mg), calcium (Ca), carbon (C), iron (Fe), manganese can do.

In this specification, the nitride based semiconductor layer can grow on the c-plane or the m-plane. As an example, when the nitride-based semiconductor layer is a GaN layer and the GaN layer is grown on the c-plane, the GaN layer is alternately stacked with the Ga layer and the N layer along the height direction (i.e., the direction perpendicular to the c- Structure. The m-plane may mean a plane substantially perpendicular to the c-plane. For example, when grown in the height direction on the m-plane, a unit GaN layer in which Ga and N coexist can be stacked in a multi- have.

1 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the first embodiment of the present disclosure; 1, the nitride-based transistor 10 includes an n-type doped first nitride based first semiconductor layer 110 grown on an m-plane, and an insulating second nitride layer 110 disposed on the first semiconductor layer 110. The first nitride- A second semiconductor layer 120, and a gate electrode layer 130 disposed on the second semiconductor layer 120. At this time, the first semiconductor layer 110 and the second semiconductor layer 120 may have different energy band gaps. For convenience of discussion, the y direction in Fig. 1 is set to a direction perpendicular to the m-plane.

The nitride-based transistor 110 includes a p-type doped third semiconductor layer 140 disposed in the first semiconductor layer 110 and a source electrode layer 150 disposed on the third semiconductor layer 140 . The third semiconductor layer 140 may be disposed in contact with the first semiconductor layer 110 in the lateral direction of the gate electrode layer 130.

The nitride-based transistor 110 includes an n-type doped first nitride based fourth semiconductor layer 160 disposed on the lower surface of the first semiconductor layer 110 and the third semiconductor layer 140, A first n-type doped first nitride semiconductor layer 170 disposed on the lower surface of the first semiconductor layer 160 and a drain electrode layer 180 disposed on the lower surface of the fifth semiconductor layer 170. Drain electrode layer 180 may form an ohmic contact with the fifth semiconductor layer 170.

Referring again to FIG. 1, the first connection pattern layer 141 may be disposed on the third semiconductor layer 140. The first connection pattern layer 141 may be doped with a high concentration n-type and may form ohmic junctions with the first semiconductor layer 110 and the source electrode layer 150, respectively. The first connection pattern layer 141 may be formed by count doping the third semiconductor layer 140 doped with p-type. As described above, the source electrode layer 150 may be electrically connected to the first semiconductor layer 110 through the first connection pattern layer 141.

Referring again to FIG. 1, a second connection pattern layer 142 formed on the third semiconductor layer 140 and surrounded by the source electrode layer 142 may be disposed. The second connection pattern layer 142 may form an ohmic contact with the third semiconductor pattern layer 140. The second connection pattern layer 142 may be formed of a metal or an alloy. In addition, the second connection pattern layer 142 may be electrically connected to the source electrode layer 150.

As a result, when a voltage is applied to the source electrode layer 150, the voltage is applied to the first and second semiconductor layers 110 and 140 through the first and second connection pattern layers 141 and 142, respectively .

In one embodiment, the first semiconductor layer 110 may be an n-type doped GaN layer, the second semiconductor layer 120 may be an AlGaN layer, and the third semiconductor layer 130 may be a p-type doped GaN layer . At this time, the first and third semiconductor layers 110 and 130 may grow on the m-plane. In the AlGaN layer, the content of Al may be about 10 to 50 atomic%.

In addition, the fourth semiconductor layer 160 may be an n-type doped GaN layer, and the fifth semiconductor layer 170 may be a n-type doped GaN layer having a high concentration. The fourth semiconductor layer 160 and the fifth semiconductor layer 170 may be GaN layers grown in the m-plane. For example, the fifth semiconductor layer 170 may be a high-concentration n-type doped GaN substrate having an m-plane as an upper surface.

The first connection pattern layer 141 may be a high concentration n-type doped GaN layer. The second connection pattern layer 142 may include a metal such as nickel (Ni) and gold (Au). As a specific example, the second connection pattern layer 130 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

The source electrode layer 150 and the drain electrode layer 180 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked. The gate electrode layer 130 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the gate electrode layer 130 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

In this embodiment, the second semiconductor layer 120 may function as a gate dielectric layer at the bottom of the gate electrode layer 130. As an example, when the second semiconductor layer 120 is an AlGaN layer, the AlGaN layer may not be intentionally doped. Alternatively, the AlGaN layer may be doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).

In the nitride-based transistor of this embodiment, a depletion layer formed by the PN junction at the interface between the first semiconductor layer 110 and the third semiconductor layer 140 in the turn-off state is formed inside the first semiconductor layer 110 Can be filled. The electrons supplied from the source electrode layer 150 through the first connection pattern layer 141 are trapped by the depletion layer and the electrons supplied to the drain electrode layer 180 via the fourth and fifth semiconductor layers 160 The charge transfer can be suppressed. That is, when the voltage lower than the threshold voltage is maintained in the gate electrode layer 130, the nitride-based transistor 10 can maintain the normally-off state.

When an operation voltage equal to or higher than the threshold voltage is applied to the gate electrode layer 130, the nitride-based transistor 10 can be turned on. At this time, the depletion layer under the gate electrode layer 130 is removed, so that the charge conductivity of the first semiconductor layer 110 can be restored. A conductive channel is formed due to the recovered charge conductivity and the source electrode layer 150, the first connection pattern layer 141, the first semiconductor layer 110, the fourth semiconductor layer 160, the fifth semiconductor layer 170 To reach the drain electrode layer 180 can be formed. As a result, electric current is conducted between the source electrode layer 150 and the drain electrode layer 170.

In this embodiment, a nitride semiconductor layer having a different energy band gap from the first semiconductor layer 110 may be used as the second semiconductor layer 120 serving as a gate dielectric layer. The difference in lattice constant at the interface between the gate dielectric layer 120 and the first semiconductor layer 110 can be relatively reduced by applying a nitride based semiconductor layer instead of using a silicon oxide film or a silicon nitride film as the gate dielectric layer 120. [ As shown in FIG. Accordingly, the impurity density existing at the interface between the gate dielectric layer 120 and the first semiconductor layer 110 can be reduced, thereby realizing the channel ON / OFF operation of the nitride-based transistor more reliably.

In this embodiment, the first nitride based first semiconductor layer 110 grown on the m-plane is arranged to be bonded to the second nitride based second semiconductor layer 120, so that the nitride based system having the different energy bandgap Generation of spontaneous polarization or piezoelectric polarization in the interface region of the semiconductor layer can be suppressed. Thus, the formation of the 2DEG layer in the interface region of the first nitride based first semiconductor layer 110 and the second nitride based second semiconductor layer 120 can be suppressed. Accordingly, charge can be prevented from moving through the 2DEG layer in the turn-off state, and the normally-off characteristic of the nitride-based transistor can be reliably realized.

2 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to a second embodiment of the present disclosure; Referring to FIG. 2, the nitride-based transistor 20 includes a gate insulating layer 235 disposed between the second semiconductor layer 120 and the gate electrode layer 130, The structure of the nitride-based transistor 10 is substantially the same.

The gate dielectric layer 235 may comprise, by way of example, silicon oxide, silicon nitride, silicon oxynitride. The gate dielectric layer 235 can more reliably realize the conductive channel forming operation by the gate electrode layer 130 together with the second semiconductor layer 120. [

3A-3F are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to one embodiment of the present disclosure. Referring to FIG. 3A, a high concentration n-type doped first nitride based first material layer 310 is prepared. The first material layer 310 may grow on the m-plane. As an example, the first material layer 310 may be a GaN substrate having an m-plane as an upper surface.

Next, a first nitride based second material layer 320 doped with n-type is formed on the first material layer 310. The second material layer 320 may grow on the m-plane of the first material layer 310. Accordingly, the second material layer 320 may be formed in a direction perpendicular to the m-plane. Next, a p-type doped first nitride based third material layer 330 is formed on the second material layer 320. The third material layer 330 may grow on the m-plane of the second material layer 320. Accordingly, the third material layer 330 may be formed in a direction perpendicular to the m-plane. Then, an n-type dopant is selectively implanted into the third material layer 330 to form a first n-type doped first connection pattern layer 340 having a high concentration.

Referring to FIG. 3B, the third material layer 330 is patterned to form a third material pattern layer 335 including the first connection pattern layer 340 therein.

Referring to FIG. 3C, an n-type doped first nitride based fourth material layer 350 is formed on the second material layer 320 so as to burie the third material pattern layer 335. The fourth material layer 350 may be formed by growing in the height direction on the m-plane. Next, an insulating second nitride-based fifth material layer 360 is formed on the fourth material layer 350. The second nitride based fifth material layer 360 has a different energy band gap from the fourth material layer 350.

In one embodiment, the first nitride based first to fourth material layers 310, 320, 330, 350 may be a GaN layer and the second nitride based material layer 360 may be an AlGaN layer. The AlGaN layer is not intentionally doped or the AlGaN layer is doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).

Referring to FIG. 3D, a trench 370 is formed by sequentially patterning the fifth material layer 360 and the fourth material layer 350 to expose the first connection pattern layer 340 and the third material pattern layer 335, .

Referring to FIG. 3E, a second connection pattern layer 375 is formed on the third material pattern layer 335 in the trench 370. The second connection pattern layer 375 may form an ohmic contact with the third material pattern layer 335. The second connection pattern layer 375 may include a metal such as nickel (Ni) and gold (Au) as an example. As a specific example, the second connection pattern layer 375 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

Next, a gate electrode layer 380 is formed on the fifth material layer 360 between the trenches 370. The gate electrode layer 380 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the gate electrode layer 130 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

Referring to FIG. 3F, a source electrode layer 390 covering the second connection pattern layer 375 in the trench 370 is formed. The source electrode layer 390 may form an ohmic contact with the first connection pattern layer 340. The source electrode layer 390 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked.

On the other hand, a drain electrode layer 305 can be formed on the lower surface of the first material layer 310. The drain electrode layer 305 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked.

By proceeding with the above-described manufacturing method, a nitride-based transistor implementing the normally-off can be manufactured. As an example, the manufacturing method of Figs. 3A to 3F can be applied to the manufacturing method of the nitride-based

transistors

10 and 20 described above with reference to Figs.

Although not shown, in some embodiments, a layer of dielectric material, which acts as a gate dielectric layer, is added between the gate electrode layer 380 and the fifth material layer 360, when forming the gate electrode layer 380 of Figure 3e . The dielectric material layer may comprise, by way of example, silicon oxide, silicon nitride, silicon oxynitride.

4A through 4H are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to another embodiment of the present disclosure. Referring to FIG. 4A, a high concentration n-type doped first nitride based first material layer 310 is prepared. The first material layer 310 may grow on the m-plane. As an example, the first material layer 310 may be a GaN substrate having an m-plane as an upper surface.

Next, a first nitride based second material layer 320 doped with n-type is formed on the first material layer 310. The second material layer 320 may grow on the m-plane of the first material layer 310. Accordingly, the second material layer 320 may be formed in a direction perpendicular to the m-plane. Next, a p-type doped first nitride based third material layer 330 is formed on the second material layer 320. The third material layer 330 may grow on the m-plane of the second material layer 320. Accordingly, the third material layer 330 may be formed in a direction perpendicular to the m-plane. Then, a high concentration n-type doped first nitride based contact material layer 440 is formed on the third material layer 330. Next,

Referring to FIG. 4B, the contact material layer 440 is selectively etched to form a contact pattern layer 445.

Referring to FIG. 4C, the third material layer 330 is selectively etched to form a third material pattern layer 335 having a connection pattern layer 445 on the second material layer 320 .

Referring to FIG. 4D, a first nitride based fourth material layer 350 is formed on the second material layer 320 to fill the third material pattern layer 335 and the connection pattern layer 445. The fourth material layer 350 may be doped n-type. In addition, the fourth material layer 350 may be formed by growing in the height direction on the m-plane.

Referring to FIG. 4E, a second nitride based fifth material layer 360 is formed on the fourth material layer 350. The fifth material layer 360 may have different band gap energies compared to the fourth material layer 350.

In one embodiment, the first to fourth material layers 310, 320, 330, 350 and the nitride based connecting layer may be a GaN layer and the fifth material layer 360 may be an AlGaN layer. The AlGaN layer is not intentionally doped or the AlGaN layer is doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).

4F, a trench 470 is formed by selectively etching the fifth material layer 360, the fourth material layer 350, and the connection pattern layer 445 to expose the third material pattern layer 335, . The connection pattern layer 445 can be separated by the trench 470 and a pair of first connection pattern layers 445 can be formed.

Referring to FIG. 4G, a second connection pattern layer 475 is formed on the third material pattern layer 335 in the trench 470. The second connection pattern layer 475 may form an ohmic contact with the third material pattern layer 335. The second connection pattern layer 475 may include a metal such as nickel (Ni) and gold (Au) as an example. As a specific example, the second connection pattern layer 475 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

Referring to FIG. 4H, a gate electrode layer 380 is formed on the fifth material layer 360. The gate electrode layer 380 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the gate electrode layer 130 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

Further, a source electrode layer 390 filling the trench 470 is formed so as to cover the second connection pattern layer 475. The source electrode layer 390 may form an ohmic contact with the first connection pattern layer 340. The source electrode layer 390 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked.

Referring again to FIG. 4H, a drain electrode layer 305 may be formed on the lower surface of the first material layer 310. FIG. The drain electrode layer 305 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked.

By proceeding with the above-described manufacturing method, a nitride-based transistor implementing the normally-off can be manufactured. As an example, the manufacturing method of Figs. 4A to 4H can be applied to the manufacturing method of the nitride-based

transistors

10 and 20 described above with reference to Figs.

5A and 5B are cross-sectional views schematically illustrating a nitride-based transistor implementing a normally-off according to a third embodiment of the present disclosure. Specifically, FIG. 5A schematically shows the turn-off state of the nitride-based transistor 30, and FIG. 5B schematically shows the turn-on state of the nitride-based transistor 30. FIG.

5A, the nitride-based transistor 30 includes an n-type doped first nitride based first semiconductor layer 510 grown on a c-plane, a second nitride based first semiconductor layer 510 disposed on the first semiconductor layer 510, And a second nitride based second semiconductor layer (520).

The nitride-based transistor 30 may include a trench 530 that penetrates the second semiconductor layer 520 and reaches the inside of the first semiconductor layer 510. The nitride-based transistor 30 includes a first nitride-based third semiconductor layer 540 disposed along the inner wall of the trench 530 and disposed on the second semiconductor layer 520 outside the trench 530, a trench 530 A second insulating fourth nitride semiconductor layer 550 disposed on the third semiconductor layer 540 inside and outside the first semiconductor layer 550 and a gate electrode layer 560 disposed on the fourth semiconductor layer 550 . At this time, the third semiconductor layer 540 and the fourth semiconductor layer 550 may have different energy band gaps. Meanwhile, the second semiconductor layer 520 and the third semiconductor layer 540 may be a nitride-based semiconductor layer grown on the c-plane. A 2DEG layer may be formed in the interface region between the third semiconductor layer 540 and the fourth semiconductor layer 550 grown on the c-plane. For convenience of discussion, the y direction in FIG. 5A is set to a direction perpendicular to the c-plane, and the x direction is set to a direction parallel to the c-plane.

The nitride-based transistor 30 may include a high-concentration n-type doping pattern region 575 disposed inside the third and fourth semiconductor layers 540 and 550 in the lateral direction of the gate electrode layer 560. In addition, the nitride-based transistor 30 may include a source electrode layer 570 disposed on the n-type doping pattern region 575. The source electrode layer 570 can supply charge to the third semiconductor layer 540 through the n-type doping pattern region 575. [ The N-type doping pattern region 575 may be formed by selectively implanting an n-type dopant into the third semiconductor layer 540 and the fourth semiconductor layer 550.

The nitride-based transistor 30 includes a first n-type doped first nitride semiconductor layer 580 and a second n-type doped first nitride semiconductor layer 580 disposed on the lower surface of the first semiconductor layer 510, And a drain electrode layer 590 disposed thereon.

In one embodiment, the first and third semiconductor layers 510 and 540 are an n-type doped GaN layer, the second semiconductor layer 520 is a p-type doped GaN layer, AlGaN layer. The fifth semiconductor layer 580 may be a high concentration n-type doped GaN layer. The first to third semiconductor layers 510, 520, and 540, and the fifth semiconductor layer 580 may be a nitride-based material layer grown on the c-plane.

The source electrode layer 570 and the drain electrode layer 590 may include metals such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the source electrode layer 150 and the drain electrode layer 180 may have a structure in which an aluminum (Al) layer and a gold (Au) layer are sequentially stacked. The gate electrode 560 may include a metal such as nickel (Ni), gold (Au), titanium (Ti), and aluminum (Al) As a specific example, the gate electrode layer 130 may have a structure in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked.

In this embodiment, the fourth semiconductor layer 550 may function as a gate dielectric layer at the bottom of the gate electrode layer 560. As an example, when the fourth semiconductor layer 550 is an AlGaN layer, the AlGaN layer may not be intentionally doped. Alternatively, the AlGaN layer may be doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).

In the nitride-based transistor of this embodiment, the turn-off state can be maintained when a voltage less than the threshold voltage is applied to the gate electrode layer 560. At this time, a depletion layer Ad is formed at the interface between the second semiconductor layer 520 and the first and third semiconductor layers 510 and 540 by PN junction to fill the inside of the third semiconductor layer 540. In addition, a depletion layer Ad may be formed on a portion of the second semiconductor layer 520 and a portion of the first semiconductor layer 510 in contact with the second semiconductor layer 520.

On the other hand, the charges supplied from the source electrode layer 570 through the n-type doping pattern region 575 are trapped by the depletion layer Ad of the third semiconductor layer 540, so that the first and fifth semiconductor layers 510 and 580 The flow of charges toward the drain electrode layer 590 can be suppressed. That is, while the voltage lower than the threshold voltage is maintained in the gate electrode layer 560, the nitride-based transistor 30 can maintain the normally-off state.

Referring to FIG. 5B, in a nitride-based transistor, a turn-off state can be switched from a turn-off state to a turn-on state when an operation voltage equal to or higher than a threshold voltage is applied to the gate electrode layer 560. The depletion layer of the third semiconductor layer 540 is removed by the operation voltage, so that the third semiconductor layer can recover the charge conductivity. Specifically, as shown in FIG. 5B, at least the third semiconductor layer 540 under the gate electrode layer 560 can restore the charge conductivity by the n-type dopant.

In addition, a 2DEG layer can be formed in the interface region between the third semiconductor layer 540 and the fourth semiconductor layer 550 grown on the c-plane. As an example, when the GaN layer is grown on the c-plane, the Ga plane and the N plane may be alternately stacked, and spontaneous polarization due to polarization between the Ga plane and the N plane may occur. Further, when the GaN layer grown on the c-plane is bonded to the AlGaN layer, the 2DEG layer may be formed in the interface region due to the spontaneous polarization of the GaN layer or the piezoelectric polarization at the interface between the GaN and AlGaN layers.

5B, the side wall surface of the trench 530 may be perpendicular to the c-plane. That is, the sidewall surfaces of the trenches 530 may be parallel to the y-direction and perpendicular to the x-direction. Since the third semiconductor layer 540 located on the sidewall of the trench 530 is not grown on the c-plane, the 2DEG layer can not be formed at the interface with the fourth semiconductor layer 550.

The depletion layer Ad in the third semiconductor layer 540 located on the sidewall surface of the trench 530 is removed by the operating voltage applied to the gate electrode layer 560, The conductive channel (Ac) can be formed. Accordingly, the charges moved in the lateral direction along the source electrode layer 570, the n-type doping pattern region 575 and the 2DEG layer move in the vertical direction along the conductive channel Ac to form the first semiconductor layer 510, And reach the drain electrode layer 590 via the fifth semiconductor layer 580. [

As described above, in this embodiment, the nitride-based transistor can be manufactured using the first nitride-based third semiconductor layer 540 grown on the c-plane as the conductive layer. When the first nitride based third semiconductor layer 540 grows on the c-plane, the 2DEG layer can be formed in the interface region of the second nitride based semiconductor layer 550 having a different energy bandgap. In this embodiment, trenches 530 are formed in the first and second nitride-based first and second semiconductor layers 510 and 520, and the first nitride-based third semiconductor layer 510 is formed in a direction parallel to the sidewalls of the trench 530. [ Thereby forming a conductive channel (Ac) in the via hole (540). The direction parallel to the sidewalls of the trench 530 is perpendicular to the c-plane, and the polarization phenomenon can be suppressed at the interface between the first nitride based third semiconductor layer 540 and the second nitride based semiconductor layer 550 have. Accordingly, the formation of the 2DEG layer can be suppressed at the interface between the first nitride based third semiconductor layer 540 and the second nitride based semiconductor layer 550. As a result, when a voltage less than the threshold voltage is applied to the nitride-based transistor, the normally-off state can be effectively realized. In addition, at the time of the turn-on, the 2DEG layer is formed in the interface region of the first nitride based third semiconductor layer 540 and the second nitride based semiconductor layer 550 except for the channel Ac, thereby increasing the charge supply amount to the channel (Ac) So that the amount of current flowing through the channel Ac can be increased.

In some other embodiments, the sidewall surface of the trench 530 is not formed in a direction perpendicular to the bottom surface of the trench 530, but may be formed to be inclined at a predetermined angle. In this case, the direction parallel to the sidewalls of the trench 530 may not be perpendicular to the c-plane. Thus, the polarization phenomenon at the interface between the first nitride based third semiconductor layer 540 and the second nitride based semiconductor layer 550 may not be completely suppressed. As a result, the 2DEG layer may be locally formed at the interface between the first nitride based semiconductor layer 540 and the second nitride based semiconductor layer 550 disposed along the sidewalls of the trench 530. However, such a locally formed 2DEG layer can be controlled to be removed by the electric field formed between the second semiconductor layer 520 and the third semiconductor layer 540. [ Therefore, the normally-off state in the nitride-based transistor can be effectively maintained.

6 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the fourth embodiment of the present disclosure; Referring to FIG. 6, the nitride-based transistor 40 includes a gate dielectric layer 665 disposed between the fourth semiconductor layer 550 and the gate electrode layer 560, The structure of the nitride-based transistor 30 is substantially the same.

The gate dielectric layer 665 may comprise, by way of example, silicon oxide, silicon nitride, silicon oxynitride. The gate dielectric layer 665 can more reliably realize the conductive channel forming operation by the gate electrode layer 560 together with the fourth semiconductor layer 550. [

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the above teachings. It will be understood.

* Explanation of symbols

110: a nitride-based first semiconductor layer, 120: a second nitride-based second semiconductor layer

130: gate electrode layer 140: first nitride-based third semiconductor layer

141: first connection pattern layer 142: second connection pattern layer

150: source electrode layer 160: first nitride-based fourth semiconductor layer

170: first nitride-based fifth semiconductor layer 180: drain electrode layer

235: gate dielectric layer

305: drain electrode layer

310, 320, 330, 350: first nitride-based first to fourth material layers

340: first connection pattern layer 360: second nitride based fifth material layer

370: Trench 375: Second connection pattern layer

380: gate electrode layer 390: source electrode layer

440: connecting material layer 470: trench

510: first nitride based first semiconductor layer 520: first nitride based second semiconductor layer

530: trench 540: first nitride-based third semiconductor layer

550: first nitride-based fourth semiconductor layer 560: gate electrode layer

570: source electrode layer 580: first nitride-based fifth semiconductor layer

590: drain electrode layer 665: gate dielectric layer

Claims

an n-type doped first nitride based first semiconductor layer grown on an m-plane;

An insulating second nitride based second semiconductor layer disposed on the first semiconductor layer; And

And a gate electrode layer disposed on the second semiconductor layer,

Wherein the first semiconductor layer and the second semiconductor layer implement a normally-off having different energy band gaps.
The method according to claim 1,

A p-type doped first nitride based third semiconductor layer disposed in contact with the first semiconductor layer in a lateral direction of the gate electrode layer; And

Further comprising a source electrode layer disposed on the third semiconductor layer.
3. The method of claim 2,

Wherein the source electrode layer is electrically connected to the first semiconductor layer and the third semiconductor layer.
3. The method of claim 2,

The first semiconductor layer is an n-type doped GaN layer,

The second semiconductor layer is an AlGaN layer,

Wherein the third semiconductor layer is a p-type doped GaN layer that implements normally-off.
The method according to claim 1,

Wherein the AlGaN layer is an insulating nitride-based semiconductor layer that is not intentionally doped.
The method according to claim 1,

Wherein the AlGaN layer is an insulating nitride-based semiconductor layer doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).
3. The method of claim 2,

An n-type doped first nitride based fourth semiconductor layer disposed on a lower surface of the first semiconductor layer and the third semiconductor layer;

A first n-type doped first nitride based fifth semiconductor layer disposed on a lower surface of the fourth semiconductor layer; And

Further comprising a drain electrode layer disposed on a lower surface of the fifth semiconductor layer.
8. The method of claim 7,

Wherein the fourth semiconductor layer and the fifth semiconductor layer are nitride-based semiconductor layers grown in an m-plane.
The method according to claim 1,

Off state in which a depletion layer formed by a PN junction at an interface between the first semiconductor layer and the third semiconductor layer is filled in the first semiconductor layer when the first semiconductor layer and the second semiconductor layer are turned off.
10. The method of claim 9,

Off state in which the depletion layer under the gate electrode layer is removed by an operation voltage applied to the gate electrode layer in a turn-on state to restore the charge conductivity of the first semiconductor layer.
The method according to claim 1,

Further comprising a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer.
an n-type doped first nitride based first semiconductor layer grown on a c-plane;

A p-type doped first nitride based second semiconductor layer disposed on the first semiconductor layer;

A first nitride based third semiconductor layer disposed along the inner wall of the trench passing through the second semiconductor layer to reach the inside of the first semiconductor layer and disposed on the second semiconductor layer outside the trench;

An insulating second nitride-based fourth semiconductor layer disposed on the third semiconductor layer inside and outside the trench; And

And a gate electrode layer disposed on the fourth semiconductor layer,

And wherein the third semiconductor layer and the fourth semiconductor layer implement a normally-off having different energy band gaps.
13. The method of claim 12,

A high concentration n-type doping pattern region disposed inside the third and fourth semiconductor layers in a lateral direction of the gate electrode layer; And

And a source electrode layer disposed on the n-type doping pattern region.
13. The method of claim 12,

And a 2DEG layer disposed in an interface region between the third semiconductor layer and the fourth semiconductor layer,

Wherein the 2DEG layer implements a normally-off suppression at an interface parallel to the sidewall surface of the trench.
13. The method of claim 12,

Wherein the first and third semiconductor layers are n-type doped GaN layers,

The second semiconductor layer is a p-type doped GaN layer,

Wherein the fourth semiconductor layer is an AlGaN layer that implements normally-off.
16. The method of claim 15,

Wherein the AlGaN layer is an insulating nitride-based semiconductor layer that is not intentionally doped.
16. The method of claim 15,

Wherein the AlGaN layer is an insulating nitride-based semiconductor layer doped with at least one of iron (Fe), carbon (C), and magnesium (Mg).
13. The method of claim 12,

A first n-type doped first nitride based fifth semiconductor layer disposed on a lower surface of the first semiconductor layer; And

Further comprising a drain electrode layer disposed on a lower surface of the fifth semiconductor layer.
19. The method of claim 18,

And the fifth semiconductor layer is a nitride-based semiconductor layer grown in a c-plane.
13. The method of claim 12,

A depletion layer formed by the PN junction at the interface between the second semiconductor layer and the third semiconductor layer in the turn-off state realizes a normally-off state filling at least the inside of the third semiconductor layer in contact with the gate electrode layer Nitride type transistor.
13. The method of claim 12,

Off state in which the depletion layer is removed and the charge conductivity of the third semiconductor layer is restored by an operation voltage applied to the gate electrode layer when the semiconductor substrate is turned on.
13. The method of claim 12,

Further comprising a gate dielectric layer disposed between the fourth semiconductor layer and the gate electrode layer.