KR20170000612A - nitride-based transistor having normally-off state - Google Patents
nitride-based transistor having normally-off state Download PDFInfo
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- KR20170000612A KR20170000612A KR1020150089752A KR20150089752A KR20170000612A KR 20170000612 A KR20170000612 A KR 20170000612A KR 1020150089752 A KR1020150089752 A KR 1020150089752A KR 20150089752 A KR20150089752 A KR 20150089752A KR 20170000612 A KR20170000612 A KR 20170000612A
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 186
- 239000004065 semiconductor Substances 0.000 claims abstract description 241
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910002704 AlGaN Inorganic materials 0.000 claims description 23
- 239000011777 magnesium Substances 0.000 claims description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 7
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 229910052749 magnesium Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 description 79
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 60
- 239000010931 gold Substances 0.000 description 52
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 26
- 229910052737 gold Inorganic materials 0.000 description 26
- 229910002601 GaN Inorganic materials 0.000 description 23
- 229910052759 nickel Inorganic materials 0.000 description 20
- 239000010936 titanium Substances 0.000 description 20
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 230000010287 polarization Effects 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000002269 spontaneous effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000011575 calcium Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
Description
This disclosure relates generally to nitride-based transistors, and more particularly to nitride-based transistors that implement a normally-off.
BACKGROUND ART [0002] With the development of information and communication technologies, there is an increasing demand for high-voltage transistors operating in a high-speed switching environment or a high-voltage environment. Therefore, a gallium nitride transistor using a recently developed III-V semiconductor material is capable of high-speed switching operation as compared with a conventional silicon transistor, and is suitable not only for ultra-high speed signal processing but also for high voltage It has attracted the attention of the industry due to its applicability.
Such a gallium nitride-based transistor can be manufactured in a horizontal structure or a vertical structure. The horizontal structure means a structure in which the charge conduction from the source electrode layer to the drain electrode layer is formed in the lateral direction and generally has a structure in which the source electrode layer, the gate electrode layer, and the drain electrode layer are disposed on the same surface of the substrate .
Unlike the above-described horizontal structure, a vertical structure recently appeared means a structure in which charge conduction from the source electrode layer to the drain electrode layer is made in the vertical direction, and the structure disclosed in U.S. Patent Publication No. 2012-0319127 A Current Aperture Vertical Electron Transistor (CAVET) can be presented as an example. According to the CAVET, the source electrode layer and the drain electrode layer are arranged to face each other in the vertical direction, and a p-type gallium nitride (p-GaN) layer is disposed as a current barrier layer therebetween. Then, the current flows vertically from the source electrode layer to the drain electrode layer through the aperture provided by the p-type gallium nitride (p-GaN) layer.
On the other hand, in order to commercialize the above-described horizontal and vertical structures, there is still a demand for a technique for securing reliability in an on-off switching operation through a channel layer.
Embodiments of the present disclosure provide a structure of a nitride-based transistor that reliably implements a normally-off state.
The embodiment of the present disclosure provides a structure of a nitride-based transistor capable of improving the electric conductivity of a channel layer at the time of turning on.
A nitride-based transistor implementing a normally-off according to one aspect includes: an n-type doped first nitride based first semiconductor layer grown on an m-plane; An insulating second nitride based second semiconductor layer disposed on the first semiconductor layer; And a gate electrode layer disposed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer have different energy band gaps.
A nitride-based transistor implementing a normally-off according to another aspect comprises: an n-type doped first nitride based first semiconductor layer grown on a c-plane; A p-type doped first nitride based second semiconductor layer disposed on the first semiconductor layer; A first nitride based third semiconductor layer disposed along the inner wall of the trench passing through the second semiconductor layer to reach the inside of the first semiconductor layer and disposed on the second semiconductor layer outside the trench; An insulating second nitride-based fourth semiconductor layer disposed on the third semiconductor layer inside and outside the trench; And a gate electrode layer disposed on the fourth semiconductor layer. The third semiconductor layer and the fourth semiconductor layer have different energy band gaps.
According to one embodiment of the present disclosure, a nitride-based transistor can be manufactured using the first nitride-based semiconductor layer grown on the m-plane as a conductive layer. When the first nitride semiconductor layer is grown on the m-plane, spontaneous polarization in the first nitride semiconductor layer can be suppressed. As a result, formation of a charge high-conductivity layer such as a 2DEG layer due to various polarization phenomena can be effectively suppressed in the junction interface region with the second nitride-based semiconductor layer having different energy bandgaps. Thus, in the nitride-based transistor, the normally-off state can be effectively realized.
According to one embodiment of the present disclosure, a nitride-based transistor can be manufactured using the first nitride-based semiconductor layer grown on the c-plane as a conductive layer. When the first nitride-based semiconductor layer is grown on the c-plane, the 2DEG layer can be formed in the junction interface region with the second nitride-based semiconductor layer having a different energy bandgap. On the other hand, in this embodiment, a trench can be formed in the first nitride based semiconductor layer and a channel layer can be formed in the first nitride based semiconductor layer in a direction parallel to the side wall of the trench. The direction parallel to the sidewalls of the trench is perpendicular to the c-plane, and polarization can be suppressed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer. Thus, the formation of the 2DEG layer can be suppressed. As a result, in the nitride-based transistor, the normally-off state can be effectively realized. In addition, a 2DEG layer is formed in the interface region of the first and second nitride based semiconductor layers except the channel layer at the time of turning on, thereby increasing the amount of charge supplied to the channel layer and increasing the amount of current flowing through the channel layer .
The effects of the disclosed techniques described above are to illustrate any of the various effects derived from the configuration of one embodiment of the present disclosure and not to preclude other various effects that may be apparently derived from the configuration of the presented embodiments.
1 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the first embodiment of the present disclosure;
2 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to a second embodiment of the present disclosure;
3A-3F are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to one embodiment of the present disclosure.
4A through 4H are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to another embodiment of the present disclosure.
5A and 5B are cross-sectional views schematically illustrating a nitride-based transistor implementing a normally-off according to a third embodiment of the present disclosure.
6 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the fourth embodiment of the present disclosure;
Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device.
Where an element is referred to herein as being located on another element "above" or "below", it is to be understood that the element is directly on the other element "above" or "below" It means that it can be intervened. In this specification, the terms 'upper' and 'lower' are relative concepts set at the observer's viewpoint. When the viewer's viewpoint is changed, 'upper' may mean 'lower', and 'lower' It may mean.
Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
In this specification, the source electrode layer and the drain electrode layer are referred to for convenience in consideration of the direction of current. When the direction of current changes due to a change in the applied voltage polarity, the source electrode layer becomes a drain electrode layer, It may mean an electrode layer.
In this specification, the interfacial region between one thin film layer and another thin film layer is interpreted to include not only the interface between one thin film layer and another thin film layer but also an inner region of a predetermined depth from the surface of one thin film layer or another thin film layer adjacent to the interface .
In this specification, the nitride-based semiconductor layer or the nitride-based material layer may include a nitride such as Al x In y Ga 1-xy N (0? X? 1, 0? Y? The nitride-based semiconductor layer or the nitride-based material layer may be formed by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MIB), hydride vapor phase epitaxy ) Can be used to form the epitaxial film. The method of forming the epitaxial layer may be performed at a temperature of 1000 ° C to 1100 ° C as an example.
In this specification, the n-type or p-type doping implies that the n-type dopant is doped into the nitride-based semiconductor layer or the nitride-based material layer by about 1E16 / cm 3 or more and the p-type dopant is doped with 1E17 / cm 3 or more can do. Also, the expression 'doping with a high concentration of n-type' means that the n-type dopant is doped into the nitride-based semiconductor at a concentration of about 1E19 / cm 3 or more.
In this specification, when doping the nitride-based semiconductor layer into n-type or p-type, for example, when doping to the n-type, silicon (Si), germanium (Ge), selenium (Se), tellurium Te, etc. may be applied. When doping to p-type, beryllium (Be), magnesium (Mg), calcium (Ca), carbon (C), iron (Fe), manganese can do.
In this specification, the nitride based semiconductor layer can grow on the c-plane or the m-plane. In one example, when the nitride-based semiconductor layer is a GaN layer and the GaN layer is grown on the c-plane, the GaN layer is alternately stacked along the height direction (i.e., the direction perpendicular to the c- . ≪ / RTI > The m-plane may mean a plane substantially perpendicular to the c-plane. For example, when grown in the height direction on the m-plane, a unit GaN layer in which Ga and N coexist is stacked in a multilayer structure .
1 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the first embodiment of the present disclosure; 1, the nitride-based
The nitride-based
The nitride-based
Referring again to FIG. 1, the first
Referring again to FIG. 1, a second
As a result, when a voltage is applied to the
In one embodiment, the
In addition, the
The first
The
In this embodiment, the
In the nitride-based transistor of this embodiment, a depletion layer formed by the PN junction at the interface between the
When an operation voltage equal to or higher than the threshold voltage is applied to the
In this embodiment, a nitride semiconductor layer having a different energy band gap from the
In this embodiment, the first nitride based
2 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to a second embodiment of the present disclosure; Referring to FIG. 2, the nitride-based
The
3A-3F are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to one embodiment of the present disclosure. Referring to FIG. 3A, a high concentration n-type doped first nitride based
Next, a first nitride based
Referring to FIG. 3B, the
Referring to FIG. 3C, an n-type doped first nitride based
In one embodiment, the first nitride based first to fourth material layers 310, 320, 330, 350 may be a GaN layer and the second nitride based
Referring to FIG. 3D, a
Referring to FIG. 3E, a second
Next, a
Referring to FIG. 3F, a
On the other hand, a
By proceeding with the above-described manufacturing method, a nitride-based transistor implementing the normally-off can be manufactured. As an example, the manufacturing method of Figs. 3A to 3F can be applied to the manufacturing method of the nitride-based
Although not shown, in some embodiments, between the
4A through 4H are cross-sectional views schematically illustrating a method of manufacturing a nitride-based transistor implementing a normally-off according to another embodiment of the present disclosure. Referring to FIG. 4A, a high concentration n-type doped first nitride based
Next, a first nitride based
Referring to FIG. 4B, the
Referring to FIG. 4C, the
Referring to FIG. 4D, a first nitride based
Referring to FIG. 4E, a second nitride based
In one embodiment, the first to fourth material layers 310, 320, 330, 350 and the nitride based connecting layer may be a GaN layer and the
4F, a
Referring to FIG. 4G, a second
Referring to FIG. 4H, a
Further, a
Referring again to FIG. 4H, a
By proceeding with the above-described manufacturing method, a nitride-based transistor implementing the normally-off can be manufactured. As an example, the manufacturing method of Figs. 4A to 4H can be applied to the manufacturing method of the nitride-based
5A and 5B are cross-sectional views schematically illustrating a nitride-based transistor implementing a normally-off according to a third embodiment of the present disclosure. Specifically, FIG. 5A schematically shows the turn-off state of the nitride-based
5A, the nitride-based
The nitride-based
The nitride-based
The nitride-based
In one embodiment, the first and third semiconductor layers 510 and 540 are an n-type doped GaN layer, the
The
In this embodiment, the
In the nitride-based transistor of this embodiment, the turn-off state can be maintained when a voltage less than the threshold voltage is applied to the
On the other hand, the charges supplied from the
Referring to FIG. 5B, in a nitride-based transistor, a turn-off state can be switched from a turn-off state to a turn-on state when an operation voltage equal to or higher than a threshold voltage is applied to the
In addition, a 2DEG layer can be formed in the interface region between the
5B, the side wall surface of the
The depletion layer Ad in the
As described above, in this embodiment, the nitride-based transistor can be manufactured using the first nitride-based
In some other embodiments, the sidewall surface of the
6 is a cross-sectional view schematically showing a nitride-based transistor implementing a normally-off according to the fourth embodiment of the present disclosure; Referring to FIG. 6, the nitride-based
The
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the above teachings. It can be understood that.
110: a nitride-based first semiconductor layer, 120: a second nitride-based second semiconductor layer,
130: gate electrode layer, 140: first nitride based third semiconductor layer,
141: first connection pattern layer, 142: second connection pattern layer,
150: source electrode layer, 160: first nitride-based fourth semiconductor layer,
170: a first nitride-based fifth semiconductor layer, 180: a drain electrode layer,
235: gate dielectric layer,
305: drain electrode layer, 310, 320, 330, 350: first nitride based first to fourth material layers,
340: first connection pattern layer, 360: second nitride based fifth material layer,
370: trench, 375: second connection pattern layer,
380: gate electrode layer, 390: source electrode layer,
440: connecting material layer, 470: trench,
510: first nitride based first semiconductor layer, 520: first nitride based second semiconductor layer,
530: trench, 540: first nitride-based third semiconductor layer,
550: first nitride based fourth semiconductor layer, 560: gate electrode layer,
570: source electrode layer, 580: first nitride-based fifth semiconductor layer,
590: drain electrode layer, 665: gate dielectric layer.
Claims (22)
An insulating second nitride based second semiconductor layer disposed on the first semiconductor layer; And
And a gate electrode layer disposed on the second semiconductor layer,
Wherein the first semiconductor layer and the second semiconductor layer have different energy band gaps
A nitride-based transistor that implements normally-off.
A p-type doped first nitride based third semiconductor layer disposed in contact with the first semiconductor layer in a lateral direction of the gate electrode layer; And
And a source electrode layer disposed on the third semiconductor layer
A nitride-based transistor that implements normally-off.
And the source electrode layer is electrically connected to the first semiconductor layer and the third semiconductor layer
A nitride-based transistor that implements normally-off.
The first semiconductor layer is an n-type doped GaN layer,
The second semiconductor layer is an AlGaN layer,
The third semiconductor layer is a p-type doped GaN layer
A nitride-based transistor that implements normally-off.
The AlGaN layer is an insulating nitride-based semiconductor layer which is not intentionally doped
A nitride-based transistor that implements normally-off.
The AlGaN layer is an insulating nitride-based semiconductor layer doped with at least one of iron (Fe), carbon (C), and magnesium (Mg)
A nitride-based transistor that implements normally-off.
An n-type doped first nitride based fourth semiconductor layer disposed on a lower surface of the first semiconductor layer and the third semiconductor layer;
A first n-type doped first nitride based fifth semiconductor layer disposed on a lower surface of the fourth semiconductor layer; And
And a drain electrode layer disposed on a lower surface of the fifth semiconductor layer
A nitride-based transistor that implements normally-off.
The fourth semiconductor layer and the fifth semiconductor layer are nitride-based semiconductor layers grown in the m-plane
A nitride-based transistor that implements normally-off.
A depletion layer formed by a PN junction at the interface between the first semiconductor layer and the third semiconductor layer in the turn-off state fills the inside of the first semiconductor layer
A nitride-based transistor that implements normally-off.
The depletion layer under the gate electrode layer is removed by the operation voltage applied to the gate electrode layer in the turn-on state to recover the charge conductivity of the first semiconductor layer
A nitride-based transistor that implements normally-off.
And a gate dielectric layer disposed between the second semiconductor layer and the gate electrode layer
A nitride-based transistor that implements normally-off.
A p-type doped first nitride based second semiconductor layer disposed on the first semiconductor layer;
A first nitride based third semiconductor layer disposed along the inner wall of the trench passing through the second semiconductor layer to reach the inside of the first semiconductor layer and disposed on the second semiconductor layer outside the trench;
An insulating second nitride-based fourth semiconductor layer disposed on the third semiconductor layer inside and outside the trench; And
And a gate electrode layer disposed on the fourth semiconductor layer,
Wherein the third semiconductor layer and the fourth semiconductor layer have different energy band gaps
A nitride-based transistor that implements normally-off.
A high concentration n-type doping pattern region disposed inside the third and fourth semiconductor layers in a lateral direction of the gate electrode layer; And
And a source electrode layer disposed on the n-type doping pattern region
A nitride-based transistor that implements normally-off.
And a 2DEG layer disposed in an interface region between the third semiconductor layer and the fourth semiconductor layer,
The 2DEG layer is suppressed on the interface parallel to the sidewall surface of the trench
A nitride-based transistor that implements normally-off.
Wherein the first and third semiconductor layers are n-type doped GaN layers,
The second semiconductor layer is a p-type doped GaN layer,
The fourth semiconductor layer is an AlGaN layer
A nitride-based transistor that implements normally-off.
The AlGaN layer is an insulating nitride-based semiconductor layer which is not intentionally doped
A nitride-based transistor that implements normally-off.
The AlGaN layer is an insulating nitride-based semiconductor layer doped with at least one of iron (Fe), carbon (C), and magnesium (Mg)
A nitride-based transistor that implements normally-off.
A first n-type doped first nitride based fifth semiconductor layer disposed on a lower surface of the first semiconductor layer; And
And a drain electrode layer disposed on a lower surface of the fifth semiconductor layer
A nitride-based transistor that implements normally-off.
The fifth semiconductor layer is a nitride semiconductor layer grown in a c-plane
A nitride-based transistor that implements normally-off.
A depletion layer formed by a PN junction at an interface between the second semiconductor layer and the third semiconductor layer in a turn-off state is formed in at least the third semiconductor layer in contact with the gate electrode layer
A nitride-based transistor that implements normally-off.
The depletion layer is removed by the operation voltage applied to the gate electrode layer in the turn-on state to restore the charge conductivity of the third semiconductor layer
A nitride-based transistor that implements normally-off.
And a gate dielectric layer disposed between the fourth semiconductor layer and the gate electrode layer
A nitride-based transistor that implements normally-off.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020150089752A KR20170000612A (en) | 2015-06-24 | 2015-06-24 | nitride-based transistor having normally-off state |
PCT/KR2016/004501 WO2016208864A1 (en) | 2015-06-24 | 2016-05-12 | Nitride-based transistor for implementing normally-off |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020150089752A KR20170000612A (en) | 2015-06-24 | 2015-06-24 | nitride-based transistor having normally-off state |
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KR20170000612A true KR20170000612A (en) | 2017-01-03 |
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WO (1) | WO2016208864A1 (en) |
Family Cites Families (5)
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JP2008311533A (en) * | 2007-06-15 | 2008-12-25 | Rohm Co Ltd | High electron mobility transistor |
JP5693831B2 (en) * | 2008-08-15 | 2015-04-01 | トヨタ自動車株式会社 | Transistor |
JP5529595B2 (en) * | 2009-07-30 | 2014-06-25 | 住友電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP5299208B2 (en) * | 2009-10-09 | 2013-09-25 | 住友電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP6069688B2 (en) * | 2012-06-18 | 2017-02-01 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
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