CN114141870A - III-nitride semiconductor high electron mobility transistor with enhanced reliability and manufacturing method thereof - Google Patents
III-nitride semiconductor high electron mobility transistor with enhanced reliability and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a drain electrode, a p-type doped nitride semiconductor layer, a first surface reinforcing layer, and a gate electrode. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The source electrode and the drain electrode are provided on the second nitride semiconductor layer. The p-type doped nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first surface reinforcing layer is disposed on the p-type doped nitride semiconductor layer, and the p-type doped nitride semiconductor layer and the first surface reinforcing layer have the same group III element. The first surface reinforcing layer also contains oxygen element, and the oxygen element and the III group element form bonding in the first surface reinforcing layer. A gate window is defined between the gate electrode and the first surface reinforcing layer, and the width of the gate window is smaller than or equal to the width of the p-type doped nitride semiconductor layer.
Description
Technical Field
The present invention generally relates to a semiconductor device. Still further, the present invention relates to a high electron mobility transistor device having a p-type doped group III-V compound layer with a reinforcement layer provided on a surface (and/or a surface of a barrier layer) of the p-type doped group III-V compound layer to improve reliability of the device.
Background
In recent years, gallium nitride based transistors have become an attractive high power device due to their high breakdown voltage, fast switching speed and low on-resistance, with High Electron Mobility Transistors (HEMTs) exhibiting particularly superior characteristics. In gallium nitride based HEMTs, it is common to have a barrier layer and a channel layer composed of two group III-V compounds of different band gaps, such as aluminum gallium nitride/gallium nitride HEMTs, which are one type of heterojunction device. In such a structure, a quantum well structure capable of accommodating electrons may be formed at the interface due to the band gap structure of the barrier layer (e.g., aluminum gallium nitride layer)/channel layer (e.g., gallium nitride layer) discontinuity. Meanwhile, due to the polarization characteristic of the III-V group compound, high-concentration two-dimensional electron gas can be generated in the quantum well, the two-dimensional electron gas generally has high mobility, and the gallium nitride HEMT can use the two-dimensional electron gas as a conducting channel. The high conductivity of the two-dimensional electron gas combined with the high voltage withstand capability of the gallium nitride material makes GaN-based HEMTs very suitable for high power/high frequency applications.
Nowadays, gan-based hemts have become key components in high power, high efficiency power conversion systems. With the increasing commercialization of gallium nitride-based high electron mobility transistors, the reliability of the device becomes a critical issue. For example, during operation, the high electric fields present in the device can seriously threaten the reliability of the device over long periods of operation. The carriers move in a high electric field to gradually obtain kinetic energy and are accelerated to become high-energy carriers, when the high-energy carriers reach the surface or interface of the device, the high-energy carriers bombard the surface to release energy to crystal lattices, and the bombardment of the high-energy carriers generates defects in the device, so that the performance of the device is reduced, and the service life of the device is shortened. Therefore, there is a need in the art for a new high electron mobility transistor structure or fabrication technique to enhance its resistance to high energy carrier bombardment, thereby improving device performance and its useful life.
Disclosure of Invention
According to an embodiment of the present invention, there is provided a semiconductor device characterized by including a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a drain electrode, a p-type doped nitride semiconductor layer, a first surface reinforcing layer, and a gate electrode. The first nitride semiconductor layer has a first band gap. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a second band gap, and the second band gap is greater than the first band gap. The source electrode is provided on the second nitride semiconductor layer or on the first nitride semiconductor layer. The drain electrode is provided on the second nitride semiconductor layer or on the first nitride semiconductor layer. The p-type doped nitride semiconductor layer is disposed on the second nitride semiconductor layer and between the gate electrode and the drain electrode. The first surface reinforcing layer is arranged on the p-type doped nitride semiconductor layer, the p-type doped nitride semiconductor layer and the first surface reinforcing layer have the same III group elements, and the first surface reinforcing layer also has oxygen elements which form bonding with the III group elements in the first surface reinforcing layer. The grid electrode is arranged on the first surface reinforcing layer and is positioned between the source electrode and the drain electrode, a grid window is defined between the grid electrode and the first surface reinforcing layer, and the width of the grid window is smaller than that of the p-type doped nitride semiconductor layer or is consistent with that of the p-type doped nitride semiconductor layer.
In some embodiments, the p-type doped nitride semiconductor layer and the first surface reinforcing layer contact each other to form an interface, and the p-type doped nitride semiconductor layer and the first surface reinforcing layer are connected to each other by an interatomic bond.
In some embodiments, the semiconductor device further comprises a dielectric layer. The dielectric layer is disposed on the second nitride semiconductor layer, wherein the gate electrode penetrates through the dielectric layer to define a gate window in the dielectric layer.
In some embodiments, the gate window coincides with a width of the gate electrode.
In some embodiments, the first surface reinforcing layer completely covers the upper surface of the p-type doped nitride semiconductor layer directly and extends down the sidewalls of the p-type doped nitride semiconductor layer.
In some embodiments, the thickness of the first surface reinforcing layer is between 1 nm and 20 nm.
In some embodiments, the semiconductor device further comprises a second surface reinforcing layer. The second surface reinforcing layer is arranged between the second nitride semiconductor layer and the source electrode and between the second nitride semiconductor layer and the drain electrode, the second nitride semiconductor layer and the second surface reinforcing layer have the same III-group element, the second surface reinforcing layer also has oxygen element, and the oxygen element and the III-group element form bonding in the second surface reinforcing layer.
In some embodiments, the p-type doped nitride semiconductor layer is a p-type gallium nitride layer and the first surface reinforcing layer is a gallium oxynitride layer.
According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, characterized by the following sub-step. A second nitride semiconductor layer is formed on the first nitride semiconductor layer. A p-type doped nitride semiconductor cap layer is formed on the second nitride semiconductor layer. And carrying out oxidation treatment and high-temperature annealing on the upper surface of the p-type doped nitride semiconductor cap layer to form a first surface reinforcing layer. And removing a part of the p-type doped nitride semiconductor cap layer and a part of the surface reinforcing layer to form the p-type doped nitride semiconductor layer and the surface reinforcing layer. A second surface reinforcing layer is formed on the second nitride semiconductor layer. A dielectric layer is formed to cover the second nitride semiconductor layer and the p-type doped nitride semiconductor layer. A source electrode and a drain electrode are formed, which pass through the dielectric layer and contact the second nitride semiconductor layer or the first nitride semiconductor layer. A portion of the dielectric layer is removed to expose the first surface stiffener layer. And forming a gate electrode on the dielectric layer so that the gate electrode extends to the first surface reinforcing layer contact.
In some embodiments, the first surface reinforcing layer is formed on the p-type doped nitride semiconductor cap layer or the second nitride semiconductor layer, or both.
In some embodiments, the first surface reinforcing layer comprises gallium oxide, gallium oxynitride, aluminum gallium oxynitride or combinations thereof.
In some embodiments, the first surface reinforcing layer is formed by deposition.
In some embodiments, the first surface reinforcing layer is formed by oxidation and subsequent high temperature annealing.
In some embodiments, the oxidation is exposure of the device surface to an oxygen-containing plasma or an oxygen-containing gas.
In some embodiments, wherein the high temperature annealing comprises annealing at a temperature in a range of 500 ℃ to 1000 ℃.
In some embodiments, the high temperature annealing is performed in a nitrogen or ammonia environment.
According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, characterized by the following sub-step. A second nitride semiconductor layer is formed on the first nitride semiconductor layer. A p-type doped nitride semiconductor cap layer is formed on the second nitride semiconductor layer. And carrying out oxidation treatment and high-temperature annealing on the upper surface of the p-type doped nitride semiconductor cap layer to form a surface reinforcing layer. And forming a gate electrode on the surface reinforcing layer. And removing a part of the p-type doped nitride semiconductor cap layer and a part of the surface reinforcing layer through a self-alignment process of the gate electrode to form the p-type doped nitride semiconductor layer and the first surface reinforcing layer. And a grid window is defined between the grid electrode and the first surface reinforcing layer, and the width of the grid window, the width of the grid electrode and the width of the first surface reinforcing layer are consistent. A second surface reinforcing layer is formed on the second nitride semiconductor layer. A dielectric layer is formed to cover the second nitride semiconductor layer and the p-type doped nitride semiconductor layer. A source electrode and a drain electrode are formed, which pass through the dielectric layer and contact the second nitride semiconductor layer or the first nitride semiconductor layer.
By applying the above configuration, the first surface reinforcing layer can be formed as a gallium-oxygen-nitrogen layer, which can improve the resistance of the gate electrode to bombardment by high-energy carriers, thereby weakening the surface/interface degradation occurring between the gate electrode and the p-type doped nitride semiconductor layer. Therefore, the gate breakdown voltage can be increased, the gate leakage current can be inhibited, the stability and the reliability of the device can be improved, and the service life of the device can be prolonged.
Drawings
The present invention can be readily understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Some embodiments of the invention are described in more detail below with reference to the accompanying drawings, in which:
fig. 1 is a cross-sectional view showing a semiconductor device according to some embodiments of the present invention.
Fig. 2A to 2C are schematic views illustrating a surface of a p-type doped nitride semiconductor cap layer is converted into a first surface reinforcing layer according to some embodiments of the present invention.
Fig. 3A and 3B are surface morphologies before and after modification, respectively, which were characterized by atomic force microscopy. Fig. 3C shows the oxygen penetration depth before and after modification, as measured by secondary ion mass spectrometry.
Fig. 4 is a graph showing the relationship between gate-source voltage and gate current for the unmodified and modified transistors.
FIG. 5 is a Weibull plot of the breakdown time distribution without modification and after modification and a lifetime prediction plot thereof.
Fig. 6 is a flow chart illustrating a semiconductor device fabrication process according to some embodiments of the present invention.
Fig. 7A-7H are schematic diagrams of various stages in the manufacture of a semiconductor device according to some embodiments of the present invention.
Fig. 8 is a cross-sectional view of a semiconductor device according to a portion of an embodiment of the present invention.
Fig. 9 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.
Fig. 10 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.
Detailed Description
Embodiments of the present invention will be more readily understood by the following detailed description in conjunction with the accompanying drawings. In the description of the present invention, terms such as "upper", "lower", "above", "left", "right", "below", "one side", "over", "under", and the like, which are relative to each other, are used for illustrative purposes only, and practical embodiments may be arranged in any direction or manner in a space, which is used for describing the positional relationship between two or more components, and is not used to limit the embodiments of the present invention. Those skilled in the art will appreciate that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the present invention. In the present invention, some specific details are omitted to avoid ambiguity; the present invention is intended to enable those skilled in the art to practice the teachings of the present invention without undue experimentation.
Fig. 1 is a cross-sectional view of a semiconductor device 100A according to some embodiments of the present invention. The semiconductor device 100A includes a substrate 110, a buffer layer 112, a first nitride semiconductor layer 120, a second nitride semiconductor layer 122, a p-type doped nitride semiconductor layer 130, a first surface reinforcing layer 132, a dielectric layer 140, a source electrode 142, a drain electrode 144, a gate electrode 150, and a connection metal 160.
The material selected for substrate 110 may include silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-doped silicon (p-doped Si), n-doped silicon (n-doped Si), sapphire (sapphire), diamond, aluminum nitride (AlN), gallium nitride (GaN), a semiconductor layer overlying an insulator layer, such as a Silicon On Insulator (SOI), or other suitable semiconductor material. In some embodiments, the semiconductor material may include a group iii element, a group iv element, a group v element, or combinations thereof. In some other embodiments, the substrate 110 may also include one or more doped regions, buried layers, epitaxial layers, or combinations thereof.
A buffer layer 112 is disposed on the substrate 110. The buffer layer 112 may be made of a nitride or a III-V compound, such as gallium nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN) alloy, or a combination thereof. The buffer layer 112 may serve to reduce lattice mismatch and thermal mismatch between the substrate 110 and a layer subsequently formed on the buffer layer 112 (e.g., epitaxially formed thereon), thereby suppressing defects due to the mismatch. By the buffer layer 112, the occurrence of dislocations and defects can be reduced. The buffer layer may be a single layer or a multilayer of the same or different composition and may also be deposited using the same material under different conditions. In some embodiments, the semiconductor device 100A may further include a nucleation layer (and/or a transition layer) that may be disposed between the substrate 110 and the buffer layer 112 to further reduce the occurrence of dislocations and defects. The nucleation layer may also be made of nitride or a group III-V compound, such as gallium nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), an alloy, or a combination thereof.
The first nitride semiconductor layer 120 is disposed on the buffer layer 112. The material selected for the first nitride semiconductor layer 120 may include nitride or III-V compound, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (In)xAlyGa(1–x–y)N, where x + y is less than or equal to 1), AlGaN (Al)yGa(1–y)N, wherein y is less than or equal to 1). The second nitride semiconductor layer 122 is disposed on the first nitride semiconductor layer 120. The material selected for the second nitride semiconductor layer 122 may include nitride or III-V compound, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (In)xAlyGa(1–x–y)N, where x + y is less than or equal to 1), AlGaN (Al)yGa(1–y)N, wherein y is less than or equal to 1). The first nitride semiconductor layer 120 and the second nitride semiconductor layer 122 may have a single-layer structure or a composite layer structure. In the embodiment where the first nitride semiconductor layer 120 or the second nitride semiconductor layer 122 is a composite layer structure, the selected material may be a combination of the above materials.
The first nitride semiconductor layer 120 has a first band gap (bandgap), and the second nitride semiconductor layer 122 has a second band gap. The materials of the first nitride semiconductor layer 120 and the second nitride semiconductor layer 122 may be selectively selected so that the second band gap of the second nitride semiconductor layer 122 is greater than the first band gap of the first nitride semiconductor layer 120. . For example, when the material of the first nitride semiconductor layer 120 is selected to be a GaN layer and it has a band gap of about 3.4ev, the material of the second nitride semiconductor layer 122 may be selected to be an AlGaN layer and it has a band gap of about 4.0 ev. The first nitride semiconductor layer 120 and the second nitride semiconductor layer 122 may function as a channel layer and a barrier layer, respectively. A triangular potential well is created at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular potential well, thereby creating a two-dimensional electron gas (2 DEG) region 124 at the interface. Therefore, the semiconductor device 100A can be used as a High Electron Mobility Transistor (HEMT).
The source electrode 142 and the drain electrode 144 may be disposed on the second nitride semiconductor layer 122 or the first nitride semiconductor layer 120. The source electrode 142 and the drain electrode 144 may be formed of a selected material, such as a metal, an alloy, a doped semiconductor material (e.g., doped crystalline silicon), other conductive material, or a combination thereof. The p-type doped nitride semiconductor layer 130 is disposed on the second nitride semiconductor layer 122, and the gate electrode 150 is disposed on the p-type doped nitride semiconductor layer 130. The p-type doped nitride semiconductor layer 130 and the gate electrode 150 are located between the source electrode 142 and the drain electrode 144. The p-type doped nitride semiconductor layer 130 may be made of p-type doped group III-V nitride semiconductor materials, such as p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or combinations thereof. In some embodiments, p-type doping can Be achieved by using p-type impurities, such as beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd). The material of the gate 150 may include a metal or a metal compound, such as tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, metal silicides, doped semiconductors, metal alloys, or combinations thereof.
In the exemplary plot of fig. 1, the source electrode 142, the drain electrode 144, the p-type doped nitride semiconductor layer 130, and the gate electrode 150 may constitute a high electron mobility transistor in combination with the 2DEG region 124, wherein a region between the source electrode 142 and the gate electrode 150 and a region between the drain electrode 144 and the gate electrode 150 may be defined as an access region (access region). The source electrode 142 and the drain electrode 144 are symmetrical with respect to the gate electrode 150, however, the disclosure is not limited thereto, and the arrangement relationship of the source electrode 142 and the drain electrode 144 may be adjustable, or may be asymmetrical. A connection metal 160 may be disposed on the source electrode 142, the drain electrode 144, and the gate electrode 150 for electrically connecting to an external circuit to effectively operate the high electron mobility transistor composed of the source electrode 142, the drain electrode 144, and the gate electrode 150.
In the present invention, the p-type doped nitride semiconductor layer 130 is used in order to make the semiconductor device 100A into an enhancement mode. For an enhancement mode device, the gate electrode 150 is in a normally-off (normal-off) state when it is substantially at zero bias. The reason for this is that the p-type doped nitride semiconductor layer 130 may deplete the lower 2DEG region 124 such that the region under the gate electrode 150 has different characteristics from the other 2DEG regions 124, for example, it has different electron concentrations due to the depletion effect such that the region under the gate electrode 150 disconnects the 2DEG region 124. By this mechanism, the semiconductor device 100A can have a normally-off characteristic. When no voltage is applied to the gate electrode 150, or the voltage applied to the gate electrode 150 is less than the threshold voltage, the region under the gate electrode 150 is still in the off 2DEG region 124, and thus no current will flow through this region.
The gate electrode 150 may define a gate window between the gate electrode 150 and the p-type doped nitride semiconductor layer 130. The location of the gate window may also be defined in conjunction with the dielectric layer 140. Specifically, the dielectric layer 140 is disposed on the second nitride semiconductor layer 122 and covers the p-type doped nitride semiconductor layer 130. The dielectric layer 140 may extend along sidewalls of the p-type doped nitride semiconductor layer 130. In addition, the source electrode 142 and the drain electrode 144 may also be in contact with the second nitride semiconductor layer 122 or the first nitride semiconductor layer 120 through the dielectric layer 140. The gate electrode 150 is located on the dielectric layer 140 and extends downward through the dielectric layer 140 and toward the p-type doped nitride semiconductor layer 130, and this downward extending portion is located within the dielectric layer 140 and is a block of the gate electrode 150 that is closest to the p-type doped nitride semiconductor layer 130, thereby defining a gate window.
The first surface reinforcing layer 132 may be disposed at the gate window between the gate electrode 150 and the p-type doped nitride semiconductor layer 130 such that the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 contact each other to form an interface. The interface between the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 may not be visible, i.e., the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 are fused with each other. The gate electrode 150 may also contact the first surface stiffener layer 132 to form an interface, which may be a visually distinct interface.
The first surface reinforcing layer 132 may cover the upper surface of the p-type doped nitride semiconductor layer 130. In some embodiments, the first surface reinforcing layer 132 completely covers the upper surface of the p-type doped nitride semiconductor layer 130 directly, so that the upper surface of the p-type doped nitride semiconductor layer 130 may be completely separated from the gate electrode 150 by the first surface reinforcing layer 132. The first surface reinforcing layer 132 may serve to enhance the resistance of the interface between the gate electrode 150 and the p-type doped nitride semiconductor layer 130 to high energy carrier bombardment.
Specifically, the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 may have the same group III element, and the first surface reinforcing layer 132 further has an oxygen element, and the oxygen element and the group III element can form a bond in the first surface reinforcing layer 132. For example, the group III element may be gallium or aluminum, the p-type doped nitride semiconductor layer 130 may be a p-type gallium nitride or a p-type aluminum gallium nitride layer, and the first surface reinforcing layer 132 may be a gallium oxynitride layer or an aluminum gallium oxynitride layer, both having gallium or aluminum elements, and the first surface reinforcing layer 132 further having oxygen elements. As the first surface reinforcing layer 132 can reinforce the surface of the p-type doped nitride semiconductor layer 130, it can suppress surface/interface degradation between the gate electrode 150 and the p-type doped nitride semiconductor layer 130 when carriers of the 2DEG region 124 are bombarded toward the gate window. Therefore, the gate breakdown voltage can be improved, the stability and the reliability of the device can be improved, and the service life of the device can be prolonged.
The first surface reinforcing layer 132 may be formed by surface-modifying the p-type doped nitride semiconductor layer 130, so that the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 may be connected to each other by an interatomic bond. Compared with the mode of additionally forming a reinforcing layer, the connecting mode has stronger bonding energy and can also avoid damage to other structures in preparation. In addition, since the first surface reinforcing layer 132 may be formed by surface-modifying the p-type doped nitride semiconductor layer 130, the distribution range of the first surface reinforcing layer 132 may be aligned with the upper surface of the p-type doped nitride semiconductor layer 130, so as to make the capability of resisting carriers more comprehensive. Hereinafter, the term "without using the surface reinforcing layer" means no modification, and the term "with using the surface reinforcing layer" means after modification.
Referring to fig. 2A to 2C, the surface modification is schematically illustrated in different stages of converting the surface of the p-type doped nitride semiconductor cap layer 130' into the first surface reinforcing layer 132 according to the present invention. As shown in fig. 2A, a p-type doped nitride semiconductor cap layer 130' is formed on the second nitride semiconductor layer 122 before the surface reinforcing layer is formed. The p-type doped nitride semiconductor cap layer 130' is formed of a material including gallium nitride, i.e., the inner structure thereof has gallium nitride bonds. As shown in fig. 2B, the surface of the p-type doped nitride semiconductor cap layer 130' may be oxidized and annealed at a high temperature to achieve surface modification. In some embodiments, the surface oxidation may be performed using an oxygen plasma or an oxygen-containing gas. As shown, during the surface oxidation, oxygen is added and diffused into the p-type doped nitride semiconductor cap layer 130'. As shown in fig. 2C, after the oxygen element diffusion, a high temperature annealing (the high temperature annealing includes annealing at a temperature in the range of 500 ℃ to 1000 ℃, for example, an environment of 800 ℃) may be performed, wherein the high temperature annealing may be performed in a nitrogen or ammonia environment to reconstruct the internal structure of the gallium nitride oxide layer and form the first surface reinforcing layer 132, while the remaining portion of the original p-type doped nitride semiconductor cap layer 130' remains as the p-type doped nitride semiconductor layer 130. Through the structural reconfiguration achieved through the high temperature annealing, the first surface reinforcing layer 132 formed may be a gallium oxynitride layer of a crystalline structure.
Referring to fig. 3A and fig. 3B, the surface features before and after modification are respectively represented by an atomic force microscope. It can be seen from the figure that after the surface modification, the roughness can be maintained almost without any large difference in surface morphology, and thus the surface modification does not damage or degrade the surface of the layer. Referring again to fig. 3C, the oxygen distribution depth of the layer before and after modification was measured by secondary ion mass spectrometry. As can be seen from the figure, the gallium oxynitride layer can be efficiently formed by the modification. The thickness of the gallium oxynitride layer can be further adjusted by adjusting the process parameters. In some embodiments, the first surface reinforcing layer 132 may be formed to a thickness of between about 1 nm and about 20 nm, which may enhance the bombardment of the interface with high energy carriers and avoid the possibility of device performance degradation.
Referring back to fig. 1, since the first surface reinforcing layer 132 is formed by surface-modifying the p-type doped nitride semiconductor layer 130, the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132 may be connected to each other by an interatomic bond, which may have a stronger bond energy. In addition, the width of the first surface reinforcing layer 132 is greater than the width of the gate window in this example, i.e., greater than the width of the bottom of the gate electrode 150. However, the width of the first surface reinforcing layer 132 may be equal to the width of the gate window, i.e., the width of the bottom of the gate electrode 150. For example, the width of the gate window may be made equal to the width of the gate metal 150 by a self-aligned process.
In terms of device performance improvement, fig. 4 is a graph of the relationship between gate-source voltage and gate current for no modification and after modification, and fig. 5 is a graph of breakdown time (t) for no modification and after modificationBD) A weibull plot of the distribution and a life prediction plot thereof. As shown in FIG. 4, the devices without and with the surface reinforcing layer have almost the same threshold voltage (V)TH) And on-resistance (R)ON). The gate breakdown voltage of the device with the surface reinforcing layer was about 12.7V in an environment of 25 c, while the gate breakdown voltage of the device without the surface reinforcing layer was about 10.5V. The gate breakdown voltage of the device with the surface reinforcing layer was about 13.4V in the environment of 150 c, while the gate breakdown voltage of the device without the surface reinforcing layer was about 11.4V. As shown in fig. 5, the predicted maximum applicable on-state gate voltage of the device using the surface reinforcing layer is 8.3V, which is superior to the device without the surface reinforcing layer, in the case of a 10-year lifetime.
According to some embodiments of the present invention, a device manufacturing method is provided for manufacturing the semiconductor device having the surface reinforcing layer. Referring to fig. 6, a flow chart of a method of manufacturing a semiconductor device 100A according to an embodiment of the invention is shown. The method of manufacturing the semiconductor device 100A includes steps S10, S20, S30, S40, S50, S60, S70, and step S80. Step S10 is to form a stacked structure. Step S20 is modifying the p-type doped nitride semiconductor cap layer. Step S30 is to remove a portion of the p-type doped nitride semiconductor cap layer and the surface reinforcing layer. Step S40 is to form a dielectric layer. In step S50, a source electrode and a drain electrode are formed. Step S60 is to remove a portion of the dielectric layer. Step S70 is to form a gate electrode. Step S80 is to form a bonding metal. The steps S10-S80 will be described in conjunction with schematic diagrams, as shown in fig. 7A-7H, respectively, which illustrate different stages in a method for fabricating the semiconductor device 100A.
Referring to fig. 7A, a stacked structure is formed in step S10. The substrate 110 may be prepared first, and then one or more layers of the buffer layer 112, the first nitride semiconductor layer 120, the second nitride semiconductor layer 122, and the p-type doped nitride semiconductor cap layer 130' may be sequentially formed over the substrate 110. In some embodiments, the buffer layer 112, the first nitride semiconductor layer 120, the second nitride semiconductor layer 122, and the p-type doped nitride semiconductor cap layer 130' may be formed by using Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), epitaxial growth (epitaxial growth), or other suitable processes.
Referring to fig. 7B, the p-type doped nitride semiconductor layer covering layer is modified corresponding to step S20. As previously described with respect to fig. 2A through 2C, the upper surface of the p-type doped nitride semiconductor cap layer 130 'may be subjected to an oxidation process and a high temperature anneal after the oxidation to form a surface-strengthened cap layer 132' (or surface-strengthened cap layer). In some embodiments, the oxidation treatment is achieved by applying an oxygen plasma gas. In some embodiments, the surface-strengthening cap layer 132' may also be formed by deposition.
Referring to fig. 7C, the p-type doped nitride semiconductor cap layer and the surface reinforcing layer are removed in step S30. A portion of the p-type doped nitride semiconductor cap layer 130 'and a portion of the surface reinforcing cap layer 132' may be removed to form the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132. After the removal step, the second nitride semiconductor layer 122 is exposed. The removal may be by photolithography, exposure and development, etching, other suitable processes, or a combination thereof.
Referring to fig. 7D, a dielectric layer is formed corresponding to step S40. A dielectric layer 140 may be formed on the second nitride semiconductor layer 122. The dielectric layer 140 is formed to cover the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132. The dielectric layer 140 may be conformal with the p-type doped nitride semiconductor layer 130 and the first surface reinforcing layer 132, and thus protrude upward.
Referring to fig. 7E, a source electrode and a drain electrode are formed corresponding to step S60. A source electrode 142 and a drain electrode 144 may be formed through the dielectric layer 140 and contact the second nitride semiconductor layer 122 or the first nitride semiconductor layer 120. In this step, a portion of the dielectric layer 140 may be removed to expose the second nitride semiconductor layer 122, so as to define source/drain regions. Next, a source electrode 142 and a drain electrode 144 are formed by a deposition process and a patterning process. In some embodiments, the second nitride semiconductor layer 120 may be removed, in whole or in part, by etching or the like before depositing the metal.
Referring to fig. 7F, a portion of the dielectric layer is removed in step S70. A portion of the dielectric layer 140 may be removed to expose the first surface stiffener layer 132. The opening formed by removing the dielectric layer 140 to expose the first surface stiffener layer 132 may be referred to as a gate window.
Referring to fig. 7G, a gate electrode is formed corresponding to step S70. The gate electrode 150 may be formed on the dielectric layer 140 such that the gate electrode 150 extends to contact the first surface reinforcing layer 132 exposed by the dielectric layer 140. Specifically, a gate conductive layer may be formed by a deposition process and filled into the opening of the dielectric layer 140. Then, by using a patterning process, an excess portion of the gate conductive layer is removed to leave a portion designed as a gate electrode, thereby forming the gate electrode 150. In this case, the width of the gate window is smaller than that of the gate metal 150, and in other cases, the width of the gate window can be equal to that of the gate metal 150 through a self-aligned process.
Please refer to fig. 7H, which corresponds to the step S80. A connection metal 160 may be formed on the source electrode 142, the drain electrode 144, and the gate electrode 150, respectively. The connectable metal 160 is then electrically connected into the designed circuit topology.
Referring to fig. 8, a cross-sectional view of a semiconductor device 100B is shown, according to some embodiments of the present invention. At least one difference between the present embodiment and the foregoing embodiment is that, in the present embodiment, the width of the gate window, the width of the gate electrode 150, and the width of the p-type doped nitride semiconductor layer 130 are the same. In addition, the width of the first surface reinforcing layer 132 is also identical to the width of the gate electrode 150 and the p-type doped nitride semiconductor layer 130.
Referring to fig. 9, a cross-sectional view of a semiconductor device 100C is shown, according to some embodiments of the present invention. At least one difference between the present embodiment and the foregoing embodiments is that the semiconductor device 100C of the present embodiment further includes a second surface reinforcing layer 170. The second surface reinforcing layer 170 is disposed between the second nitride semiconductor layer 122 and the source electrode 142, and is also disposed between the second nitride semiconductor layer 122 and the drain electrode 144. The second surface reinforcing layer 170 may be formed in the same manner as previously described, and may be formed by oxidizing and high-temperature annealing the surface of the second nitride semiconductor layer 122. In some embodiments, the second surface reinforcing layer 170 may also be formed by deposition. Accordingly, the second surface reinforcing layer 170 may be sandwiched between the second nitride semiconductor layer 122 and the dielectric layer 140. In this way, the second surface reinforcing layer 170 reinforces the surface of the second nitride semiconductor layer 122, and when high-energy carriers bombard the nitride semiconductor layer 122, the degradation caused by the high-energy carrier bombardment can be suppressed and thus the degradation of the device performance can be suppressed.
Since the second surface reinforcing layer 170 may be formed by modifying the surface of the second nitride semiconductor layer 122, the second nitride semiconductor layer 122 and the second surface reinforcing layer 170 may have the same group III element, and the second surface reinforcing layer 170 may further have an oxygen element, and the oxygen element and the group III element form a bond in the second surface reinforcing layer 170. Further, the group III element may be gallium or aluminum, so the second nitride semiconductor layer 122 may be an aluminum gallium nitride or aluminum nitride layer, and the second surface reinforcing layer 170 may be an aluminum gallium oxynitride layer. The AlGaAs layer as the second surface reinforcing layer 170 may suppress degradation of the second nitride semiconductor layer 122/dielectric layer 140 interface caused by high energy carrier bombardment. The boundaries of the second surface reinforcing layer 170 may be aligned with the boundaries of both sides of the p-type doped nitride semiconductor layer 130, which facilitates the formation of the second surface reinforcing layer 170.
Fig. 10 is a cross-sectional view of a semiconductor device 100D according to some embodiments of the invention. At least one difference between the present embodiment and the previous embodiment is that the first surface reinforcing layer 132 of the present embodiment extends downward along the sidewall of the p-type doped nitride semiconductor layer 130. The cross-sectional profile of the first surface reinforcing layer 132 may have a bridge-spanning profile. This can be achieved by patterning the p-type doped nitride semiconductor layer 130 first, followed by surface modification. Since the first surface reinforcing layer 132 extends down along the sidewalls of the p-type doped nitride semiconductor layer 130, the protection margin can be further increased to block more potential carriers bombarded upward, thereby maintaining the device performance.
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. It is intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
Terms, such as "substantially", "approximately" and "about", as used herein and not otherwise defined, are used for descriptive and explanatory purposes as small variations. When used with an event or condition, the term can include instances where the event or condition occurs precisely as well as instances where the event or condition occurs approximately. For example, when used with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. By the term "substantially coplanar", it may refer to two surfaces lying in the micrometer range along the same plane, for example within 40 micrometers (μm), within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane.
As used herein, the singular terms "a", "an" and "the" may include the plural reference unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "above" or "on top of" another component may include instances where the preceding component is directly on (e.g., in physical contact with) the succeeding component, and instances where one or more intervening components are located between the preceding and succeeding components.
While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The drawings are not necessarily to scale. There may be a distinction between the processes presented in the present invention and the actual devices due to manufacturing process and tolerance factors. Other embodiments of the invention may not be specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process, to the objective, spirit and scope of the present invention. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein are described by performing particular operations in a particular order with reference to that order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of such operations is not limiting.
Claims (18)
1. A high electron mobility transistor device, comprising:
a first nitride semiconductor layer having a first band gap;
a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second band gap, the second band gap being greater than the first band gap;
a source electrode provided on the second nitride semiconductor layer or on the first nitride semiconductor layer
A drain electrode provided on the second nitride semiconductor layer or on the first nitride semiconductor layer;
a p-type doped nitride semiconductor layer disposed on the second nitride semiconductor layer and between the gate electrode and the drain electrode;
a first surface reinforcing layer disposed on the p-type doped nitride semiconductor layer, the p-type doped nitride semiconductor layer and the first surface reinforcing layer having the same group III element, wherein the first surface reinforcing layer further has an oxygen element, and forms a bond with the group III element of the first surface reinforcing layer in the first surface reinforcing layer; and
and a gate electrode disposed on the first surface reinforcing layer and between the source electrode and the drain electrode, wherein a gate window is defined between the gate electrode and the first surface reinforcing layer, and the width of the gate window is smaller than or equal to the width of the p-type doped nitride semiconductor layer.
2. The semiconductor device according to claim 1, wherein the p-type doped nitride semiconductor layer and the first surface reinforcing layer are in contact with each other to form an interface, and the p-type doped nitride semiconductor layer and the first surface reinforcing layer are connected to each other by an interatomic bond.
3. The semiconductor device according to claim 1, further comprising:
and the dielectric layer is arranged on the second nitride semiconductor layer, wherein the gate electrode penetrates through the dielectric layer so as to define the gate window in the dielectric layer.
4. The semiconductor device according to claim 1, wherein the first surface reinforcing layer directly covers an upper surface of the p-type doped nitride semiconductor layer entirely.
5. The semiconductor device according to claim 1, wherein the first surface enhancement layer extends downward along a sidewall of the p-type doped nitride semiconductor layer.
6. The semiconductor device of claim 1, wherein the p-type doped nitride semiconductor layer comprises a p-type gallium nitride layer or a p-type aluminum gallium nitride layer, and the first surface enhancement layer comprises a gallium oxide layer, a gallium oxynitride layer, an aluminum gallium oxynitride layer, or a combination thereof.
7. The semiconductor device according to claim 1, wherein the first surface reinforcing layer has a thickness of 1 nm to 20 nm.
8. The semiconductor device according to claim 1, further comprising:
and a second surface reinforcing layer disposed between the second nitride semiconductor layer and the source electrode and also between the second nitride semiconductor layer and the drain electrode, the second nitride semiconductor layer and the second surface reinforcing layer having the same group III element, wherein the second surface reinforcing layer further has an oxygen element, and forms a bond with the group III element of the second surface reinforcing layer in the second surface reinforcing layer.
9. A method of manufacturing a semiconductor device, comprising:
forming a second nitride semiconductor layer on the first nitride semiconductor layer;
forming a p-type doped nitride semiconductor cap layer on the second nitride semiconductor layer;
carrying out oxidation treatment and high-temperature annealing on the upper surface of the p-type doped nitride semiconductor cap layer to form a surface reinforced cap layer;
removing a part of the p-type doped nitride semiconductor cap layer and a part of the surface reinforcing cap layer to form a p-type doped nitride semiconductor layer and a first surface reinforcing layer;
forming a dielectric layer to cover the second nitride semiconductor layer and the p-type doped nitride semiconductor;
forming a source electrode and a drain electrode which pass through the dielectric layer and contact the second nitride semiconductor layer or the first nitride semiconductor layer;
removing a portion of the dielectric layer to expose the first surface stiffener layer;
forming a gate electrode on the dielectric layer such that the gate electrode extends into contact with the first surface-reinforcing layer.
10. The method of claim 9, further comprising:
forming a second surface reinforcing layer on the second nitride semiconductor layer before forming the dielectric layer.
11. The method of claim 10, wherein the first surface strengthening layer comprises gallium oxide, gallium oxynitride, aluminum gallium oxynitride or combinations thereof, and the second surface strengthening layer comprises gallium oxynitride, aluminum gallium oxynitride or combinations thereof.
12. The method of claim 10, wherein the first or second surface-strengthening layer is formed by deposition.
13. The method of claim 10, wherein the first or second surface-reinforcement-layer surface-reinforcing layer is formed by oxidation and subsequent high-temperature annealing.
14. The method of claim 13, wherein the oxidizing is exposing the device surface to an oxygen-containing plasma or an oxygen-containing gas.
15. The method of claim 13, wherein the high temperature annealing comprises annealing at a temperature in a range of 500 ℃ to 1000 ℃.
16. The method of claim 13, wherein the high temperature annealing is performed in a nitrogen or ammonia environment.
17. A method of manufacturing a semiconductor device, comprising:
forming a second nitride semiconductor layer on the first nitride semiconductor layer;
forming a p-type doped nitride semiconductor cap layer on the second nitride semiconductor layer;
carrying out oxidation treatment and high-temperature annealing on the upper surface of the p-type doped nitride semiconductor cap layer to form a surface reinforced cap layer;
forming a gate electrode on the surface-reinforcing cap layer;
removing a part of the p-type doped nitride semiconductor cap layer and a part of the surface reinforcing cap layer through a self-alignment process of the grid electrode so as to form a p-type doped nitride semiconductor layer and a first surface reinforcing layer;
a grid window is defined between the grid electrode and the first surface reinforcing layer, and the width of the grid window, the width of the grid electrode and the width of the first surface reinforcing layer are consistent;
forming a dielectric layer to cover the second nitride semiconductor layer and the p-type doped nitride semiconductor;
forming a source electrode and a drain electrode which pass through the dielectric layer and contact the second nitride semiconductor layer or the first nitride semiconductor layer.
18. The method of claim 17, further comprising:
forming a second surface reinforcing layer on the second nitride semiconductor layer before forming the dielectric layer.
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| WO2024103199A1 (en) * | 2022-11-14 | 2024-05-23 | Innoscience (Zhuhai) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024103199A1 (en) * | 2022-11-14 | 2024-05-23 | Innoscience (Zhuhai) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing the same |
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