CN116344608A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN116344608A
CN116344608A CN202111683255.9A CN202111683255A CN116344608A CN 116344608 A CN116344608 A CN 116344608A CN 202111683255 A CN202111683255 A CN 202111683255A CN 116344608 A CN116344608 A CN 116344608A
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China
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layer
semiconductor
semiconductor layer
electrode
hole concentration
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CN202111683255.9A
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Inventor
焦佑麒
黄永立
朱俊宜
周圣伟
张宏铭
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Hannstar Display Corp
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Hannstar Display Corp
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Priority to CN202111683255.9A priority Critical patent/CN116344608A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor device includes a channel layer, an active layer, a semiconductor layer, a gate electrode, a drain electrode and a source electrode. The active layer is located on the channel layer. The semiconductor layer is arranged on the active layer and comprises a P-type dopant. The gate electrode is located on the semiconductor layer, the gate electrode comprises a first metal electrode, and the material of the first metal electrode comprises nickel, wherein the first metal electrode contacts a first part of the semiconductor layer, the first metal electrode does not contact a second part of the semiconductor layer, and the hole concentration of the first part of the semiconductor layer is higher than that of the second part of the semiconductor layer. The drain electrode and the source electrode are respectively connected with two sides of the channel layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to a semiconductor device and a manufacturing method thereof.
Background
Semiconductor devices are used in a variety of electronic applications, such as high power devices, personal computers, cell phones, digital cameras, and other electronic devices. These semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, and then patterning the various material layers using a photolithography process to form circuit devices and components on the semiconductor substrate.
Among these devices, high Electron Mobility Transistors (HEMTs) are widely used in high power applications due to their advantages such as high output power and high breakdown voltage.
Disclosure of Invention
In the embodiments of the present invention, the activation degree of the doped semiconductor layer under the gate metal electrode can be locally enhanced only by the arrangement of the gate metal electrode, and the step of removing the doped semiconductor layer by etching can be omitted in the design of the process step, so that the on-voltage stability and reliability stability of the semiconductor device are improved. In a further embodiment, when the doped semiconductor layer and the active layer comprise similar materials (e.g., comprise the same metal element (e.g., aluminum)), the concentration of the metal element (e.g., aluminum) in the doped semiconductor layer may be set to epitaxially grow in a decreasing manner, resulting in a graded concentration profile of the metal element (e.g., aluminum) in the doped semiconductor layer. Therefore, on one hand, the lower end of the doped semiconductor layer can be lattice matched with the active layer so as to reduce electric leakage caused by lattice mismatch with the active layer and improve the limitation of conductive carriers, and on the other hand, the upper end of the doped semiconductor layer can be easy for the grid metal electrode to form ohmic contact.
According to some embodiments of the present invention, a semiconductor device includes a channel layer, an active layer, a semiconductor layer, a gate electrode, and a drain and source electrode. The active layer is located on the channel layer. The semiconductor layer is arranged on the active layer and comprises a P-type dopant. The gate electrode is located on the semiconductor layer, the gate electrode comprises a first metal electrode, and the material of the first metal electrode comprises nickel, wherein the first metal electrode contacts a first part of the semiconductor layer, the first metal electrode does not contact a second part of the semiconductor layer, and the hole concentration of the first part of the semiconductor layer is higher than that of the second part of the semiconductor layer. The drain electrode and the source electrode are respectively connected with two sides of the channel layer.
In some embodiments, the p-type dopant comprises magnesium.
In some embodiments, the semiconductor layer comprises a gallium nitride layer or an aluminum gallium nitride layer.
In some embodiments, the active layer comprises an AlGaN layer, and the semiconductor layer comprises Al x Ga (1-x) N layers, where x is greater than or equal to 0 and less than 1, and x decreases in a direction perpendicular to the substrate and toward the gate electrode.
In some embodiments, alxGa (1-x) X in the N layer decreases to 0 in a direction perpendicular to the channel layer and toward the gate electrode.
In some embodiments, the ratio of the hole concentration of the first portion of the semiconductor layer to the hole concentration of the second portion of the semiconductor layer is greater than 10.
In some embodiments, the gate electrode further includes a second metal electrode disposed on the first metal electrode.
In some embodiments, the semiconductor layer is disposed on the active layer in a first direction, and the second portion of the semiconductor layer is located on two sides of the first portion of the semiconductor layer in a second direction, wherein the first direction is perpendicular to the channel layer, and the second direction is perpendicular to the first direction.
In some embodiments, the second portion of the semiconductor layer is located between the gate electrode and the drain electrode and between the gate electrode and the source electrode in the second direction.
According to some embodiments of the present invention, a method includes forming a channel layer on a substrate; forming an active layer on the channel layer; forming a semiconductor material layer on the active layer, wherein the semiconductor material layer comprises a P-type dopant; forming a gate electrode on the semiconductor material layer, wherein the gate electrode comprises a first metal electrode, and the material of the first metal electrode comprises nickel, and the first metal electrode contacts a first part of the semiconductor material layer and the first metal electrode does not contact a second part of the semiconductor material layer; and after forming the gate electrode, performing a thermal annealing process to convert the semiconductor material layer into a semiconductor layer, wherein the semiconductor layer has a first portion and a second portion, the first portion of the semiconductor layer overlaps the first metal electrode in a direction perpendicular to the substrate, the second portion of the semiconductor layer does not overlap the first metal electrode in a direction perpendicular to the substrate, and a hole concentration of the first portion of the semiconductor layer is higher than a hole concentration of the second portion of the semiconductor layer.
In some embodiments, the thermal annealing process activates the first portion of the semiconductor material layer more than the second portion of the semiconductor material layer.
In some embodiments, the hole concentration of the first portion of the semiconductor layer is greater than a hole concentration of the first portion of the semiconductor material layer, and the hole concentration of the second portion of the semiconductor layer is greater than or equal to a hole concentration of the second portion of the semiconductor material layer.
In some embodiments, an annealing temperature of the thermal annealing process is in a range of 200 degrees to 800 degrees.
In some embodiments, the method further comprises forming a source recess and a drain recess after the thermal annealing process, the source recess and the drain recess penetrating the second portion of the semiconductor layer and the active layer; and forming a source and a drain in the source recess and the drain recess, respectively, wherein the source recess and the drain recess contact the channel layer.
Drawings
For a more complete understanding of the embodiments and advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1A is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 1B is another schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 2-6 are schematic cross-sectional views of a semiconductor device at various stages in the fabrication process according to some embodiments of the present disclosure;
fig. 7A is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 7B is a heterostructure band diagram of the semiconductor device of fig. 7A.
Detailed Description
Embodiments of the present disclosure are discussed in detail below. However, it is to be understood that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative and are not meant to limit the scope of the disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. Unless otherwise limited, the singular forms "a", "an" and "the" are intended to mean the plural forms as well.
It will be understood that, although the terms "first," "second," "third," and the like may be used herein to describe different signals and/or entities, such signals and/or entities should not be limited by these terms. Such terms are merely used to distinguish one signal and/or entity from another signal and/or entity.
For simplicity and clarity of illustration, reference numerals and/or letters may be reused herein in the various embodiments, but this is not meant to indicate causal relationships between the various embodiments and/or configurations discussed.
Fig. 1A is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes a substrate 110, a nucleation buffer layer 120, a channel layer 130, an active layer 140, a doped semiconductor layer 150, a gate electrode 160, a drain electrode 170D, and a source electrode 170S.
The substrate 110 may be formed of an insulating or semi-insulating material. For example, the substrate 110 may be formed of one or more of sapphire, semiconductor, and diamond, and the size of the substrate may range from about 2 to about 12 inches. In some embodiments, the semiconductor material of the substrate 110 may comprise an elemental semiconductor, such as silicon, germanium; compound semiconductors such as silicon carbide, gallium nitride; an alloy semiconductor; and combinations thereof. The material of the substrate 110 of the present invention is not limited to the above examples.
A nucleation buffer layer 120 is disposed on the substrate 110. Nucleation buffer layer 120 may comprise one or more layers of a iii-v semiconductor compound. For example, nucleation buffer layer 120 is comprised of a nucleation layer, such as an aluminum nitride (AlN) layer, and a buffer layer, such as a gallium nitride (GaN) layer. The nucleation layer may provide an appropriate lattice structure for subsequent epitaxial growth of a semiconductor layer thereon having a corresponding lattice structure. Taking the trisazo semiconductor material as an example, the nucleation layer may provide a wurtzite (wurtzite) lattice structure. The buffer layer may have an appropriate lattice structure and/or coefficient of thermal expansion to compensate for lattice mismatch and/or coefficient of thermal expansion mismatch between the nucleation layer and the overlying layer body, such as channel layer 130 (e.g., a gallium nitride (GaN) layer). The buffer layer may be doped with carbon or iron to achieve an insulating or semi-insulating state, preventing the potential of the channel layer 130 from leaking onto the substrate 110.
The channel layer 130 and the active layer 140 are located on the nucleation buffer layer 120. The active layer 140 may also be referred to as a barrier (barrier) layer. The channel layer 130 and the active layer 140 may comprise one or more iii-v semiconductor compound layers, wherein the channel layer 130 and the active layer 140 are different in composition. For example, the active layer 140 may include a metal element, such as aluminum. In some embodiments, the channel layer 130 is composed of GaN, and the active layer 140 is composed of AlGaN. The energy gap of the active layer 140 is greater than the energy gap of the channel layer 130. Thus, a heterojunction is formed between the active layer 140 and the channel layer 130. At this hetero interface, a large-scale conduction band discontinuity occurs, so that free electrons diffuse from the higher bandgap active layer 140 to the lower bandgap channel layer 130, forming a two-dimensional electron gas (two-dimensional electron gas) 2DEG. In other words, the active layer 140 is used to form the two-dimensional electron gas 2DEG in the channel layer 130. This two-dimensional electron gas 2DEG may also be referred to as a carrier channel. This two-dimensional electron gas 2DEG is shown in the figure by a dotted line. It should be noted that, the semiconductor device 100 of the present invention is a normally-off (or enhancement) type semiconductor device, and the semiconductor device 100 shown in fig. 1A is in a state where the gate electrode 160 is biased to be greater than the threshold voltage (threshold voltage) and the semiconductor device 100 is turned on. Referring to fig. 1B, fig. 1B is another schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 shown in fig. 1B is in a state in which the gate electrode 160 is biased (e.g., zero) or not biased with a voltage less than a threshold voltage, and the semiconductor device 100 is turned off (i.e., not turned on). When the semiconductor device 100 is not biased or is biased with a voltage smaller than the threshold voltage, the two-dimensional electron gas 2DEG located right under the gate electrode 160 and the first portion 152 of the semiconductor layer 150 in the first direction D1 is depleted (depleted) to form a two-dimensional electron gas 2DEG cut-off region such that the semiconductor device 100 is turned off, that is, the channel layer 130 includes the first portion 132 and the second portion 134, the first portion 132 overlaps the first portion 152 of the semiconductor layer 150 in the first direction D1, the second portion 134 overlaps the second portion 154 of the semiconductor layer 150 in the first direction D1, the second portion 134 of the channel layer 130 has the two-dimensional electron gas 2DEG, but the first portion 132 of the channel layer 130 does not have the two-dimensional electron gas 2DEG and forms the two-dimensional electron gas 2DEG cut-off region.
In some embodiments, the active layer 140 and the channel layer 130 may be referred to as an intrinsic (intrinsic) semiconductor layer, wherein the active layer 140 and the channel layer 130 are not intentionally doped. For example, the active layer 140 and the channel layer 130 are not intentionally doped, but may be doped due to process contamination. Alternatively, in some other embodiments, the upper surface of the channel layer 130 may be doped with a suitable dopant, such as Si, to form a two-dimensional electron gas 2DEG. Furthermore, in some embodiments, the active layer 140 may be an N-type semiconductor.
In some embodiments, the nucleation buffer layer 120, the channel layer 130, and the active layer 140 are all formed of a tri-nitride semiconductor having a wurtzite (wurtzite) lattice structure with a polarization plane. For example, the channel layer 130 includes gallium nitride (GaN), and the active layer 140 includes aluminum gallium nitride (AlGaN). In these embodiments, electrons generated by the piezoelectric effect fall from the active layer 140 to the channel layer 130 via the polarization plane, which in turn generates a two-dimensional electron gas 2DEG of highly mobile conduction electrons within the channel layer 130. In other embodiments, the nucleation buffer layer 120, the channel layer 130 and the active layer 140 may also use other kinds of III-V semiconductors, but not limited to III-V semiconductors.
The semiconductor layer 150 is disposed on the active layer 140 and may be composed of a suitable iii-v semiconductor layer (e.g., a tri-nitride semiconductor) having the same lattice structure as the underlying active layer 140 (e.g., wurtzite lattice structure). In this embodiment, the semiconductor layer 150 is doped with a p-type dopant such as, but not limited to, magnesium, calcium, zinc, beryllium, carbon, and combinations thereof. The semiconductor layer 150 includes a first portion 152 and a second portion 154, the first portion 152 is a P-type semiconductor, and the hole concentration of the first portion 152 is much greater than that of the second portion 154. For example, the ratio of the hole concentration of the first portion 152 of the semiconductor layer 150 to the hole concentration of the second portion 154 of the semiconductor layer 150 is greater than 10. Specifically, the first portion 152 of the semiconductor layer 150 is a P-type semiconductor, and because the hole concentration of the second portion 154 of the semiconductor layer 150 is very low, the second portion 154 of the semiconductor layer 150 has characteristics similar to an insulator, and the resistance of the second portion 154 of the semiconductor layer 150 is much larger than the resistance of the first portion 152 of the semiconductor layer 150. The differences between the first portion 152 and the second portion 154 of the semiconductor layer 150 are further described in the paragraphs that follow the fabrication process. The first portion 152 of the semiconductor layer 150 can raise the energy level, so that the two-dimensional electron gas 2DEG in the first portion 132 of the channel layer 130 located directly under the first portion 152 of the semiconductor layer 150 in the first direction D1 is depleted, which helps to make the semiconductor device 100 normally off.
In some embodiments, the semiconductor layer 150 may include a metal element, such as aluminum, to facilitate lattice matching of the underlying active layer 140. For example, the semiconductor layer 150 may be a p-type doped aluminum gallium nitride layer (AlGaN). Alternatively, in some other embodiments, the semiconductor layer 150 may be free of metal elements (e.g., free of aluminum elements). For example, the semiconductor layer 150 may be a p-type doped gallium nitride layer (GaN).
The gate electrode 160 is located on the semiconductor layer 150. The gate electrode 160 may be a multi-layer gate stack. For example, the gate electrode 160 includes a first metal electrode 162 and a second metal electrode 164 disposed on the first metal electrode 162, which may include different materials. The material of the first metal electrode 162 includes nickel. The thickness of the first metal electrode 162 may be less than 10 micrometers. Preferably, the thickness of the first metal electrode 162 may be less than 10 nanometers. The first metal electrode 162 may serve as a contact electrode that contacts the first portion 152 of the semiconductor layer 150 and forms an ohmic contact with the first portion 152 of the semiconductor layer 150. The first metal electrode 162 does not contact the second portion 154 of the semiconductor layer 150. The reason for the material of the first metal electrode 162 that is in contact with the first portion 152 of the semiconductor layer 150 comprising nickel will be further described in the paragraphs that follow the fabrication process. The second metal electrode 164 may include titanium, gold, other metals, alloys thereof, or combinations thereof, but is not limited thereto. The thickness of the second metal electrode 164 may be greater than that of the first metal electrode 162, but is not limited thereto. The second metal electrode 164 may comprise a single layer or multiple layers of metal, and is not limited to the illustration.
In some embodiments of the present invention, the hole concentration of the first portion 152 of the semiconductor layer 150 is higher than the hole concentration of the second portion 154 of the semiconductor layer 150. The difference in hole concentration allows the first portion 152 of the semiconductor layer 150 to be considered conductive and form a portion of the gate of the semiconductor device 100, thereby affecting whether the two-dimensional electron gas 2DEG is turned on or not; on the other hand, the second portion 154 of the semiconductor layer 150 has a lower hole concentration and may be considered to be substantially electrically insulating. The advantage of the first portion 152 and the second portion 154 of the semiconductor layer 150 having different hole concentrations in the semiconductor device 100 according to the present invention will be described in detail in the following description of the manufacturing process of the semiconductor device 100.
In some embodiments, the nucleation buffer layer 120, the channel layer 130, the active layer 140 and the semiconductor layer 150 are sequentially disposed on the substrate 110 according to the first direction D1. For example, the semiconductor layer 150 is disposed on the active layer 140 in the first direction D1. The second portion 154 of the semiconductor layer 150 is located on two sides of the first portion 152 of the semiconductor layer 150 in a second direction D2, wherein the first direction D1 is perpendicular to the substrate 110, and the second direction D2 is perpendicular to the first direction D1.
In some embodiments, the drain 170D and the source 170S are respectively connected to two sides of the channel layer 130. The drain 170D and the source 170S may comprise suitable metals such as, but not limited to, titanium, aluminum, nickel, gold, copper, alloys thereof, or combinations thereof as electrodes. Thereby, the operation of the semiconductor device 100 can be achieved. Specifically, when the semiconductor device 100 is turned on, electrons of the two-dimensional electron gas 2DEG move from the source electrode 170S to the drain electrode 170D.
In some embodiments, in the second direction D2, the second portion 154 of the semiconductor layer 150 is located between the first portion 152 of the semiconductor layer 150 and the drain electrode 170D and between the first portion 152 of the semiconductor layer 150 and the source electrode 170S. In some embodiments, in the second direction D2, two sides of the second portion 154 of the semiconductor layer 150 respectively contact the first portion 152 of the semiconductor layer and the drain electrode 170D or respectively contact the first portion 152 of the semiconductor layer and the source electrode 170S, but not limited thereto. Since the second portion 154 of the semiconductor layer 150 is considered to be substantially electrically insulating, its presence does not result in electrical conduction between the gate electrode 160 and the drain 170D/source 170S, operation of the semiconductor device 100 is still achieved. In some embodiments, the semiconductor device 100 may further include a passivation layer (not shown) covering the gate electrode 160 and the upper surface of the second portion 154 of the semiconductor layer 150. For example, a passivation layer (not shown) may extend from the upper surface of the gate electrode 160 and to the upper surface of the second portion 154 of the semiconductor layer 150.
Fig. 2-6 are schematic cross-sectional views of a semiconductor device at various stages of a fabrication process according to some embodiments of the present disclosure.
Referring to fig. 2, first, a nucleation buffer layer 120 is deposited on a substrate 110. The nucleation buffer layer 120 may have a thickness in the range of about 100 nanometers to about 10 microns. The deposition of nucleation buffer layer 120 may comprise a suitable epitaxial growth process, such as chemical vapor deposition (chemical vapor deposition; CVD), metal organic chemical vapor deposition (metal organic chemical vapor deposition; MOCVD), atomic layer deposition (atomic layer deposition; ALD), and the like, or combinations thereof. In some embodiments, the deposition of nucleation buffer layer 120 may include depositing a nucleation layer (e.g., an AlN nucleation layer) on the substrate, and then depositing a buffer layer (e.g., a GaN buffer layer) on the nucleation layer. Carbon doping (Carbon doping) and/or iron doping (Fe doping) may be used to form a semi-insulating high quality GaN buffer layer to prevent the potential of the subsequently formed channel layer 130 from leaking onto the substrate 110 when depositing the GaN buffer layer of the nucleation buffer layer 120.
Next, on the nucleation buffer layer 120, a channel layer 130 is deposited. The thickness of the channel layer 130 may be in the range of about 60 nanometers to about 600 nanometers. Deposition of the channel layer 130 may include a suitable epitaxial growth process, such as CVD, MOCVD, ALD, or the like, or a combination thereof.
On the channel layer 130, an active layer 140 is deposited. The thickness of the active layer 140 may be in the range of about 1 nm to about 10 nm. The deposition of the active layer 140 may comprise a suitable epitaxial growth process, such as CVD, MOCVD, ALD, or the like, or a combination thereof.
On the active layer 140, a layer 150A of semiconductor material is deposited. The thickness of the semiconductor layer material 150A may be in the range of about 50 nanometers to about 120 nanometers. The deposition of the semiconductor material layer 150A may comprise a suitable epitaxial growth process, such as CVD, MOCVD, ALD, or the like, or a combination thereof. In some embodiments, the semiconductor material layer 150A may be doped in situ (in situ) with a p-type dopant during epitaxial growth, such as, but not limited to, magnesium, calcium, zinc, beryllium, carbon, and combinations thereof. Alternatively, the p-type dopant may be implanted into the layer 150A of epitaxially grown semiconductor material, as opposed to in-situ doping. For example, the semiconductor material layer 150A may be a p-doped aluminum gallium nitride layer (AlGaN) or a p-doped gallium nitride layer (GaN).
The nucleation buffer layer 120, channel layer 130, active layer 140, and semiconductor material layer 150A above may be deposited in situ. In other words, the nucleation buffer layer 120, the channel layer 130, the active layer 140 and the semiconductor material layer 150A are sequentially deposited in the same deposition chamber, for example, through MOCVD, but not limited thereto. In other embodiments, at least two of nucleation buffer layer 120, channel layer 130, active layer 140, and semiconductor material layer 150A may be deposited separately in different deposition chambers.
Referring to fig. 3, a gate electrode 160 is formed on the semiconductor material layer 150A. The gate electrode 160 may be formed through a metal lift-off process. Specifically, a photoresist is first formed on the semiconductor material layer 150A, wherein the photoresist covers the second portion 154A of the semiconductor material layer 150A and has an opening to expose the first portion 152A of the semiconductor material layer 150A. The photoresist is formed by a suitable photolithography process including coating a photosensitive material, exposing, developing, rinsing, baking, and the like. Next, a gate electrode layer is deposited over the photoresist and the second portion 154A of the semiconductor material layer 150A. In some embodiments, the gate electrode layer includes a first metal electrode layer and a second metal electrode layer, which are made of different materials. For example, the first metal electrode layer may comprise nickel, the second metal electrode layer may comprise titanium, gold, other metals, alloys thereof, or combinations thereof, and the second metal electrode layer may comprise a single layer or multiple layers of metals. The metal electrode layer of the gate electrode layer may be performed by physical vapor deposition (physical vapor deposition; PVD), ALD, or combinations thereof. Then, the photoresist and a part of the gate electrode layer on the photoresist are removed. That is, a portion of the gate electrode layer located on the second portion 154A of the semiconductor material layer 150A is removed. Thereby, on the first portion 152A of the semiconductor material layer 150A, the remaining first metal electrode layer forms the first metal electrode 162, the remaining second metal electrode layer forms the second metal electrode 164, and the combination of the first metal electrode 162 and the second metal electrode 164 constitutes the gate electrode 160. Through the process, the first metal electrode 162 (e.g., nickel) is formed to contact the first portion 152A of the semiconductor material layer 150A and not contact the second portion 154A of the semiconductor material layer 150A.
Herein, the first portion 152A of the semiconductor material layer 150A may refer to the semiconductor material layer 150A directly under the gate electrode 160, and the second portion 154 of the semiconductor material layer 150 may refer to the semiconductor material layer 150A not directly under the gate electrode 160. That is, from the first direction D1, the gate electrode 160 overlaps the first portion 152A of the semiconductor material layer 150A, and the gate electrode 160 does not overlap the second portion 154A of the semiconductor material layer 150A. Specifically, the intersection of the first portion 152A and the second portion 154A (as shown by the dashed line 150I) may be generally opposite the sides of the Ji Shanji electrode 160.
It should be noted that, at the present stage, the p-doped semiconductor material layer 150A is not subjected to the p-dopant activation step, and the dopant activation step may include, for example, a thermal annealing (thermal annealing) process or a low-energy electron beam irradiation (low energy electron beam irradiation) process, so that, at the present stage, the hole concentration in the semiconductor material layer 150A is extremely small, and the semiconductor material layer 150A may be regarded as being substantially electrically insulating.
Referring to fig. 4, a thermal annealing process is performed to convert the semiconductor material layer 150A into the semiconductor layer 150, wherein the first portion 152 of the semiconductor layer 150 is a P-type semiconductor, and the hole concentration of the first portion 152 of the semiconductor layer 150 is substantially greater than that of the second portion 154 of the semiconductor layer 150. Because the p-type dopant (e.g., magnesium) in the semiconductor material layer 150A will bond with hydrogen and nickel has the property of enhancing desorption of the p-type dopant from hydrogen, the present invention performs a thermal annealing process after the formation of the first metal electrode 162, and because the first metal electrode 162 comprising nickel contacts the first portion 152A of the semiconductor material layer 150A but does not contact the second portion 154A of the semiconductor material layer 150A, the present invention can utilize a low temperature thermal annealing process to activate the p-type dopant in the first portion 152A of the semiconductor material layer 150A in contact with the first metal electrode 162 comprising nickel to convert the first portion 152A of the semiconductor material layer 150A into the first portion 152 of the semiconductor material layer 150 having a high concentration of holes, whereas the low temperature thermal annealing process activates the second portion 154A of the semiconductor material layer 150A that is not in contact with nickel to a lesser extent than the first portion 152A of the semiconductor material layer 150A that is in contact with nickel, and thus the first portion 152A of the semiconductor material layer 150A has a concentration of holes that is much greater than the second portion 150A. It should be noted that "the activation degree of the second portion 154A of the semiconductor material layer 150A is smaller than the activation degree of the first portion 152A of the semiconductor material layer 150A" herein includes an embodiment in which both the first portion 152A and the second portion 154A of the semiconductor material layer 150A are activated and the activation degree of the second portion 154A is smaller than the activation degree of the first portion 152A, and an embodiment in which the first portion 152A of the semiconductor material layer 150A is activated and the second portion 154A is not activated. In addition, since the first portion 152A of the semiconductor material layer 150A is activated and the second portion 154A of the semiconductor material layer 150A is activated to a much smaller extent than the first portion 152A of the semiconductor material layer 150A after the thermal annealing process, the hole concentration of the first portion 152 of the semiconductor layer 150 is greater than the hole concentration of the first portion 152A of the semiconductor material layer 150A and the hole concentration of the second portion 154 of the semiconductor layer 150 is greater than or equal to the hole concentration of the second portion 154A of the semiconductor material layer 150A. For example, the hole concentration of the semiconductor material layer 150A is X (the hole concentrations of the first portion 152A and the second portion 154A of the semiconductor material layer 150A are also X), the hole concentration of the first portion 152 of the semiconductor layer 150 is Y, the hole concentration of the second portion 154 of the semiconductor layer 150 is Z, and then Y is greater than X, Z is greater than or equal to X, and Y is greater than Z. An annealing temperature of the thermal annealing process is in a range of 200 degrees celsius to 800 degrees celsius. Preferably, the annealing temperature may be selected in the range of 200 degrees celsius to 600 degrees celsius. More preferably, the annealing temperature may be selected to be in the range of 200 degrees celsius to 550 degrees celsius. For example, when the annealing temperature of the thermal annealing process is in the range of 200 degrees celsius to 550 degrees celsius, the first portion 152A of the semiconductor material layer 150A is activated to form the first portion 152 of the semiconductor layer 150 having an extremely high hole concentration, and the second portion 154A of the semiconductor material layer 150A is not activated such that the second portion 154 of the semiconductor layer 150 formed after the thermal annealing process has an extremely low hole concentration, and the ratio of the hole concentration of the first portion 152 of the semiconductor layer 150 to the hole concentration of the second portion 154 of the semiconductor layer 150 is greater than 10. In some embodiments, when the annealing temperature of the thermal annealing process is 600 degrees celsius, both the first portion 152A and the second portion 154A of the semiconductor material layer 150A are activated, and the degree of activation of the second portion 154A of the semiconductor material layer 150A is much smaller than the degree of activation of the first portion 152A of the semiconductor material layer 150A, so that the first portion 152A of the semiconductor material layer 150A is activated to form the first portion 152 of the semiconductor layer 150 having the extremely high hole concentration, and the second portion 154A of the semiconductor material layer 150A is activated to form the second portion 154 of the semiconductor layer 150 having the relatively low hole concentration, and the ratio of the hole concentration of the first portion 152 of the semiconductor layer 150 to the hole concentration of the second portion 154 of the semiconductor layer 150 is greater than 10. It should be noted that, referring to fig. 3 and 4, the channel layer 130 has a first portion 132 and a second portion 134, the first portion 132 of the channel layer 130 overlaps the first portion 152A (fig. 3) of the semiconductor material layer 150A or the first portion 152 (fig. 4) of the semiconductor layer 150 in a direction perpendicular to the substrate 110 (e.g., the first direction D1), and the second portion 134 of the channel layer 130 overlaps the second portion 154A (fig. 3) of the semiconductor material layer 150A or the second portion 154 (fig. 4) of the semiconductor layer 150 in a direction perpendicular to the substrate 110. In fig. 3, since the semiconductor material layer 150A has not been activated yet, there is a two-dimensional electron gas 2DEG (not shown) in both the first portion 132 and the second portion 134 of the channel layer 130; in fig. 4, because the semiconductor material layer 150A is subjected to the thermal annealing process to be converted into the semiconductor layer 150, and the hole concentration of the first portion 152 of the semiconductor layer 150 is greater than that of the second portion 154 of the semiconductor layer 150, the two-dimensional electron gas 2DEG of the first portion 132 of the channel layer 130 under the first portion 152 of the semiconductor layer 150 in the first direction D1 is depleted without the two-dimensional electron gas 2DEG, and the second portion 134 of the channel layer 130 under the second portion 154 of the semiconductor layer 150 in the first direction D1 is still provided with the two-dimensional electron gas 2DEG (not shown), that is, the two-dimensional electron gas 2DEG of the first portion 132 of the channel layer 130 is cut off to form the enhanced semiconductor device, and the second portion 134 of the channel layer 130 is still provided with the two-dimensional electron gas 2DEG so that when the gate electrode 160 is applied with the two-dimensional electron gas cut-off region greater than the threshold voltage to generate electrons under the gate electrode 160, the two-dimensional electron gas cut-off region of the second portion 134 of the channel layer 130 is connected to form the semiconductor device. Therefore, in the present invention, the thermal annealing process is performed after the gate electrode 160 is formed, and the temperature is selected such that the second portion 154A of the semiconductor material layer 150A is activated to a lesser extent than the first portion 152A of the semiconductor material layer 150A, so that after the semiconductor material layer 150A is converted into the semiconductor layer 150 by the thermal annealing process, the second portion 154 of the semiconductor layer 150 has a very small hole concentration, such that the second portion 134 of the channel layer 130 under the second portion 154 of the semiconductor layer 150 still has a two-dimensional electron gas 2DEG, and thus the second portion 154 of the semiconductor layer 150 is not removed any more to form the enhanced semiconductor device, thereby saving the process steps and avoiding the damage of the underlying channel layer 130 during the etching and removing step.
The difference in activation is such that the hole concentration of the first portion 152 of the semiconductor layer 150 is higher than the hole concentration of the second portion 154 of the semiconductor layer 150, e.g., by a number higher than the hole concentration of the second portion 154, i.e., the ratio of the hole concentration of the first portion 152 to the hole concentration of the second portion 154 is greater than 10. Thereby, the first portion 152 of the semiconductor layer 150 forms a P-type semiconductor such that the gate electrode 160 forms an ohmic contact with the first portion 152 of the semiconductor layer 150, and the first portion 152 of the semiconductor layer 150 may form a semiconductor device as an enhancement type semiconductor device. On the other hand, the second portion 154A of the semiconductor material layer 150A that is not substantially activated or has a low degree of activation may be considered to be substantially electrically insulating without affecting the operation of the device and without being removed. In some embodiments, when the semiconductor material layer 150A is AlGaN: the first portion 152 of the semiconductor layer 150 can be regarded as P after the thermal annealing process during Mg + AlGaN, and the second portion 154 of the semiconductor layer 150 may be regarded as AlGaN: mg, but not limited thereto.
The temperature of the thermal annealing process of the present invention may be selected such that the first portion 152A and the second portion 154A of the semiconductor material layer 150A are activated to the same or similar extent if the temperature of the thermal annealing process is too high (e.g., over 800 degrees celsius), such that the difference in hole concentration between the first portion 152 and the second portion 154 of the semiconductor layer 150 cannot be generated. On the other hand, if the temperature of the thermal annealing process is too low (e.g., less than 200 degrees celsius), both the first portion 152A and the second portion 154A of the semiconductor material layer 150A may not be activated, and the enhanced semiconductor device may not be formed. Therefore, the second portion 154A of the semiconductor material layer 150A is activated less than the first portion 152A of the semiconductor material layer 150A by selecting the appropriate annealing temperature, and the second portion 154A of the semiconductor material layer 150 does not need to be removed, which is helpful for forming the enhanced semiconductor device.
In the prior art, after depositing a p-doped semiconductor material layer on the active layer and before forming the gate electrode, a p-doped activation step is performed on the p-doped semiconductor material layer, for example, a thermal annealing process or low-energy electron beam irradiation is performed to activate the p-doped semiconductor material layer, so that the p-doped semiconductor material layer forms a p-type semiconductor layer with a high hole concentration. Since the portion of the p-type semiconductor layer that is not overlapped with the gate electrode is removed to avoid that the enhancement-type semiconductor device cannot be turned on, the portion of the p-type semiconductor layer that is not overlapped with the subsequent gate electrode is then etched and removed, and the portion of the p-type semiconductor layer that is not overlapped with the subsequent gate electrode is not etched and removed and remains. And forming a gate electrode on the part of the p-type semiconductor layer which is not etched and removed to form the enhanced semiconductor device. Therefore, in the prior art, an etching process is required to etch and remove the portion of the p-type semiconductor layer that is not overlapped with the gate electrode, and the etching process usually damages the active layer under the p-type semiconductor layer, resulting in degradation of the characteristics of the enhanced semiconductor device.
The invention can save process steps and solve the problem of active layer damage caused by etching the semiconductor layer in the prior art. In the present invention, the portion of the semiconductor layer 150 that does not overlap the gate electrode 160 (i.e., the second portion 154 of the semiconductor layer 150) is not etched away, but rather, after the formation of the p-doped semiconductor material layer 150A on the active layer 140 and before the formation of the gate electrode 160, a dopant activation process is not performed, and after the formation of the gate electrode 160, a thermal annealing process is performed to activate the dopants in the first portion 152A of the semiconductor material layer 150A, wherein the gate electrode 160 includes a first metal electrode 162 in contact with the first portion 152A of the semiconductor material layer 150A, and the first metal electrode 162 includes nickel. Because nickel enhances desorption of hydrogen in the first portion 152A of the semiconductor material layer 150A to increase hole concentration when the nickel contacts the first portion 152A of the P-doped semiconductor material layer 150A, the present invention employs an optimized temperature during the thermal annealing process such that the first portion 152A of the semiconductor layer 150A contacting the first metal electrode 162 of the gate electrode 160 is activated to a greater extent than the second portion 154A of the semiconductor layer 150A not contacting the first metal electrode 162 of the gate electrode 160, i.e., after the thermal annealing process of the present invention, the semiconductor layer 150A is converted into the semiconductor layer 150, and the hole concentration of the first portion 152 of the semiconductor layer 150 is substantially greater than the hole concentration of the second portion 152 of the semiconductor layer 150, so the first portion 152 of the semiconductor layer 150 may be a P-type semiconductor layer, and the second portion 154 of the semiconductor layer 150 may be regarded as substantially electrically insulating. Because the second portion 154 of the semiconductor layer 150 is considered to be substantially electrically insulating, the present invention does not require etching to remove the second portion 154 of the semiconductor layer 150, and thus does not cause the active layer damage caused by etching the semiconductor layer as in the prior art. In addition, because the nickel in the invention can enhance the desorption of hydrogen to increase the hole concentration when contacting the semiconductor layer doped with p-type dopant, the temperature of the thermal annealing process in the invention is far less than that of the thermal annealing process in the activation step in the prior art, so that the time for raising and lowering the temperature of the machine is shortened to reduce the manufacturing cost.
Next, referring to fig. 5, after the thermal annealing process, a portion of the second portion 154 of the semiconductor layer 150, the active layer 140 and the channel layer 130 are etched to form a source recess RS and a drain recess RD, which penetrate the second portion 154 of the semiconductor layer 150 and the active layer 140, and the channel layer 130 is exposed by the source recess RS and the drain recess RD. As shown, the etching process further etches a portion of the channel layer 130 in the second direction D2, that is, the bottoms of the source recess RS and the drain recess RD are lower than the upper surface of the channel layer 130, so as to further reduce the on-resistance between the drain 170D and the source 170S formed later, but not limited thereto.
Referring to fig. 6, a source SE and a drain DE are formed in the source recess RS and the drain recess RD, respectively. The drain 170D and the source 170S may comprise an appropriate metal as electrodes. For example, the formation of the drain 170D and the source may be accomplished by suitable deposition methods (e.g., PVD, ALD, or combinations thereof) and removal methods (e.g., etching, polishing, or metal stripping, etc.).
Through the above-described process steps, the semiconductor device 100 can be formed. In the process of the present embodiment, the gate electrode 160 is formed by using a metal lift-off process (metal lift-off), and the gate electrode 160 is formed without using an etching metal layer, so that the problem that the etching depth of the etching metal layer is difficult to control can be avoided. Furthermore, since the second portion 154 of the semiconductor layer 150 has a low hole concentration and is thus considered to be insulating, it is not necessary to etch the second portion 154 of the semiconductor layer 150, and thus the problem that the underlying active layer is damaged by etching (e.g., the problem of current collapse due to surface charge trapping electrons) can be avoided.
Fig. 7A is a schematic cross-sectional view of a semiconductor device 100' according to some embodiments of the present disclosure. The semiconductor device 100 'of the present embodiment may include a substrate 110, a nucleation buffer layer 120, a channel layer 130, an active layer 140, a semiconductor layer 150', a gate electrode 160, and a drain 170D and a source 170S. The semiconductor device 100' of the present embodiment is similar to the semiconductor device 100 of fig. 1 to 6, with the difference that: the present embodiment employs a graded doped metal semiconductor layer 150' in order to achieve ohmic contact with the gate electrode 160 thereon and to have a matched lattice constant with the underlying semiconductor layer (e.g., the active layer 140). Details of other elements of the present embodiment are generally as described above, and are not repeated here. Similar to fig. 1A, fig. 7A shows the semiconductor device 100 'in a state where the gate electrode 160 is biased with a voltage greater than a threshold voltage and the semiconductor device 100' is turned on. The state of the semiconductor device 100 'when the gate electrode 160 is biased to be less than the threshold voltage or not biased and the semiconductor device 100' is turned off (i.e., is not turned on) may refer to fig. 1B, and will not be described herein.
In some embodiments, the semiconductor layer 150' may include Al x Ga (1-x) N layers, where x is greater than or equal to 0 and less than 1, and x decreases in a direction perpendicular to the substrate and toward the gate electrode (e.g., first direction D1). For example, in some embodiments, al x Ga (1-x) X in the N layer may taper to 0 in a direction perpendicular to the substrate and toward the gate electrode 160 such that the upper end 150T of the semiconductor layer 150 'substantially comprises GaN Mg and the lower end 150B of the semiconductor layer 150' substantially comprises AlGaN Mg. As such, an aluminum composition of the semiconductor layer 150 'adjacent to the upper end 150T of the active layer 140 is lower than an aluminum composition of the semiconductor layer 150' adjacent to the lower end 150B of the gate electrode 160. Thereby, the material of the upper end 150T of the semiconductor layer 150 '(e.g., gaN: mg) is more likely to form an ohmic contact with the contacted nickel metal than the material of the lower end 150B of the semiconductor layer 150' (e.g., alGaN: mg). On the other hand, by the graded doping, the material (e.g., gaN: mg) at the upper end 150T of the semiconductor layer 150 'has a first lattice constant, and the material (e.g., alGaN: mg) at the lower end 150B of the semiconductor layer 150' has a second lattice constant, wherein the second lattice constant is closer to a lattice constant of the active layer 140 (e.g., alGaN) than the first lattice constant. Therefore, the leakage caused by lattice mismatch between the lower end 150B of the semiconductor layer 150' and the active layer 140 can be reduced, and the confinement of the channel carrier can be improved. For example, the semiconductor layer 150' may include Al x Ga (1-x) N layers, x being greater than or equal to 0 and less than 1, x decreasing in a direction perpendicular to the substrate 110 and toward the gate electrode 160 (e.g., first direction D1), the active layer 140 may comprise Al y Ga (1-y) N layer, y is greater than 0 and less than 1, in order to reduce lattice mismatch between semiconductor layer 150' and active layer 140, inX is equal to y at the junction of the semiconductor layer 150' and the active layer 140; in order to form an ohmic contact of the semiconductor layer 150 'with the gate electrode 160, x is equal to 0 at the junction of the semiconductor layer 150' with the first metal electrode 162 of the gate electrode 160.
As before, after the thermal annealing process of the present invention, the semiconductor material layer is converted into the semiconductor layer 150', and the first portion 152' and the second portion 154 'of the semiconductor layer 150' have a hole concentration difference, for example, a hole concentration difference of at least one order of magnitude or more. In detail, the upper end 152T of the first portion 152' can be regarded as P + The lower end 152B of the GaN first portion 152' may be considered P + AlGaN, the upper end 154T of the second portion 154 'may be considered GaN to Mg, and the lower end 154B of the second portion 154' may be considered AlGaN to Mg, but is not limited thereto.
In this embodiment, aluminum gallium nitride as the semiconductor layer 150' may be epitaxially deposited to grow with a decreasing aluminum composition. The other process steps of the semiconductor device 100 'of the present embodiment are substantially the same as those of the semiconductor device 100' of fig. 2 to 6, and are not repeated here.
Fig. 7B is a heterostructure band diagram of the semiconductor device of fig. 7A. The conduction band E of the semiconductor layer 150', the active layer 140 and the channel layer 130 is shown C And valence band E V . Specifically, the semiconductor layer 150' depicted in fig. 7B is a first portion 152' of the semiconductor layer 150 '. The semiconductor layer 150' may include Al x Ga (1-x) N layers, x is greater than or equal to 0 and less than 1, x decreases in a direction perpendicular to the active layer 140 and away from the active layer 140, such that the energy gap of the semiconductor layer 150' decreases. The active layer 140 may include Al y Ga (1-y) N layers, y is greater than 0 and less than 1. X is equal to y at the junction of semiconductor layer 150 'and active layer 140 to reduce the lattice mismatch of semiconductor layer 150' and active layer 140.
In the embodiments of the present invention, the activation degree of the doped semiconductor layer under the gate metal electrode can be locally enhanced only by the arrangement of the gate metal electrode, and the step of removing the doped semiconductor layer by etching can be omitted in the design of the process step, so that the on-voltage stability and reliability stability of the semiconductor device are improved. In a further more recent embodiment, when the doped semiconductor layer and the active layer comprise similar materials (e.g., comprise the same metal element (e.g., aluminum)), the concentration of the metal element (e.g., aluminum) in the doped semiconductor layer may be set to epitaxially grow in a decreasing manner, resulting in a graded concentration profile of the metal element (e.g., aluminum) in the doped semiconductor layer. Therefore, on one hand, the lower end of the doped semiconductor layer can be lattice matched with the active layer so as to reduce electric leakage caused by lattice mismatch with the active layer and improve the limitation of conductive carriers, and on the other hand, the upper end of the doped semiconductor layer can be easy for the grid metal electrode to form ohmic contact.
The features of various embodiments are summarized above. It should be appreciated by those skilled in the art that the invention may be embodied or carried out in a variety of ways, including as a matter of design or modification of other processes or structures, and that various changes, substitutions, and alterations are possible and are within the spirit and scope of the invention herein.

Claims (10)

1. A semiconductor device, comprising:
a channel layer;
an active layer on the channel layer;
a semiconductor layer on the active layer, wherein the semiconductor layer comprises a P-type dopant;
a gate electrode on the semiconductor layer, the gate electrode comprising a first metal electrode, and a material of the first metal electrode comprising nickel, wherein the first metal electrode contacts a first portion of the semiconductor layer, the first metal electrode does not contact a second portion of the semiconductor layer, and a hole concentration of the first portion of the semiconductor layer is higher than a hole concentration of the second portion of the semiconductor layer; and
a drain electrode and a source electrode respectively connected with two sides of the channel layer.
2. The semiconductor device of claim 1, wherein the p-type dopant comprises magnesium.
3. The semiconductor device according to claim 1, wherein the semiconductor layer comprises a gallium nitride layer or an aluminum gallium nitride layer.
4. The semiconductor device of claim 1, wherein the active layer comprises an AlGaN layer and the semiconductor layer comprises Al x Ga (1-x) N layers, where x is greater than or equal to 0 and less than 1, and x decreases in a direction perpendicular to the substrate and toward the gate electrode.
5. The semiconductor device of claim 1, wherein a ratio of the hole concentration of the first portion of the semiconductor layer to the hole concentration of the second portion of the semiconductor layer is greater than 10.
6. A method of manufacturing a semiconductor device, comprising:
forming a channel layer on a substrate;
forming an active layer on the channel layer;
forming a semiconductor material layer on the active layer, wherein the semiconductor material layer comprises a P-type dopant;
forming a gate electrode on the semiconductor material layer, wherein the gate electrode comprises a first metal electrode, and the material of the first metal electrode comprises nickel, and the first metal electrode contacts a first part of the semiconductor material layer and the first metal electrode does not contact a second part of the first semiconductor material layer; and
after forming the gate electrode, a thermal annealing process is performed to convert the semiconductor material layer into a semiconductor layer, wherein the semiconductor layer has a first portion and a second portion, the first portion of the semiconductor layer overlaps the first metal electrode in a direction perpendicular to the substrate, the second portion of the semiconductor layer does not overlap the first metal electrode in a direction perpendicular to the substrate, and a hole concentration of the first portion of the semiconductor layer is higher than a hole concentration of the second portion of the semiconductor layer.
7. The method of claim 6, wherein the thermal annealing process activates the first portion of the semiconductor material layer more than the second portion of the semiconductor material layer.
8. The method of claim 7, wherein the hole concentration of the first portion of the semiconductor layer is greater than a hole concentration of the first portion of the semiconductor material layer, and the hole concentration of the second portion of the semiconductor layer is greater than or equal to a hole concentration of the second portion of the semiconductor material layer.
9. The method of claim 6, wherein an annealing temperature of the thermal annealing process is in a range of 200 degrees to 800 degrees.
10. The method as recited in claim 6, further comprising:
after the thermal annealing process, forming a source groove and a drain groove, wherein the source groove and the drain groove penetrate through the second part of the semiconductor layer and the active layer; and
and forming a source electrode and a drain electrode in the source electrode groove and the drain electrode groove respectively, wherein the source electrode groove and the drain electrode groove are contacted with the channel layer.
CN202111683255.9A 2021-12-22 2021-12-22 Semiconductor device and method for manufacturing the same Pending CN116344608A (en)

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