KR101935928B1 - High Electron Mobility Transistor having Reduced Gate Leakage Current - Google Patents

Abstract

The present invention relates to a high electron mobility transistor, and in particular, a high electron mobility transistor according to the present invention comprises a first III-V semiconductor; A second III-V semiconductor positioned adjacent to said first III-V semiconductor; A gate insulator located adjacent to said second III-V semiconductor; A gate electrode positioned on the gate insulator; And source and drain electrodes located on the second III-V semiconductor and spaced apart opposite to each other with the gate insulator interposed therebetween, the gate insulator comprising a p-type metal oxide, an intrinsic metal oxide, and a n-type metal oxide are successively laminated on the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high electron mobility transistor having a reduced gate leakage current,

The present invention relates to a high electron mobility transistor, and more particularly to a high electron mobility transistor with a significantly reduced gate leakage current and a normally-off characteristic.

GaN is a wide band-gap semiconductor with a band gap energy of 3.4 eV and has a characteristic of being suitable for high-temperature, high-voltage and high-output operation with a limit electric field strength of about 6 times higher than that of Si and a high electron saturation speed. Therefore, it has been attracting attention as a next-generation power semiconductor material which can replace Si that has already reached the characteristic limit inherent to the material.

In addition, the AlGaN / GaN heterojunction structure is very useful for a high-power or high-frequency semiconductor device because a high concentration 2DEG (2-dimensional electron gas) layer is formed at the interface due to spontaneous polarization and piezoelectric polarization phenomenon and energy band gap difference.

However, despite these advantages, devices based on the AlGaN / GaN heterojunction structure have a problem in that the circuit configuration becomes complicated and the cost increases as the 2DEG automatically performs a normally-on operation . When the thickness of AlGaN is reduced or the mole fraction of Al is decreased for the normally off-off operation, the concentration of 2DEG in the channel region also decreases, which increases the on-resistance.

In order to solve this problem, a method of implanting F ions on the surface of an AlGaN barrier (US Patent Publication No. 2010-0084687), a method of using a conductive metal oxide having a large work function as a gate electrode (Japanese Patent Laid- 149794), a recess gate structure (U.S. Patent Publication No. 2010-0025730), a method of implementing a normally-off state by a charge trapped in a gate insulating film, and a p-type gate structure have been proposed .

The p-type gate structure is a structure in which the p-type layer grown on AlGaN depletes the 2DEG channel to realize a normally-off operation. However, such a p-type gate structure has a problem that the gate leakage current is as high as about 10 ^-3 A / mm at a gate voltage of 6V. Thus, there has been an attempt to reduce the leakage current by using a metal which forms a high sort key barrier such as tungsten (W) on the p-type gate as a gate electrode. However, the leakage current is still reduced to 2x10 ^-5 A / mm It is required to develop a device capable of reducing the power loss by minimizing the gate leakage current.

U.S. Published Patent Application No. 2010-0084687 Japanese Patent Application Laid-Open No. 2007-149794 U.S. Published Patent Application No. 2010-0025730

It is an object of the present invention to provide a high electron mobility transistor (HEMT) having a significantly reduced gate leakage current and a normally-off operation.

It is another object of the present invention to provide a high electron mobility transistor having a significantly reduced gate leakage current and a normally off-off characteristic while having a low contact resistance.

A high electron mobility transistor (HEMT) according to the present invention comprises a first III-V semiconductor; A second III-V semiconductor positioned adjacent to the first III-V semiconductor; A gate insulator located adjacent to the second III-V semiconductor; A gate electrode positioned on the gate insulator; And source and drain electrodes located on the second III-V semiconductor and spaced apart opposite to each other with a gate insulator therebetween, the gate insulator comprising a p-type metal oxide, an intrinsic metal oxide, and an n-type metal And a laminated body of a pin structure in which oxides are sequentially stacked.

In a high electron mobility transistor according to an embodiment of the present invention, the p-type metal oxide of the gate insulator is a metal oxide of an intrinsic metal oxide doped with a p-type dopant, and the n-type metal oxide is doped with an n-type dopant Lt; / RTI > metal oxide.

In the high electron mobility transistor according to an embodiment of the present invention, the gate insulator may include a laminate of p-type ZnO, intrinsic ZnO, and n-type ZnO.

In the high electron mobility transistor according to an embodiment of the present invention, the p-type dopant of the p-type ZnO is one or more elements selected from among Sb, P, As and N, and the n-type dopant of the n- , Al, and In.

In the high electron mobility transistor according to an embodiment of the present invention, the electrode material of the gate electrode may be a metal that makes ohmic contact with the n-type metal oxide.

In the high electron mobility transistor according to an embodiment of the present invention, each of the first group III-V semiconductor and the second group III-V semiconductor may be a nitride semiconductor.

In a high electron mobility transistor according to an embodiment of the present invention, the first III-V semiconductor may be GaN, and the second III-V semiconductor may be AlGaN.

The high electron mobility transistor according to the present invention has the advantage of being capable of normally off-operating by a gate insulator of p-i-n structure, having a significantly reduced gate leakage current and a low contact resistance. Further, according to an advantageous example, when the pin structure is realized by ZnO of the same kind, deterioration of properties due to dopant diffusion can be prevented, and wet etching can be produced with high selectivity, And can be produced at a low cost. In addition, it can be manufactured by varying the type of the dopant to be supplied and the supply of the dopant only in the deposition process, which is advantageous in terms of commerciality.

1 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention,
2 is another cross-sectional view illustrating a cross section of a high electron mobility transistor according to an embodiment of the present invention.

Hereinafter, a high electron mobility transistor according to the present invention will be described in detail with reference to the accompanying drawings. The following drawings are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the following drawings, but may be embodied in other forms, and the following drawings may be exaggerated in order to clarify the spirit of the present invention. Hereinafter, the technical and scientific terms used herein will be understood by those skilled in the art without departing from the scope of the present invention. Descriptions of known functions and configurations that may be unnecessarily blurred are omitted.

A high electron mobility transistor according to the present invention comprises a first III-V semiconductor; A second III-V semiconductor positioned adjacent to the first III-V semiconductor; A gate insulator located adjacent to the second III-V semiconductor; A gate electrode positioned on the gate insulator; And a source electrode and a drain electrode positioned on the first III-V semiconductor and facing each other with a gate insulator interposed therebetween, wherein the gate insulator comprises a p-type metal oxide, an intrinsic metal oxide, and an n-type metal And a laminated body of a pin structure in which oxides are sequentially stacked.

The high electron mobility transistor according to the present invention can have a normally-off state due to the p-type metal oxide of the gate insulator located adjacent to the second III-V semiconductor, The gate leakage current can be significantly reduced by electrochemical constraints (including junctions and built-in potentials), and furthermore, the contact resistance with the gate electrode material can be reduced by the n-type metal oxide.

The p-type metal oxide of the gate insulator prevents the 2DEG from forming below the gate insulator, thereby enabling the transistor to normally operate-off, thereby enabling simplification of the circuit design. Further, the intrinsic metal oxide of the gate insulator can greatly reduce the gate leakage current together with the p-type metal oxide, which increases the resistance of the gate insulator in the off state to create a normally off state. In addition, since the gate insulator has a pin structure (pin diode structure), an external voltage is applied to the gate electrode so that the transistor is in a turn-on state (a state in which a positive voltage of more than a threshold voltage is applied to the gate electrode, , The gate insulator itself is biased in the reverse direction by the applied gate voltage Vgs. With this reverse biased p-i-n structure, the gate insulator has a very large impedance in turn-on state, which can significantly reduce gate leakage current in high voltage operation (power device) or high frequency operation (high frequency device). Also, as is known, the p-type metal oxide is difficult to be ohmic-bonded to the metal, and thus the contact resistance of the electrode is large. However, since the gate insulator has the p-i-n structure, the n-type metal oxide is electrically connected to the gate electrode material, so that the ohmic contact with various metals having excellent conductivity can be performed, thereby reducing the contact resistance of the electrode.

1 is a cross-sectional view illustrating a cross section of a high electron mobility transistor according to an embodiment of the present invention. As shown in FIG. 1, the second III-V semiconductor 200 may be disposed on the first III-V semiconductor 100 in contact with the first III-V semiconductor 100. The heterogeneous junction of the first III-V semiconductor 100 and the second III-V semiconductor 200 forms a conductive channel, referred to as a 2DEG.

The first III-V semiconductor 100 may be a first III-nitride semiconductor. Group III nitride semiconductors are more advantageous for power devices and high frequency devices due to their high energy bandgaps and their excellent current carrying capability. As an example of the first group III nitride semiconductor, the first group III nitride semiconductor may be a gallium-containing nitride, and more practically, a gallium nitride (GaN), which is a representative example of the first group III nitride semiconductor Wherein the first Group III nitride semiconductor is selected from the group consisting of aluminum nitride (AlN), indium nitride (InN), aluminum nitride indium (Al _x In _1-x N), and aluminum gallium nitride (Al _x Ga _1-x N) A real number greater than zero and less than one).

The second III-V semiconductor 200 has a band gap energy that is relatively larger than the band gap energy of the first III-V semiconductor 100 and is a III-V semiconductor having a composition different from that of the first III- Lt; / RTI > The second III-V semiconductor 200 may be a III-V semiconductor that has a relatively larger (larger) band gap energy than the first III-V semiconductor and can be lattice matched. The second group III-V semiconductor may also be a group III nitride semiconductor (second group III nitride semiconductor) in view of the large bandgap energy and lattice mismatch compared to the first group III-V semiconductor. The second group III nitride semiconductor may be aluminum nitride, aluminum gallium nitride (Al _x Ga _1-x N), or aluminum nitride indium (Al _x In _1-x N) based on gallium nitride, which is a representative example of the first group III nitride semiconductor. Lt; / RTI > However, the properties required according to the application may be that the second III-V semiconductor is a quaternary alloy such as In _x Ga _y Zn _{1-x y} O, or a group IV nitride such as Si _x N. Design changes of heterogeneous materials taking into account applications are a change in the generic tolerance of compound semiconductor device workers.

The gate insulator 300 may be disposed on the second III-V semiconductor 200 in contact with the second III-V semiconductor 200. As described above, the gate insulator 300 may include a stack of p-i-n structures in which p-type metal oxide 310, intrinsic metal oxide 320, and n-type metal oxide 330 are sequentially stacked. In this case, the p-type metal oxide 310 is located on the side of the second III-V semiconductor 200, and the n-type metal oxide 330 is located on the gate electrode 400 side.

When the transistor turns on, the size in the direction of the current flow is called the length, and the size in the direction perpendicular to the length is called the width. The gate insulator has a length and width (designed to correspond to the distance and width between the source electrode and the drain electrode Of course, the physical dimensions can be determined. In a specific, non-limiting example, the length of the gate insulator is relatively smaller than the length of the channel, but can be stably long enough to interrupt the 2DEG, and the width of the gate insulator is relatively greater than the width of the channel, It is enough to stop the 2DEG.

As described above, in the state where the 2DEG is naturally formed by the hetero-junction of the first III-V semiconductor 100 and the second III-V semiconductor 200, the p-type metal oxide 310 of the gate insulator 300 Off state can be realized by stopping the 2DEG by depletion of the gate insulator 300 by the lower depletion of the gate insulator 300. [ In addition, since the gate insulator 300 includes the pin structure in which the p-type metal oxide 310 -the phosphorus-based metal oxide 320-the n-type metal oxide 330 are stacked, The gate leakage current can be remarkably reduced, and the contact resistance with the gate electrode can be lowered.

It is advantageous that the p-type metal oxide 310 -indenthalloy metal oxide 320 -n-type metal oxide 330 forming the p-i-n structure in the gate insulator 300 is a homogeneous metal oxide. That is, the p-type metal oxide 310 of the gate insulator 300 is a metal oxide of an intrinsic metal oxide doped with a p-type dopant, and the n-type metal oxide 330 is an oxide of an intrinsic metal oxide doped with an n-type dopant It is advantageous to be a metal oxide. In an advantageous example, the p-i-n structure is of course a p-i-n structure by homojunction.

When a p-i-n structure is formed by a metal oxide of the same kind, a gate insulator 300 having a p-i-n structure can be realized by using a metal oxide having an excellent etching selectivity to the second III-V semiconductor. In the case of a high electron mobility transistor, the surface damage or defect of the heterojunction semiconductor greatly affects the performance of the device. Therefore, when the pin structure is realized by the same kind of metal oxide having excellent etching selectivity, It is advantageous to realize a gate insulator having a dimension designed through the gate insulator.

Further, when a pin structure is formed by a metal oxide of the same type, a metal oxide is deposited on the second III-V semiconductor, and the implementation of the pin structure is performed by varying the dopant supply or dopant material in deposition. It is possible. Implementation of the p-i-n structure through a single deposition process can improve process reproducibility and reliability, and can significantly improve the productivity by shortening the time required for the gate insulator process.

Further, when the p-i-n structure is formed by the same kind of metal oxide, it is advantageous that the element which does not diffuse well to the III-V semiconductor, specifically, the group III nitride semiconductor is a p-type dopant. As is known, in the case of p-type GaN or p-type AlGaN used for the conventional p-type gate, not only a problem of dry etching having a large damage but also a problem of causing deterioration of the device due to high diffusibility of p- have.

III-V semiconductors, particularly III-nitride semiconductors, has an excellent etching selectivity (etch selectivity in wet etching) and is easily controlled to n-type or p-type by a dopant, and III-V semiconductors ZnO is a metal oxide having a p-type dopant as an element which is not well diffused into a group III nitride semiconductor. That is, as an advantageous typical example, the p-type metal oxide, the intrinsic metal oxide, and the n-type metal oxide may be p-type ZnO, intrinsic ZnO (intrinsically undoped intrinsic ZnO), and n-type ZnO.

Furthermore, in the case of ZnO, the electrical characteristics can be easily controlled through doping of the dopant without a large deformation of the lattice size, so that the internal defects of the gate insulator can be minimized, and interface defects of the p-i-n structure can be minimized. Quality gate insulators whose internal defects are minimized can prevent deterioration of characteristics of devices due to charge traps and the like.

In addition, since ZnO has a low cost for raw materials compared with p-type GaN or p-type AlGaN used in conventional p-type gates, it is more excellent in commercial performance.

As is known, the p-type dopant of p-type ZnO may be an element selected from one or more elements selected from Group 5 elements, specifically, Sb, P, As and N. At this time, since the p-type dopant easily substitutes for oxygen sites and exhibits stable p-type characteristics, it is possible to eliminate the adverse effect due to the diffusion of the p-type dopant due to the fact that a representative example of the second III-V semiconductor is a group III nitride It is advantageous to include nitrogen which can be used. That is, it is advantageous that the p-type ZnO is nitrogen-containing ZnO. One example of the doping concentration of p-type ZnO (p-type dopant concentration) is a concentration of 10 ¹⁷ / cm ³ to 10 ¹⁹ / cm ³ order, but is not limited thereto. The n-type dopant of the n-type ZnO may be one or more elements selected from Group 3 elements, specifically Ga, Al and In, and the n-type ZnO may be one or more elements selected from Ga, Al and In May be ZnO doped with the selected element. An example of the doping concentration of the n-type ZnO is a concentration of 10 ¹⁷ / cm ³ to 10 ²⁰ / cm ³ order, but the present invention is not limited thereto.

As described above, in the gate insulator 300, the p-type metal oxide 310 and the n-type metal oxide 330 are doped with 10 ¹⁷ / cm ³ to stop the 2DEG stably by depletion and reduce the gate- Lt; RTI ID = 0.0 > order. ≪ / RTI > Such a high concentration of doping is also advantageous in terms of preventing the size change of the depletion region in the gate insulator 300 by the driving voltage applied to the gate electrode in order to turn on the transistor.

The thickness of the n-type metal oxide 330 may be more than the depletion region width on the n-type side due to the pin junction in terms of stable ohmic contact formation with the gate electrode. In a specific, non-limiting example, when the width of the depletion region on the n-type metal oxide side due to the pin junction is denoted by W _n ⁱ in the n-type metal oxide 330, the thickness of the n-type metal oxide 330 is 1 W _n ⁱ to 50W _n ⁱ days, more specifically 2W _n ⁱ to 50W _n ⁱ , but is not limited thereto.

The width of the depletion region on the p-type metal oxide 310 side due to the junction with the second III-V semiconductor is set so that the thickness of the p-type metal oxide 310 can stably deplete the lower portion of the gate insulator, And the width of the depletion region on the p-type metal oxide 310 side due to the pin junction. In a specific and non-limiting example, the width of the depletion region on the p-type metal oxide side due to the junction with the second III-V semiconductor 200 in the p-type metal oxide 310 is W _p ^sem , The thickness of the p-type metal oxide 310 is 1 (W _p ^sem + W _p ⁱ ) to 50 (W _p ^sem + W _p ⁱ ), where W _p ⁱ is the width of the depletion region on the side of the _p- ), But is not limited thereto.

The thickness of the intrinsic metal oxide 320 may be appropriately changed in consideration of the use of a transistor such as a high-voltage device or a high-frequency device, and may be 5 nm to 100 nm in view of stably suppressing a gate leakage current, but is not limited thereto .

As shown in FIG. 1, the gate electrode 400 may be located on the gate insulator 300 including the p-i-n structure. The p-type metal oxide is a state in which the Fermi energy level is controlled by the p-type impurity so as to have a majority carrier of holes, and the metal (p-type) The ohmic contact is difficult, and it is also difficult to stably maintain the ohmic contact. Therefore, in the conventional p-type gate structure, it is common to perform a Schottky junction between the gate metal and the p-type insulator. However, in the case of the n-type metal oxide, the Fermi energy level is controlled by the n-type impurity so as to have the electron charge, and the ohmic contact with the metal having the work function smaller than the work function of the n- . Thus, the gate insulator has a pin structure, so that the gate electrode 400 can be connected to the n-type metal oxide 330 without being connected to the p-type material like the conventional p-type gate, And can have a low contact resistance.

As described above, the gate electrode material of the gate electrode 400 may be a metal that makes ohmic contact with the n-type metal oxide 330, as the gate insulator includes a p-i-n structure. Al, Pt, Au, Al, Zn, or their laminated films (Zn / Au, Al, Zn) as a typical gate electrode (material) in ohmic contact with n-type ZnO on the basis of n-type ZnO, Al / Au, Ti / Au, Ti / Al / Au, Ti / Al / Pt / Au). However, the present invention is not limited thereto.

The source electrode 510 and the drain electrode 520 may be positioned to be in contact with the second III-V semiconductor 200 and to face each other with the gate insulator 300 therebetween. The distance between the source electrode 510 and the drain electrode 520 may correspond to the channel length of the device so that the source electrode 510 and the drain electrode 520 may be spaced apart by a designed distance have. The source electrode 510 and the drain electrode 520 may be of a material and a structure conventionally used in a conventional nitride semiconductor-based high electron mobility transistor. The source electrode 510 and the drain electrode 520 may be formed of any one or more metal single layers selected from among Ta, Ti, Al, W, Ni, Mo, Pt and Au, Ti / Al / Mo / Au, Ti / Al / Ni / Au, Ti / Al / Pt / Au, etc.).

  2 is another cross-sectional view illustrating a cross section of a high electron mobility transistor according to an embodiment of the present invention. 2, a high electron mobility transistor is formed on the bottom of the first III-V semiconductor 100, and a substrate supporting the first III-V semiconductor 100 and its upper components The buffer layer 20 may further include a support 10 and may further include a buffer layer 20 disposed between the support 10 and the first III-V semiconductor 100.

The support 10 may be silicon, silicon carbide, sapphire, gallium nitride, gallium arsenide, or the like, but may be substantially larger in diameter and easier to obtain and may be integrated with other electronic devices This easy silicon is advantageous.

The buffer layer 20 reduces the lattice mismatch between the support 10 and the first III-V semiconductor 100 to form a first epitaxial structure having a hetero-epitaxial structure on the support 10. [ III-V semiconductors 100. [0034] The semiconductor device 100 of the present invention is not limited to the structure shown in FIG. As is known in the art of nitride semiconductor devices, the buffer layer 20 for relieving stress caused by lattice misfitting may include GaN, AlGaN, AlN, InGaAlN or a laminated layer thereof. However, when the support 10 is a bulk III-nitride semiconductor in which the III-V semiconductor can be epitaxially grown, it is needless to say that such a buffer layer 20 can be excluded.

The present invention includes a method of manufacturing the above-described high electron mobility transistor (HEMT).

A fabrication method according to the present invention comprises the steps of: a) forming a second III-V semiconductor on a first III-V semiconductor; b) forming a gate insulator comprising a laminate of a p-type metal oxide, an intrinsic metal oxide, and an n-type metal oxide on a second III-V semiconductor; And c) forming a source electrode and a drain electrode so as to face each other with a gate insulator therebetween, and forming a gate electrode over the gate insulator.

The step a) may be carried out in the form of an epitaxial film on a support (or a support with a buffer layer) such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE) V group semiconductors and second III-V group semiconductors can be used. In the conventional nitride semiconductor-based high electron mobility transistors, two semiconductors that form a 2DEG by heterojunction are used for manufacturing on a substrate Any known method may be used.

b) the step b1) comprises forming a laminated film of a p-type metal oxide film, an intrinsic metal oxide film and an n-type metal oxide film on a second III-V semiconductor, and b2) To form a gate insulator.

The step b1) is to form a gate insulating film in a semiconductor field such as sputter, pulsed laser deposition, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition Any method known to be used may be used. However, in the case where the pin structure is realized by a metal oxide of the same kind as described above, the step b1) may be performed by a one-step deposition process, and the dopant (or the dopant precursor containing the dopant element) And the dopant is injected or not, a laminated film can be produced.

Step b2) can be performed by wet etching using the etching mask that protects the designed gate region to remove the laminated film existing in the designed gate region. It goes without saying that the etching solution of the wet etching can be performed using a known etching solution of the metal oxide in consideration of the metal oxide of the laminated film. At this time, when the metal oxide is ZnO as described above, it is advantageous because it has excellent etching selectivity with respect to the III-V semiconductor.

Step c) may be performed by selectively depositing a metal in a region preliminarily designed as a gate, a source, and a drain region. Selective deposition may be performed using a deposition mask as is known, and deposition of the metal may be performed using conventional CVD or PVD.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Those skilled in the art will recognize that many modifications and variations are possible in light of the above teachings.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (7)

A first group III-V semiconductor;
A second III-V semiconductor positioned adjacent to said first III-V semiconductor;
A gate insulator located adjacent to said second III-V semiconductor;
A gate electrode positioned on the gate insulator; And
And source and drain electrodes located on the second III-V semiconductor and spaced apart from and opposite to each other with the gate insulator interposed therebetween,
Wherein the gate insulator comprises a laminate of a pin structure in which p-type ZnO, undoped intrinsic ZnO and n-type ZnO are sequentially laminated.
delete delete The method according to claim 1,
The p-type dopant of the p-type ZnO is one or more elements selected from Sb, P, As and N, and the n-type dopant of the n-type ZnO is one or more elements selected from Ga, Al and In Electron mobility transistor. The method according to claim 1,
Wherein the electrode material of the gate electrode is ohmic contact metal with the n-type ZnO. The method according to claim 1,
Wherein the first III-V semiconductor and the second III-V semiconductor are each a nitride semiconductor. The method according to claim 1,
Wherein the first III-V semiconductor is GaN, and the second III-V semiconductor is AlGaN.

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