JP2010171416A - Semiconductor device, manufacturing method therefor, and leakage-current reduction method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a withstanding-voltage characteristic and reducing the leakage current, and to ptovide a manufacturing method therefor, and a method for reducing a leakage current thereof. <P>SOLUTION: An HFET (high field-effect transistor) 100 is equipped with a sapphire substrate 101 that serves as a support substrate; a buffer layer 102 on the sapphire substrate 101; a carrier-moving layer 103 on the buffer layer 102; a carrier-supplying layer 104 on the carrier-moving layer 103; a source 106s and a drain 106d remotely formed on the carrier-supplying layer 104; a gate 107 formed on the carrier-supplying layer 104 in between the source 106s and the drain 106d; and an insulating film 105 covering over the carrier-supplying layer 104. The carrier-supplying layer 104 has a carbon concentration that exceeds 2×10<SP>17</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a method for reducing leakage current of a semiconductor device, and more particularly, a semiconductor device including compound semiconductor layers having different band gap energies that form a heterojunction interface that generates a two-dimensional electron gas, The present invention relates to a semiconductor device manufacturing method and a semiconductor device leakage current reducing method.

  Conventionally, an electronic device formed using a nitride-based compound semiconductor has been regarded as promising as a high-voltage element or a high-speed operation element because of the characteristics inherently possessed by compound semiconductor materials such as direct transition. As such an electronic device, in recent years, there is a high electron mobility transistor (hereinafter simply referred to as HEMT), which is a kind of field effect transistor (hereinafter simply referred to as FET). The HEMT has, for example, a stacked structure of a carrier traveling layer made of a nitride compound semiconductor and a carrier supply layer made of a nitride compound semiconductor having a band gap energy larger than that of the carrier traveling layer, and a heterojunction in this stacked structure. A two-dimensional electron gas generated near the interface is used as a carrier (for example, see Patent Document 1 shown below).

  Among the electronic devices having the laminated structure as described above, MESFETs (Metal Semiconductor FETs) and HFETs (Heterojunction FETs) using a GaN (gallium nitride) based semiconductor are particularly in the microwave band and the rewave. It is considered effective to be used as a band power device and is expected to be applied to highly efficient inverters and converters.

  In order to realize highly efficient inverters and converters using GaN-based semiconductors, it is necessary to develop electronic devices that are small and have high reliability and low loss. Therefore, in this type of semiconductor device, it is important to improve the breakdown voltage between the gate and the drain, increase the carrier density of the channel layer, and reduce the contact resistance.

  For example, as a method for improving the breakdown voltage between the gate and the drain, it is conceivable to increase the resistance between the source and the drain at the off time by increasing the resistance of the carrier supply layer. However, when, for example, a mixed crystal AlGaN layer is used as the carrier supply layer, since Al atoms are in an active state, n-type impurities such as oxygen can be easily taken in, and there is a problem that leakage current increases. Therefore, conventionally, the p-type impurities such as Mg (magnesium) and Fe (iron) are doped in the GaN layer and the AlGaN layer to compensate for the incorporated n-type impurities and to improve the resistance of the carrier supply layer. Increasing the value was done.

JP 2003-197643 A

  However, impurities such as Mg and Fe are likely to diffuse in the film and cause problems such as deflection to the surface. Furthermore, current collapse, which is a phenomenon that deteriorates the reproducibility of output current characteristics, is likely to occur. For this reason, in the method of doping impurities such as Mg and Fe into the carrier supply layer, there is a problem that it is difficult to realize an electronic device having stable operating characteristics.

  The present invention has been made in view of the above problems, and provides a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device leakage current reduction method capable of improving withstand voltage characteristics and reducing leakage current. The purpose is to provide.

To achieve this object, a semiconductor device according to the present invention is formed on at least a part of a first compound semiconductor layer made of a nitride-based compound semiconductor and the first compound semiconductor layer, and the first compound semiconductor layer A second compound semiconductor layer made of a nitride-based compound semiconductor having a larger band gap energy than the second compound semiconductor layer, the carbon concentration of the second compound semiconductor layer being 2 × 10 ¹⁷ cm ⁻³ or more, and carbon When a metal film having a concentration of 1 × 10 ²⁰ cm ⁻³ or less and forming a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, the reverse bias voltage is 200 V. The reverse leakage current is 1 × 10 ⁻⁴ A / cm ² or less.

The above-described semiconductor device according to the present invention is formed in at least a part of the first compound semiconductor layer made of a nitride compound semiconductor and the first compound semiconductor layer, and has a band gap energy higher than that of the first compound semiconductor layer. A second compound semiconductor layer made of a large nitride-based compound semiconductor, wherein the second compound semiconductor layer has a carbon concentration of 4 × 10 ¹⁷ cm ⁻³ or more and a carbon concentration of 1 × 10 ^20. cm ^-3 or less, the case of forming a metal film forming the Schottky interface between the second compound semiconductor layer on the second compound semiconductor layer, the reverse direction when the reverse bias voltage is 200V The leakage current is 1 × 10 ⁻⁶ A / cm ² or less.

In the semiconductor device according to the present invention, the first compound semiconductor layer is made of Al _x1 In _y1 Ga _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, x1 + y1 ≦ 1). The two-compound semiconductor layer is made of Al _x2 In _y2 Ga _1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, x2 + y2 ≦ 1) having a larger band gap energy than the first compound semiconductor layer. It is characterized by.

  The semiconductor device according to the present invention is a diode or a field effect transistor.

  In the semiconductor device according to the present invention, the first compound semiconductor layer made of a nitride compound semiconductor is formed directly on a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or the silicon It is characterized by being formed on a buffer layer provided on the substrate, the sapphire substrate, the silicon carbide substrate, or the gallium nitride substrate.

In addition, a method for manufacturing a semiconductor device according to the present invention includes a first compound semiconductor layer forming step of forming a first compound semiconductor layer made of a nitride-based compound semiconductor on a support substrate, and a carbon on the first compound semiconductor layer. A nitride-based compound semiconductor having a concentration of 2 × 10 ¹⁷ cm ⁻³ or more and a carbon concentration of 1 × 10 ²⁰ cm ⁻³ or less and a band gap energy larger than that of the first compound semiconductor layer. A second compound semiconductor layer forming step of forming a two compound semiconductor layer, and a metal film that forms a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, The reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ⁻⁴ A / cm ² or less.

The above-described method for manufacturing a semiconductor device according to the present invention includes a first compound semiconductor layer forming step of forming a first compound semiconductor layer made of a nitride compound semiconductor on a support substrate, and a carbon on the first compound semiconductor layer. A nitride-based compound semiconductor having a concentration of 4 × 10 ¹⁷ cm ⁻³ or more and a carbon concentration of 1 × 10 ²⁰ cm ⁻³ or less and a band gap energy larger than that of the first compound semiconductor layer. A second compound semiconductor layer forming step of forming a two compound semiconductor layer, and a metal film that forms a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, The reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ⁻⁶ A / cm ² or less.

  In the method of manufacturing a semiconductor device according to the present invention, the second compound semiconductor layer forming step includes doping carbon atoms during the growth of the compound semiconductor film having a larger band gap energy than the first compound semiconductor layer, Either a method of doping carbon atoms into the compound semiconductor film by ion implantation after growing the compound semiconductor film, or a method of doping carbon atoms into the compound semiconductor film by thermal diffusion after growing the compound semiconductor film The second compound semiconductor layer is formed.

According to another aspect of the present invention, there is provided a method for reducing a leakage current of a semiconductor device comprising: a first compound semiconductor layer made of a nitride compound semiconductor; and a first compound semiconductor layer formed on at least a part of the first compound semiconductor layer. even leakage current reducing method of a semiconductor device including a second compound semiconductor layer band gap energy is made of a high nitride-based compound semiconductor, a, the second compound semiconductor layer, a concentration of 2 × 10 ¹⁷ cm ^-3 Carbon is doped so as to be 1 × 10 ²⁰ cm ⁻³ or less. As a result, by forming a metal film that forms a Schottky interface with the second compound semiconductor layer on the second compound semiconductor layer, the reverse leakage current when the reverse bias voltage is 200 V is obtained. It can be set to 1 × 10 ⁻⁴ A / cm ² or less.

According to the present invention, in the second compound semiconductor layer made of a nitride-based compound semiconductor, for example, problems such as diffusion in the film and deflection to the surface and current collapse problems occur compared to Mg and Fe. Since carbon (C) that is difficult to be doped is doped at 2 × 10 ¹⁷ cm ⁻³ or more, it is possible to realize a semiconductor device having a stable operating characteristic and a method for manufacturing the semiconductor device. In addition, the second compound semiconductor layer and the metal that form the Schottky interface when the carbon concentration in the second compound semiconductor layer is 1 × 10 ²⁰ cm ⁻³ or less and the reverse bias voltage between the source and the drain is 200 V. Since the reverse leakage current flowing through the film is 1 × 10 ⁻⁴ A / cm ² or less, it is possible to realize a semiconductor device and a method for manufacturing the semiconductor device that can obtain sufficient breakdown voltage characteristics.

FIG. 1 is a cross-sectional view showing the layer structure of an HFET according to Embodiment 1 of the present invention. FIGS. 2-1 is a figure which shows the manufacturing process of HFET by Embodiment 1 of this invention (the 1). FIGS. 2-2 is a figure which shows the manufacturing process of HFET by Embodiment 1 of this invention (the 2). FIGS. 2-3 is a figure which shows the manufacturing process of HFET by Embodiment 1 of this invention (the 3). FIGS. 2-4 is a figure which shows the manufacturing process of HFET by Embodiment 1 of this invention (the 4). FIG. 3 is a diagram showing a manufacturing process of the HFET according to the first modification of the first embodiment of the present invention. FIG. 4 is a diagram showing a manufacturing process of the HFET according to the second modification of the first embodiment of the present invention. FIG. 5 is a diagram showing the relationship between the carbon (C) concentration in the carrier supply layer and the gate leakage current in the HFET according to the first embodiment of the present invention. FIG. 6 is a sectional view showing the layer structure of the SBD according to the second embodiment of the present invention. FIGS. 7-1 is a figure which shows the manufacturing process of SBD by Embodiment 2 of this invention (the 1). FIGS. 7-2 is a figure which shows the manufacturing process of SBD by Embodiment 2 of this invention (the 2).

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following description, each drawing only schematically shows the shape, size, and positional relationship to the extent that the contents of the present invention can be understood. Therefore, the present invention is illustrated in each drawing. It is not limited to only the shape, size, and positional relationship. Moreover, in each figure, a part of hatching in a cross section is abbreviate | omitted for clarification of a structure. Furthermore, the numerical values exemplified below are merely preferred examples of the present invention, and therefore the present invention is not limited to the illustrated numerical values.

<Embodiment 1>
Hereinafter, an HFET 100 as a semiconductor device according to the present invention will be described in detail with reference to the drawings.

(Constitution)
FIG. 1 is a cross-sectional view showing the layer structure of the HFET 100 according to the present embodiment. FIG. 1 shows a cross-sectional structure when the HFET 100 is cut along a plane that is perpendicular to the upper surface of the sapphire substrate 101 that is a support substrate and is parallel to the channel length direction.

  As shown in FIG. 1, the HFET 100 includes a sapphire substrate 101 as a support substrate, a buffer layer 102 on the sapphire substrate 101, a carrier traveling layer 103 (first compound semiconductor layer) on the buffer layer 102, and a carrier traveling layer. 103, a carrier supply layer 104 (second compound semiconductor layer) on the source 103, a source electrode 106s and a drain electrode 106d provided on the carrier supply layer 104, and a source electrode 106s and a drain electrode 106d on the carrier supply layer 104. And an insulating film 105 covering the carrier supply layer 104.

  As the support substrate, various substrates such as a silicon (111) substrate, a silicon carbide (SiC) substrate, and a gallium nitride (GaN) substrate can be used in addition to the sapphire substrate 101.

  The buffer layer 102 is a layer for buffering the interaction caused by the difference in lattice constant between the carrier traveling layer 103 grown on the upper layer and the sapphire substrate 101 and improving the bonding strength between them. For the buffer layer 102, for example, a laminated film in which a plurality of AlN (aluminum nitride) thin films and GaN thin films are alternately stacked can be used. At this time, it is preferable that the AlN thin film is directly above the sapphire substrate 101 and the GaN thin film is directly below the carrier traveling layer 103 which is a GaN film. Thereby, the bonding strength between the buffer layer 102 and the sapphire substrate 101 and the bonding strength between the buffer layer 102 and the carrier traveling layer 103 can be increased. In the present invention, it goes without saying that the structure and material of the buffer layer 102 can be variously modified depending on the material of the semiconductor layer (GaN film in this embodiment) formed on the buffer layer 102.

  The carrier traveling layer 103 is a layer that functions as a channel layer during operation, and is formed of, for example, undoped GaN. However, this carrier traveling layer 103 functions as a slightly n-type semiconductor layer due to a difference in band gap energy from the carrier supply layer 104 formed immediately above. In the present invention, the carrier traveling layer 103 can be formed using various group III nitride compound semiconductors such as AlGaN and InGaN, not limited to the GaN film.

  The carrier supply layer 104 has a band gap energy larger than that of the carrier traveling layer 103, and is a carrier supply for generating a two-dimensional electron gas 2DEG near the heterojunction interface in the carrier traveling layer 103 by heterojunction with the carrier traveling layer 103. The layer is formed of, for example, AlGaN.

  As described above, the HFET 100 according to the present embodiment has a HEMT structure in which the carrier traveling layer 103 and the carrier supply layer 104 are laminated. For this reason, the two-dimensional electron gas 2DEG is generated near the upper surface of the carrier traveling layer 103 having the smaller band gap energy due to the piezoelectric effect due to crystal distortion caused by the heterojunction. The HFET 100 uses the two-dimensional electron gas 2DEG generated in the carrier traveling layer 103 as a carrier. In other words, it has a configuration in which majority carriers are used for current transport. For this reason, it is characterized by high speed operation and excellent on characteristics.

In this embodiment mode, carbon (C) is doped as an impurity for compensating n-type carriers in the carrier supply layer 104 formed of an AlGaN film. C as an impurity is less likely to cause problems such as diffusion in the film, deflection to the surface, and current collapse as compared with, for example, Mg and Fe, so that stable operating characteristics can be obtained. It becomes possible. Note that the C concentration in the carrier supply layer 104 is preferably about 2 × 10 ¹⁷ cm ⁻³ or more, for example. As a result, as will be described later, the gate leakage current can be efficiently suppressed, and thus the HFET 100 with improved breakdown voltage characteristics and reduced leakage current can be realized. However, the carbon (C) concentration in the carrier supply layer 104 is preferably 1 × 10 ²⁰ cm ⁻³ or less. Further, when a metal film (for example, a gate 107 described later) that forms a Schottky interface with the carrier supply layer 104 is formed on the carrier supply layer 104, for example, when the reverse bias voltage between the source and the drain is set to 200V it is preferred reverse leakage current is 1 × ¹⁰ -4 A / cm ² or less. Thereby, it is possible to prevent the resistance value between the source and the drain from being lowered and the breakdown voltage between the gate and the drain from being deteriorated. Furthermore, when a metal film (for example, the gate 107) that forms the Schottky interface with the carrier supply layer 104 is formed on the carrier supply layer 104, for example, the reverse when the reverse bias voltage between the source and the drain is 200V. By setting the directional leakage current to 1 × 10 ⁻⁶ A / cm ² or less, the breakdown voltage between the gate and the drain can be further improved.

  The source electrode 106s and the drain electrode 106d provided separately on the carrier supply layer 104 are electrodes that are in ohmic contact with the carrier supply layer 104 or in a state in which the contact resistance is sufficiently small. It is formed using a laminated metal film in which titanium (Ti), aluminum (Al), and gold (Au) are laminated (hereinafter, this laminated metal film is referred to as a Ti / Al / Au film). However, the present invention is not limited to this. For example, at least one of titanium (Ti), aluminum (Al), silicon (Si), lead (Pb), chromium (Cr), indium (In), and tantalum (Ta). A metal film made of an alloy containing at least one of Ti, Al, Si, Pb, Cr, In, Ta, or a silicide alloy containing at least one of Ti, Al, Si, Ta Any metal film satisfying the above conditions, such as a metal film including at least one of the metal films formed, may be used.

  The gate electrode 107 is an electrode in Schottky contact with the carrier supply layer 104. For example, a laminated metal film in which platinum (Pt) and Au are laminated in order from the lower layer (hereinafter, this laminated metal film is referred to as a Pt / Au film). Are used). However, the present invention is not limited to this. For example, nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum (Ta ), A metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al, Any metal material that satisfies the above conditions, such as a metal film including at least one, may be used.

The insulating film 105 is a protective film for electrically and physically protecting the HFET element formed in the lower layer, and is composed of, for example, a silicon oxide film or a silicon nitride film. However, the present invention is not limited to this, and various insulating films can be used.

(Production method)
Next, a method for manufacturing the HFET 100 according to the present embodiment will be described in detail with reference to the drawings. 2A to 2D are diagrams illustrating a manufacturing process of the HFET 100 according to the present embodiment.

  As shown in FIG. 2A, in the present manufacturing method, first, a plurality of AlN thin films and GaN thin films are alternately formed on a sapphire substrate 101 as a support substrate, whereby a buffer having a film thickness of about 20 nm, for example. Layer 102 is formed. Subsequently, by forming a GaN film on the buffer layer 102, the carrier traveling layer 103 having a thickness of, for example, about 1 μm is formed. For example, a metal organic chemical vapor deposition method (MOCVD method) can be used to form each thin film in the buffer layer 102 and the GaN film that is the carrier traveling layer 103. However, the present invention is not limited to this, and various film forming methods such as a hydride vapor phase epitaxy method (HVPE method) and a molecular beam epitaxy method (MBE method) may be used.

Next, as illustrated in FIG. 2B, an Al _0.25 Ga _0.75 N film is formed on the carrier traveling layer 103 to form the carrier supply layer 104 having a thickness of, for example, about 25 nm. For film formation of the AlGaN film as the carrier supply layer 104, various film formation methods such as the HVPE method and the MBE method can be used in addition to the MOCVD method, similarly to the carrier traveling layer 103. However, in this embodiment, the carrier supply layer 104 is formed so that the carbon (C) concentration in the film is about 2 × 10 ¹⁷ cm ⁻³ or more, for example, about 2.5 × 10 ¹⁷ cm ⁻³ . The carrier supply layer 104 containing carbon (C) as an acceptor can be formed by autodoping with carbon (C) contained in an organometallic element, for example, when MOCVD is used.

As described above, when the HEMT structure laminated film including the carrier traveling layer 103 and the carrier supply layer 104 is formed on the sapphire substrate 101 with the buffer layer 102 interposed therebetween, next, for example, silicon oxide (SiO 2) is formed on the carrier supply layer 104. ₂ ) or an insulating film 105 is formed by depositing silicon nitride (SiN). For the deposition of SiO ₂ or SiN, for example, a chemical vapor deposition method (CVD method) can be used.

  Subsequently, by patterning the insulating film 105 by a photolithography process using the photoresist R1 as an etching mask, the carrier supply layer 104 is exposed in two spaced apart regions of the insulating film 105 as shown in FIG. The opening A1 to be formed is formed. At this time, it is preferable to pattern the insulating film 105 using an etchant and an etching condition that allow a sufficient selection ratio with the carrier supply layer 104. For example, when the insulating film 105 is formed using a silicon oxide film, a hydrofluoric acid solution can be used as the etchant. Further, when the silicon nitride film is used, for example, a phosphoric acid solution can be used as the etchant.

  Subsequently, by using, for example, a lift-off method, the source electrode 106s and the drain electrode 106d that are in ohmic contact with the carrier supply layer 104 are formed in the opening A1. Note that the photoresist R1 can be used for the sacrificial layer at the time of lift-off. The source electrode 106s and the drain electrode 106d can be formed of, for example, a Ti / Al / Au film as described above. Furthermore, the source electrode 106s and the drain electrode 106d may be in contact with the carrier supply layer 104 with sufficiently small contact resistance even if they are not in ohmic contact.

  Next, by patterning the insulating film 105 by a photolithography process using the photoresist R2 as an etching mask, a part of the region sandwiched between the source 106s and the drain 106d in the insulating film 105 as shown in FIG. 2-4. An opening A2 is formed in Subsequently, for example, a lift-off method is used to form the gate electrode 107 in Schottky contact with the carrier supply layer 104 in the opening A2. Note that the photoresist R2 can be used for the sacrificial layer at the time of lift-off. Further, as described above, the gate electrode 107 can be formed of, for example, a Pt / Au film. Thereby, the HFET 100 having the layer structure shown in FIG. 1 is manufactured.

As described above, according to the present embodiment, the carrier supply layer 104 is less likely to cause problems such as diffusion in the film, deflection to the surface, and current collapse as compared with, for example, Mg or Fe. Since carbon (C) is doped at 2 × 10 ¹⁷ cm ⁻³ or more, the HFET 100 having stable operating characteristics can be realized.

That is, the carrier transit layer 103 (first compound semiconductor layer) and the carrier supply layer 104 (second compound semiconductor layer) formed on at least a part of the carrier transit layer 103 and having a larger band gap energy than the carrier transit layer 103. In the HFET 100 including, the carrier supply layer 104 is doped with carbon (C) so that the concentration is 2 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. Further, the gate 107 that forms a Schottky interface with the carrier supply layer 104 is formed on the carrier supply layer 104, and the reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ^−4. A / cm ² or less. As a result, the leakage current in the HFET 100 can be limited, so that the breakdown voltage characteristics of the HEMT 100 can be improved.

For example, when the HFET 100 is turned off by applying a reverse bias potential difference between the gate and the drain, specifically, when the drain voltage is 0 V and the gate voltage is negative, the gate leakage current flowing between the gate and the drain of the HFET 100 is Good values of about 1 × 10 ⁻⁴ A / cm ² were obtained. At this time, the gate voltage was set to −10V, and the source-drain voltage was set to 200V.

FIG. 5 shows the relationship between the carbon (C) concentration in the carrier supply layer 104 and the gate leakage current in the HFET 100 according to the present embodiment. As is clear from FIG. 5, the gate leakage current is suppressed as the carbon (C) concentration in the carrier supply layer 104 is higher. For example, when the carbon (C) concentration is about 1 × 10 ¹⁷ cm ⁻³ , the gate leakage current is about 1 × 10 ⁻⁴ A / cm ² , whereas the carbon (C) concentration is 2.5 × 10 ¹⁷ cm. ^{When it is} about ^−3, the gate leakage current is reduced to about 1 × 10 ⁻⁵ A / cm ² , and when the carbon (C) concentration is about 5 × 10 ¹⁷ cm ⁻³ , the gate leakage current is 1 × 10 ⁻⁷ A / Cm ² and so on.

Therefore, by setting the carbon (C) concentration in the carrier supply layer 104 to 2 × 10 ¹⁷ cm ⁻³ or more, gate leakage current can be efficiently suppressed, breakdown voltage characteristics are improved, and leakage current is reduced. It was found that the HFET 100 can be realized.

In this embodiment, when a metal film (for example, corresponding to the gate electrode 107) that forms a Schottky interface with the carrier supply layer 104 is formed on the carrier supply layer 104, for example, a reverse bias between the source and the drain is provided. Since the decrease in the resistance value between the source and the drain can be suppressed by setting the reverse leakage current when the voltage is 200 V to be 1 × 10 ⁻⁴ A / cm ² or less, the breakdown voltage between the gate and the drain Can be prevented from deteriorating. Further, the carbon (C) concentration in the carrier supply layer 104 is set to 4 × 10 ¹⁷ cm ⁻³ or more, and a metal film (for example, in the gate 107) that forms a Schottky interface with the carrier supply layer 104 on the carrier supply layer 104. For example, when the reverse bias voltage between the source and the drain is 200 V, the reverse leakage current is 1 × 10 ⁻⁶ A / cm ² or less, thereby It is possible to further improve the breakdown voltage.

(Modification 1)
Next, another method for manufacturing the HFET 100 according to the present embodiment will be described as a first modification. In the first modification, the carrier supply layer 104 doped with carbon (C) is formed by ion implantation. That is, an undoped AlGaN film is formed by using, for example, the MOCVD method, and subsequently, as shown in FIG. 3, after C ions are implanted into the AlGaN film, carbon (C) atoms in the film are thermally diffused. Thus, the carbon in the film (C) concentration of approximately 2 × ¹⁰ 17 ^{cm -3} or more, for example 2.5 × ¹⁰ 17 ^{cm -3} of about carrier supply layer 104 is formed. At this time, the carbon (C) atom profile in the carrier supply layer 104 may be adjusted to be uniform by changing the acceleration energy of the carbon ions continuously or stepwise. Since other configurations and manufacturing methods are the same as those in the first embodiment, detailed description thereof is omitted here.

(Modification 2)
Next, another method for manufacturing the HFET 100 according to the present embodiment will be described below as a second modification. In the second modification, a carbon (C) -rich film is formed on an undoped AlGaN film, and carbon (C) atoms are drifted from the film to the AlGaN film, thereby supplying the carrier doped with carbon (C). Layer 104 is formed. That is, for example, an MOCVD method is used to form an undoped AlGaN film, and then a carbon source film 104A containing a large amount of carbon (C) is formed by forming graphite or the like on the AlGaN layer. Next, a diffusion prevention film 104B such as a silicon oxide film is formed on the carbon source film 104A, and then the carbon source film 104A is heated by annealing as shown in FIG. Thermally drift carbon (C) atoms into the layer. Thus, the carrier supply layer 104 having a carbon (C) concentration in the film of about 2 × 10 ¹⁷ cm ⁻³ or more, for example, about 2.5 × 10 ¹⁷ cm ⁻³ is formed. At this time, a drift of carbon (C) atoms to the AlGaN layer may be promoted by forming an electric field in the chamber. Since other configurations and manufacturing methods are the same as those in the first embodiment, detailed description thereof is omitted here.

<Embodiment 2>
Hereinafter, a Schottky barrier diode (hereinafter referred to simply as SBD) 200 as a semiconductor device according to the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

(Constitution)
FIG. 6 is a cross-sectional view showing the layer structure of SBD 200 according to the present embodiment. Note that FIG. 6 shows a cross-sectional structure when the SBD 200 is cut along a plane that is perpendicular to the upper surface of the sapphire substrate 101 that is a support substrate and is parallel to the channel length direction.

  As shown in FIG. 6, the SBD 200 includes a sapphire substrate 101 that is a support substrate, a buffer layer 102 on the sapphire substrate 101, a carrier traveling layer 103 (first compound semiconductor layer) on the buffer layer 102, and a carrier traveling layer. 103, a carrier supply layer 104 (second compound semiconductor layer), an anode electrode AN and a cathode electrode CA provided on the carrier supply layer 104, and an insulating film 105 covering the carrier supply layer 104. Prepare.

In this configuration, the sapphire substrate 101, the buffer layer 102, the carrier traveling layer 103, the carrier supply layer 104, and the insulating film 105 are the same as those in the first embodiment. That is, also in this embodiment, the carrier supply layer 104 formed of an AlGaN film is doped with carbon (C) as an n-type impurity, and the C concentration is, for example, about 2 × 10 ¹⁷ cm ⁻³ or more. Has been.

  The anode electrode AN on the carrier supply layer 104 is an electrode that is in Schottky contact with the carrier supply layer 104, and is formed using, for example, a Pt / Au film in which platinum (Pt) and Au are stacked in order from the lower layer. However, the present invention is not limited to this. For example, nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum (Ta ), A metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al, Any metal material that satisfies the above conditions, such as a metal film including at least one, may be used.

  The cathode electrode CA on the carrier supply layer 104 is an electrode that is in ohmic contact with the carrier supply layer 104. For example, Ti / Ti in which titanium (Ti), aluminum (Al), and gold (Au) are stacked in this order from the lower layer. It is formed using an Al / Au film. However, the present invention is not limited to this. For example, at least one of titanium (Ti), aluminum (Al), silicon (Si), lead (Pb), chromium (Cr), indium (In), and tantalum (Ta). A metal film made of an alloy containing at least one of Ti, Al, Si, Pb, Cr, In, Ta, or a silicide alloy containing at least one of Ti, Al, Si, Ta Any metal film satisfying the above conditions, such as a metal film including at least one of the metal films formed, may be used.

(Production method)
Next, the manufacturing method of SBD200 by this Embodiment is demonstrated in detail using drawing. However, the description of the same steps as the manufacturing method according to the first embodiment is omitted by citing the description. FIGS. 7-1 and FIGS. 7-2 are figures which show the manufacturing process of SBD200 by this Embodiment.

  In this manufacturing method, first, the carrier travel is performed with the buffer layer 102 sandwiched between the sapphire substrate 101 through the same steps as those described in the first embodiment with reference to FIGS. 2-1 and 2-2. A laminated film having a HEMT structure including the layer 103 and the carrier supply layer 104 is formed.

Next, in this manufacturing method, the insulating film 105 is formed by depositing, for example, SiO ₂ or SiN on the carrier supply layer 104, and then the insulating film 105 is formed by a photolithography process using the photoresist R3 as an etching mask. By patterning, as shown in FIG. 7A, an opening A3 exposing a part of the carrier supply layer 104 is formed in the insulating film 105. Note that the patterning method of the insulating film 105 is the same as the method mentioned in the description of FIG. 2-3 or FIG.

  Subsequently, a cathode electrode CA that is in ohmic contact with the carrier supply layer 104 is formed in the opening A3 by using, for example, a lift-off method. Note that the photoresist R3 can be used for the sacrificial layer at the time of lift-off. Further, as described above, the cathode electrode CA can be formed of, for example, a Ti / Al / Au film. Furthermore, even if the cathode electrode CA is not in ohmic contact with the carrier supply layer 104, it may be in contact with a sufficiently small contact resistance.

  Next, by patterning the insulating film 105 by a photolithography process using the photoresist R4 as an etching mask, an opening A4 exposing a part of the carrier supply layer 104 is formed in the insulating film 105 as shown in FIG. Form. Note that the patterning method of the insulating film 105 is the same as the method mentioned in the description of FIG.

  Subsequently, the anode electrode AN that is in Schottky contact with the carrier supply layer 104 is formed in the opening A4 by using, for example, a lift-off method. Note that the photoresist R4 can be used for the sacrificial layer at the time of lift-off. The anode electrode AN can be formed of, for example, a Pt / Au film as described above. Thereby, SBD200 provided with the layer structure shown in FIG. 6 is manufactured.

As described above, according to the present embodiment, the carrier supply layer 104 is less likely to cause problems such as diffusion in the film, deflection to the surface, and current collapse as compared with, for example, Mg or Fe. Since carbon (C) is doped at 2 × 10 ¹⁷ cm ⁻³ or more, it becomes possible to realize the SBD 200 with stable operating characteristics.

Here, for example, when the carbon (C) concentration is about 1 × 10 ¹⁷ cm ⁻³ , the reverse leakage current when the reverse bias voltage is 200 V is about 1 × 10 ⁻⁴ A / cm ^2. On the other hand, when the carbon (C) concentration is about 2.5 × 10 ¹⁷ cm ⁻³ , the reverse leakage current when the reverse bias voltage is 200 V is reduced to about 1 × 10 ⁻⁵ A / cm ^2. It was. Further, by setting the carbon (C) concentration to about 5 × 10 ¹⁷ cm ⁻³ , the reverse leakage current at a reverse bias voltage of 200 V was further reduced to about 1 × 10 ⁻⁷ A / cm ² .

Therefore, by setting the carbon (C) concentration in the carrier supply layer 104 to 2 × 10 ¹⁷ cm ⁻³ or more, the reverse leakage current can be efficiently suppressed, the breakdown voltage characteristics are improved, and the leakage current is reduced. It has been found that the SBD 200 can be realized.

In this embodiment, when a metal film (for example, corresponding to the anode electrode AN) that forms a Schottky interface with the carrier supply layer 104 is formed on the carrier supply layer 104, the reverse bias voltage is set to 200 V, for example. When the reverse leakage current at that time is 1 × 10 ⁻⁴ A / cm ² or less, a decrease in the resistance value between the anode and the cathode can be suppressed, so that the breakdown voltage of the SBD 200 can be prevented from deteriorating. Furthermore, the carbon (C) concentration in the carrier supply layer 104 is set to 4 × 10 ¹⁷ cm ⁻³ or more, and a metal film (for example, an anode electrode AN) that forms a Schottky interface with the carrier supply layer 104 on the carrier supply layer 104 For example, when the reverse bias voltage is 200 V, the reverse leakage current is 1 × 10 ⁻⁶ A / cm ² or less to further improve the breakdown voltage of the SBD 200. Is possible.

That is, the carrier transit layer 103 (first compound semiconductor layer) and the carrier supply layer 104 (second compound semiconductor layer) formed on at least a part of the carrier transit layer 103 and having a larger band gap energy than the carrier transit layer 103. And the carrier supply layer 104 is doped with carbon (C) so as to have a concentration of 2 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less on the carrier supply layer 104. In addition, an anode electrode AN that forms a Schottky interface with the carrier supply layer 104 was formed, and the reverse direction was set downward. As a result, the leakage current in the SBD 200 can be limited, and the breakdown voltage characteristics of the SBD 200 can be improved.

  In this embodiment mode, as described with reference to FIG. 3 or FIG. 4 in Embodiment Mode 1, the carrier supply layer 104 doped with carbon (C) is formed by various methods. Is possible.

  Further, the above embodiment is merely an example for carrying out the present invention, and the present invention is not limited to these, and various modifications according to specifications and the like are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

In the first and second embodiments, the carrier travel layer 103 is formed of a GaN film and the carrier supply layer 104 is formed of an AlGaN film. However, the present invention is not limited thereto, and other elements are added as appropriate. Each layer may be formed using a group III nitride compound semiconductor. For example, the carrier traveling layer 103 is formed using a group III nitride compound semiconductor such as Al _x1 In _y1 Ga _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, x1 + y1 ≦ 1). Can do. Further, the carrier supply layer 104 is made of Al _x2 In _y2 Ga _1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, x2 + y2 ≦ 1) having a larger band gap energy than the carrier traveling layer 103. It can be formed using a group nitride compound semiconductor.

Further, in the first and second embodiments, Al _x1 In _y1 Ga _1-x1-y1 N (0 ≦ x1 ≦ 1, as a group III nitride compound semiconductor used for the carrier traveling layer 103, the carrier supply layer 104, and the like. Although 0.ltoreq.y1.ltoreq.1, x1 + y1.ltoreq.1) has been described as an example, it is needless to say that the present invention is not limited to this and can be formed using other compound semiconductors. For example, the present invention can be applied to a case where a small amount of arsenic (As) or phosphorus (P) is included as a group V element in addition to nitrogen (N).

  Furthermore, in the first embodiment, the HFET which is a kind of FET is given as an example of the semiconductor element according to the present invention. However, the present invention is not limited to this, and the MISFET (Metal Insulator Semiconductor FET) or MOSFET (Metal Oxide). The present invention can be applied to various FETs such as Semiconductor FETs and MESFETs.

100 HFET
DESCRIPTION OF SYMBOLS 101 Sapphire substrate 102 Buffer layer 103 Carrier traveling layer 104 Carrier supply layer 104A Carbon source film 104B Diffusion prevention film 105 Insulating film 106d Drain electrode 106s Source electrode 107 Gate electrode A1, A2 Opening R1, R2 Photoresist 2DEG Two-dimensional electron gas 200 SBD
AN Anode electrode CA Cathode electrode

Claims (9)

A first compound semiconductor layer made of a nitride compound semiconductor;
A second compound semiconductor layer formed on at least a part of the first compound semiconductor layer and made of a nitride-based compound semiconductor having a band gap energy larger than that of the first compound semiconductor layer;
Have
The second compound semiconductor layer has a carbon concentration of 2 × 10 ¹⁷ cm ⁻³ or more and a carbon concentration of 1 × 10 ²⁰ cm ⁻³ or less,
When a metal film that forms a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, the reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ^{− 4} A / cm ² or less. A first compound semiconductor layer made of a nitride compound semiconductor;
A second compound semiconductor layer formed on at least a part of the first compound semiconductor layer and made of a nitride-based compound semiconductor having a band gap energy larger than that of the first compound semiconductor layer;
Have
The second compound semiconductor layer has a carbon concentration of 4 × 10 ¹⁷ cm ⁻³ or more and a carbon concentration of 1 × 10 ²⁰ cm ⁻³ or less,
When a metal film that forms a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, the reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ^{− 6} A / cm ² or less. Wherein the first compound semiconductor layer _is made of _{Al x1 In y1 Ga 1-x1} -y1 N (0 ≦ x1 ≦ 1,0 ≦ y1 ≦ 1, x1 + y1 ≦ 1),
The second compound semiconductor layer is made of Al _x2 In _y2 Ga _1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, x2 + y2 ≦ 1) having a larger band gap energy than the first compound semiconductor layer. The semiconductor device according to claim 1, wherein:   The semiconductor device according to claim 1, wherein the semiconductor device is a diode or a field effect transistor.   The first compound semiconductor layer is directly formed on a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate, or the silicon substrate, the sapphire substrate, the silicon carbide substrate, or the gallium nitride. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a buffer layer provided on a substrate. A first compound semiconductor layer forming step of forming a first compound semiconductor layer made of a nitride-based compound semiconductor on a support substrate;
On the first compound semiconductor layer, the carbon concentration is 2 × 10 ¹⁷ cm ⁻³ or more and the carbon concentration is 1 × 10 ²⁰ cm ⁻³ or less, and the band gap energy is higher than that of the first compound semiconductor layer. A second compound semiconductor layer forming step of forming a second compound semiconductor layer made of a nitride-based compound semiconductor having a large thickness;
Including
It said second compound when forming the metal film forming the Schottky interface between the second compound semiconductor layer on the semiconductor layer, the reverse leakage current when a reverse bias voltage is 200V is 1 × 10 ^{- 4} A / cm < ² > or less, The manufacturing method of the semiconductor device characterized by the above-mentioned. A first compound semiconductor layer forming step of forming a first compound semiconductor layer made of a nitride-based compound semiconductor on a support substrate;
On the first compound semiconductor layer, the carbon concentration is 4 × 10 ¹⁷ cm ⁻³ or more and the carbon concentration is 1 × 10 ²⁰ cm ⁻³ or less, and the band gap energy is higher than that of the first compound semiconductor layer. A second compound semiconductor layer forming step of forming a second compound semiconductor layer made of a nitride-based compound semiconductor having a large thickness;
Including
When a metal film that forms a Schottky interface with the second compound semiconductor layer is formed on the second compound semiconductor layer, the reverse leakage current when the reverse bias voltage is 200 V is 1 × 10 ^{− 6} A / cm < ² > or less, The manufacturing method of the semiconductor device characterized by the above-mentioned.   The second compound semiconductor layer forming step includes a method of doping carbon atoms during growth of a compound semiconductor film having a band gap energy larger than that of the first compound semiconductor layer, and ion implantation after growing the compound semiconductor film. The second compound semiconductor layer is formed by any one of a method of doping carbon atoms in a semiconductor film and a method of doping carbon atoms in the compound semiconductor film by thermal diffusion after the compound semiconductor film is grown. A method for manufacturing a semiconductor device according to claim 6 or 7, wherein: A first compound semiconductor layer made of a nitride-based compound semiconductor, and a first compound semiconductor layer formed in at least a part of the first compound-semiconductor layer and having a bandgap energy larger than that of the first compound-semiconductor layer. A method for reducing leakage current of a semiconductor device including a two-compound semiconductor layer,
A method for reducing a leakage current of a semiconductor device, wherein the second compound semiconductor layer is doped with carbon so that the concentration is 2 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

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