CN212085010U - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN212085010U
CN212085010U CN202020438296.6U CN202020438296U CN212085010U CN 212085010 U CN212085010 U CN 212085010U CN 202020438296 U CN202020438296 U CN 202020438296U CN 212085010 U CN212085010 U CN 212085010U
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程凯
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Enkris Semiconductor Inc
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Abstract

本实用新型提供了一种半导体结构，包括：衬底以及位于衬底上的异质结结构；异质结结构包括源区、漏区以及位于源区与漏区之间的栅极区，漏区上设置有量子阱结构。在异质结结构的漏区上设置量子阱结构，利用量子阱结构复合发光产生光子，该光子不但可以辐射在势垒层的表面区域，同时也可以深入异质结结构的内部，从而加快被缺陷虏获的电子的释放过程，以实现减弱电流崩塌效应以及降低动态导通电阻。

Description

半导体结构
技术领域
本实用新型涉及半导体技术领域，尤其涉及一种半导体结构。
背景技术
III族氮化物半导体是继Si、GaAs等第一、第二代半导体材料之后的第三代新型半导体材料。III族氮化物半导体具有较高的饱和电子迁移速率，高击穿电压和宽禁带宽度，正因为这些特性，基于GaN的高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)器件具有广阔应用前景。
现有的III族氮化物半导体HEMT器件作为高频器件或者高压大功率开关器件使用时，存在“电流崩塌”现象。即当器件工作在直流脉冲模式或者高频模式下，漏极输出电流跟不上栅极控制信号的变化，会出现漏极电流瞬时减小、动态导通电阻增大的情况，这严重影响器件的应用。这种现象归根结底是由于极化效应在带来异质结界面沟道中二维电子气(2DEG)的同时，使得异质结中势垒层上表面形成电荷密度与2DEG浓度相当的带正电荷的离化施主造成的。其原理在于，当HEMT器件工作在截止状态时，栅极偏向漏极一侧的电场强度达到最大，栅极上的电子在电场力的作用下跃迁至势垒层表面，并在其表面施主能级间向漏极的方向横向迁移，中和了表面的离化施主并耗尽沟道中的电子，形成“虚栅”；当HEMT器件的工作状态从截止转为导通时，势垒层表面从栅极迁移来的电子会以缓慢的速率迁移回栅极。但是当HEMT器件以一定的频率开关时，势垒层表面的电子就不能及时迁移回栅极，造成导通状态下的电阻升高，可能几倍于静态导通电阻，即电流崩塌。
有鉴于此，实有必要提供一种新的半导体结构，以解决上述问题。
实用新型内容
本实用新型的发明目的是提供一种半导体结构，解决电流崩塌问题。
为实现上述目的，本实用新型提供一种半导体结构，包括：
衬底以及位于所述衬底上的异质结结构；所述异质结结构包括源区、漏区以及位于所述源区与所述漏区之间的栅极区，所述漏区上设置有量子阱结构。
可选地，所述量子阱结构包括N型半导体层、第一P型半导体层以及位于所述N型半导体层与所述第一P型半导体层之间的量子阱层。
可选地，所述第一P型半导体层包括远离所述量子阱层的空穴钝化层。
可选地，所述异质结结构自下而上包括沟道层与势垒层。
可选地，所述势垒层充当所述量子阱结构中的N型半导体层。
可选地，所述沟道层与所述势垒层的材料组合包括：GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
可选地，所述栅极区上设置有介电层和/或第二P型半导体层。
可选地，所述量子阱层为单量子阱层或多量子阱层。
可选地，所述第一P型半导体层的材料包括：GaN、AlGaN、InGaN、AlInGaN中的至少一种。
可选地，所述源区上设置有源极、所述量子阱结构上设置有第一漏极，所述栅极区上设置有栅极；所述源极与所述异质结结构之间为欧姆接触，所述第一漏极与所述量子阱结构之间为欧姆接触，所述栅极与所述异质结结构之间为肖特基接触。
可选地，所述漏区上还设置有第二漏极，所述第二漏极与所述异质结结构之间为欧姆接触。
可选地，所述第一漏极与所述量子阱结构通过绝缘层与所述第二漏极电绝缘。
可选地，所述第一漏极位于所述栅极与所述第二漏极之间。
可选地，所述第二漏极位于所述栅极与所述第一漏极之间。
与现有技术相比，本实用新型的有益效果在于：
1)在异质结结构的漏区上设置量子阱结构，利用量子阱结构复合发光产生光子，该光子不但可以辐射在势垒层的表面区域，同时也可以深入异质结结构的内部，从而加快被缺陷虏获的电子的释放过程，以实现减弱电流崩塌效应以及降低动态导通电阻。
2)可选方案中，a)量子阱结构包括N型半导体层、第一P型半导体层以及位于N型半导体层与第一P型半导体层之间的量子阱层；或b)异质结结构中的势垒层充当量子阱结构中的N型半导体层。相对于a)方案，b)方案可以简化半导体结构。
3)可选方案中，第一P型半导体层包括远离量子阱层的空穴钝化层。空穴钝化层可以防止栅极中的电子迁移至第一P型半导体层以及与第一P型半导体层中的空穴复合。换言之，空穴钝化层可以使栅极与漏极之间形成高电阻的阻断状态。空穴钝化层可以通过对第一P型半导体层进行H离子注入实现。H离子能钝化第一P型半导体层的P型掺杂离子Mg，使Mg不产生空穴。
附图说明
图1是本实用新型第一实施例的半导体结构的截面结构示意图；
图2是本实用新型第二实施例的半导体结构的截面结构示意图；
图3是本实用新型第三实施例的半导体结构的截面结构示意图；
图4是本实用新型第四实施例的半导体结构的截面结构示意图；
图5是本实用新型第五实施例的半导体结构的截面结构示意图
图6是本实用新型第六实施例的半导体结构的截面结构示意图；
图7是本实用新型第七实施例的半导体结构的截面结构示意图。
为方便理解本实用新型，以下列出本实用新型中出现的所有附图标记：
半导体结构1、2、3、4、5、6、7 衬底10
异质结结构11 源区12a
漏区12b 栅极区12c
沟道层11a 势垒层11b
量子阱结构13 N型半导体层13a
第一P型半导体层13b 量子阱层13c
空穴钝化层130 介电层14
第二P型半导体层15 源极16a
第一漏极16b 栅极16c
第二漏极16d 绝缘层17
具体实施方式
为使本实用新型的上述目的、特征和优点能够更为明显易懂，下面结合附图对本实用新型的具体实施例做详细的说明。
图1是本实用新型第一实施例的半导体结构的截面结构示意图。
参照图1所示，半导体结构1包括：
衬底10以及位于衬底10上的异质结结构11；异质结结构11包括源区12a、漏区12b以及位于源区12a与漏区12b之间的栅极区12c，漏区12b上设置有量子阱结构13。
衬底10可以为GaN基材料。GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种，本实施例对此不加以限制。
衬底10也可以包括：Al2O3、蓝宝石、碳化硅和硅中的至少一种及其上的GaN基材料。
异质结结构11自下而上可以包括沟道层11a与势垒层11b。具体地，a)沟道层11a与势垒层11b可以分别具有一层；或b)沟道层11a与势垒层11b可以分别具有多层，且交替分布；或c)一层沟道层11a与两层或两层以上的势垒层11b，以满足不同功能需求。
沟道层11a与势垒层11b的材料组合可以包括：GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
异质结结构11与衬底10之间还可以具有成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层，例如异质结结构11中的沟道层11a与衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
参照图1所示，本实施例中，量子阱结构13包括N型半导体层13a、第一P型半导体层13b以及位于N型半导体层13a与第一P型半导体层13b之间的量子阱层13c。
N型半导体层13a用于提供电子，第一P型半导体层13b用于提供空穴，以使电子与空穴在量子阱层13c中复合发光。N型半导体层13a和/或第一P型半导体层13b可以包括GaN基材料。GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。N型半导体层13a中的N型掺杂元素可以为Mg，第一P型半导体层13b中的P型掺杂元素可以为Si。
图1所示实施例中，N型半导体层13a靠近异质结结构11，第一P型半导体层13b远离异质结结构11，其它实施例中，也可以第一P型半导体层13b靠近异质结结构11，N型半导体层13a远离异质结结构11。
量子阱层13c可以为单量子阱层，也可以为多量子阱层。
半导体结构1中，在异质结结构11的漏区12b上设置量子阱结构13，利用量子阱结构13复合发光产生光子，光子能加快被缺陷虏获的电子的释放过程，从而可以实现减弱电流崩塌效应以及降低动态导通电阻。此外，该光子不但可以辐射在势垒层11b的表面区域，同时也可以深入异质结结构11的内部，换言之，不但能加快势垒层表面区域的电子的释放过程，还能加快异质结结构内部的电子的释放过程，从而可以进一步减弱电流崩塌效应以及降低动态导通电阻。
半导体结构1可以做为半导体器件的半成品生产与销售。
图2是本实用新型第二实施例的半导体结构的截面结构示意图。
参照图2所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：势垒层11b为N型半导体层，充当量子阱结构13中的N型半导体层13a。换言之，量子阱结构13省略设置N型半导体层13a。
本实施例二中，沟道层11a可以为本征半导体层。
图3是本实用新型第三实施例的半导体结构的截面结构示意图。
参照图3所示，本实施例三的半导体结构3与实施例一、二的半导体结构1、2大致相同，区别仅在于：第一P型半导体层13b包括远离量子阱层13c的空穴钝化层130。
空穴钝化层130可以防止栅极16c(参照图6所示)中的电子与第一P型半导体层13b中的空穴复合。换言之，空穴钝化层130能使栅极16c与第一漏极16b(参照图6所示)之间形成高电阻的阻断状态。
空穴钝化层130可以通过对第一P型半导体层13b进行H离子注入实现。H离子能钝化第一P型半导体层13b的P型掺杂离子Mg，使Mg不产生空穴。
图4是本实用新型第四实施例的半导体结构的截面结构示意图。
参照图4所示，本实施例四的半导体结构4与实施例一、二、三的半导体结构1、2、3大致相同，区别仅在于：栅极区12c上设置有介电层14。
介电层14的材料可以为二氧化硅或氮化硅等。介电层14可以改变异质结结构11中栅极区12c的极化程度，使半导体结构4处于常闭状态。
图5是本实用新型第五实施例的半导体结构的截面结构示意图。
参照图5所示，本实施例五的半导体结构5与实施例四的半导体结构4大致相同，区别仅在于：栅极区12c的介电层14上设置有第二P型半导体层15。
第二P型半导体层15的材料可以包括：GaN、AlGaN、InGaN、AlInGaN中的至少一种，P型掺杂元素可以为Mg。
第二P型半导体层15可以消耗异质结结构11中栅极区12c的二维电子气，使半导体结构5处于常闭状态。
本实施例五中的第二P型半导体层15可以与实施例一、二、三的半导体结构1、2、3结合，即栅极区12c设置有第二P型半导体层15。
图6是本实用新型第六实施例的半导体结构的截面结构示意图。
参照图6所示，本实施例六的半导体结构6与实施例一至五的半导体结构1、2、3、4、5大致相同，区别仅在于：源区12a上设置有源极16a、量子阱结构13上设置有第一漏极16b，栅极区12c上设置有栅极16c；源极16a与异质结结构11之间为欧姆接触，第一漏极16b与量子阱结构13之间为欧姆接触，栅极16c与异质结结构11之间为肖特基接触。
源极16a、和/或第一漏极16b、和/或栅极16c的材料可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质。
图7是本实用新型第七实施例的半导体结构的截面结构示意图。
参照图7所示，本实施例七的半导体结构7与实施例一至六的半导体结构1、2、3、4、5、6大致相同，区别仅在于：漏区12b上还设置有第二漏极16d，第二漏极16d与异质结结构11之间为欧姆接触。
第一漏极16b与第二漏极16d可以并联。第一漏极16b与第二漏极16d可以根据具体半导体结构7的设计，在施加同一电位或不同电位时实现不同的功能。
图7所示的半导体结构7中，第二漏极16d位于栅极16c与第一漏极16b之间。一些实施例中，第一漏极16b也可以位于栅极16c与第二漏极16d之间。
图7所示的半导体结构7中，第一漏极16b与量子阱结构13通过绝缘层17与第二漏极16d电绝缘。绝缘层17可以包括二氧化硅、氮化硅等材料。一些实施例中，也可以省略绝缘层17。
虽然本实用新型披露如上，但本实用新型并非限定于此。任何本领域技术人员，在不脱离本实用新型的精神和范围内，均可作各种更动与修改，因此本实用新型的保护范围应当以权利要求所限定的范围为准。

Claims (12)

1.一种半导体结构，其特征在于，包括：
衬底(10)以及位于所述衬底(10)上的异质结结构(11)；所述异质结结构(11)包括源区(12a)、漏区(12b)以及位于所述源区(12a)与所述漏区(12b)之间的栅极区(12c)，所述漏区(12b)上设置有量子阱结构(13)。
2.根据权利要求1所述的半导体结构，其特征在于，所述量子阱结构(13)包括N型半导体层(13a)、第一P型半导体层(13b)以及位于所述N型半导体层(13a)与所述第一P型半导体层(13b)之间的量子阱层(13c)。
3.根据权利要求2所述的半导体结构，其特征在于，所述第一P型半导体层(13b)包括远离所述量子阱层(13c)的空穴钝化层(130)。
4.根据权利要求1所述的半导体结构，其特征在于，所述异质结结构(11)自下而上包括沟道层(11a)与势垒层(11b)。
5.根据权利要求4所述的半导体结构，其特征在于，所述势垒层(11b)充当所述量子阱结构(13)中的N型半导体层。
6.根据权利要求4或5所述的半导体结构，其特征在于，所述沟道层(11a)与所述势垒层(11b)的材料组合包括：GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
7.根据权利要求1所述的半导体结构，其特征在于，所述栅极区(12c)上设置有介电层(14)和/或第二P型半导体层(15)。
8.根据权利要求2所述的半导体结构，其特征在于，所述量子阱层(13c)为单量子阱层或多量子阱层。
9.根据权利要求2所述的半导体结构，其特征在于，所述第一P型半导体层(13b)的材料包括：GaN、AlGaN、InGaN、AlInGaN中的一种。
10.根据权利要求1所述的半导体结构，其特征在于，所述源区(12a)上设置有源极(16a)、所述量子阱结构(13)上设置有第一漏极(16b)，所述栅极区(12c)上设置有栅极(16c)；所述源极(16a)与所述异质结结构(11)之间为欧姆接触，所述第一漏极(16b)与所述量子阱结构(13)之间为欧姆接触，所述栅极(16c)与所述异质结结构(11)之间为肖特基接触。
11.根据权利要求10所述的半导体结构，其特征在于，所述漏区(12b)上还设置有第二漏极(16d)，所述第二漏极(16d)与所述异质结结构(11)之间为欧姆接触。
12.根据权利要求11所述的半导体结构，其特征在于，所述第一漏极(16b)与所述量子阱结构(13)通过绝缘层(17)与所述第二漏极(16d)电绝缘。
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