CN114759025B - 一种基于GaN双异质结的单片集成芯片 - Google Patents
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Abstract
本发明公开了基于GaN双异质结外延片的功率器件与CMOS逻辑电路的集成芯片,包含增强型的p‑MOS和n‑MOS、耗尽型n‑MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容,其中增强型p‑MOS和n‑MOS构成CMOS反相器。本发明主要特征在于:通过基于GaN双异质结外延片的上述器件实现全GaN CMOS逻辑电路和功率器件的单片集成,减小了寄生效应,提高了芯片集成度和功率密度;本发明提出的GaN双异质结外延片结构,在GaN沟道层(3)/势垒层(4)和势垒层(4)/顶部GaN层(5)异质界面分别引入二维电子气(2DEG)和二维空穴气(2DHG),通过选择性保留2DHG实现低阻p‑MOS;双异质结引入的极化结用于增强型功率HEMT和功率SBD,器件阻断状态下,极化结改善电场集中效应,提高功率器件的击穿电压。
Description
技术领域
本发明属于功率半导体集成电路技术领域,涉及一种基于GaN双异质结外延片的功率器件与CMOS逻辑电路的单片集成芯片。
背景技术
CMOS集成技术具有高能源效率,是目前驱动集成电路(IC)的主流选择。当前Navitas等公司的GaN功率IC仅将部分驱动电路与功率器件集成,逻辑控制部分和前级驱动依旧采用Si基IC实现,这种混合集成方案限制了开关频率,且散热和抗辐照性能较差,限制了GaN IC在航天及新一代通信领域的应用。因此实现全GaN CMOS逻辑电路和功率器件的单片集成具有重大意义。其中,GaN基p沟道器件是推动GaN芯片高频化,集成化和小型化的核心单元。常规pMOS利用常关型GaN HEMT的p-GaN栅极材料实现,但p-GaN中受主Mg电离能较高,空穴浓度和迁移率较低,限制了pMOS的输出电流能力。此外,对于GaN功率器件,缓解电场集中效应、提高击穿电压是充分发挥GaN材料优良特性,拓展GaN器件应用范围亟待解决的问题。
发明内容
针对上述问题,本发明提出一种基于GaN双异质结外延片的功率器件与CMOS逻辑电路的单片集成芯片。
本发明的技术方案是:
一种基于GaN双异质结的单片集成芯片,包含增强型的p-MOS和n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容,其中增强型p-MOS和n-MOS构成CMOS反相器;
GaN双异质结外延片包括沿垂直方向自下而上依次层叠设置的衬底层1、GaN缓冲层2、GaN沟道层3、势垒层4、顶部GaN层5;所述势垒层4和GaN沟道层3形成异质结,异质结界面产生二维电子气(2DEG);所述顶部GaN层5和势垒层4形成异质结,异质结界面产生二维空穴气(2DHG);
所述增强型p-MOS制作在顶部GaN层5层的一端,其中部有凹槽,且上表面覆盖绝缘栅介质10;所述增强型p-MOS表面沿横向方向上依次分布增强型p-MOS第一导电材料、增强型p-MOS第二导电材料和增强型p-MOS第三导电材料,且三者彼此有间距;所述增强型p-MOS第一导电材料向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触,其引出端为源电极;所述增强型p-MOS第二导电材料覆盖在顶部GaN层5凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述增强型p-MOS第三导电材料向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触,其引出端为漏电极;
所述增强型n-MOS制作在势垒层4上并与增强型p-MOS相邻,增强型n-MOS对应位置势垒层4之上的顶部GaN层5被刻蚀掉;所述增强型n-MOS中部有凹槽,且上表面覆盖绝缘栅介质10;所述增强型n-MOS表面沿横向方向上依次分布增强型n-MOS第一导电材料、增强型n-MOS第二导电材料和增强型n-MOS第三导电材料,且三者彼此有间距;所述增强型n-MOS第一导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为漏电极;所述增强型n-MOS第二导电材料覆盖在势垒层4凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述增强型n-MOS第三导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为源电极;
所述耗尽型n-MOS制作在势垒层4上并与增强型n-MOS相邻,耗尽型n-MOS对应位置势垒层4之上的顶部GaN层5被刻蚀掉,且势垒层4上表面覆盖绝缘栅介质10;所述耗尽型n-MOS表面沿横向方向上依次分布耗尽型n-MOS第一导电材料、耗尽型n-MOS第二导电材料和耗尽型n-MOS第三导电材料,且三者彼此有间距;所述耗尽型n-MOS第一导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为源电极;所述耗尽型n-MOS第二导电材料与绝缘栅介质10接触,其引出端为栅电极;所述耗尽型n-MOS第三导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为漏电极;
所述电阻制作在势垒层4上并与耗尽型n-MOS相邻,电阻对应位置势垒层4之上的顶部GaN层5被刻蚀掉,且势垒层4上表面覆盖绝缘栅介质10;所述电阻表面左右两端分别设置有电阻第一导电材料、电阻第三导电材料;所述电阻第一导电材料和电阻第三导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触;
所述pn结电容制作在顶部GaN层5上并与电阻相邻,pn结电容对应顶部GaN层5在pn结电容两端分别开有窗口以露出势垒层4,将两个窗口分别定义为第一窗口和第二窗口,其中第一窗口与电阻相邻;所述第一窗口中设有pn结电容第一导电材料;所述pn结电容第一导电材料向下延伸入势垒层4中,且和势垒层4的接触为欧姆接触;所述第二窗口中设有pn结电容第三导电材料;所述pn结电容第三导电材料向下延伸入势垒层4中,且和势垒层4的接触为欧姆接触;所述顶部GaN层5上设置有pn结电容第二导电材料;所述pn结电容第二导电材料向下伸入顶部GaN层5中,且和顶部GaN层5的接触为肖特基接触;所述势垒层4和顶部GaN层5无电极覆盖的表面被绝缘栅介质10覆盖;
所述具有极化结的增强型功率HEMT制作在顶部GaN层5上并与pn结电容相邻,极化结的增强型功率HEMT对应的顶部GaN层5左右两端开有窗口以露出势垒层4,将两个窗口分别定义为第三窗口和第四窗口,且第三窗口和pn结电容相邻,且第三窗口对应的势垒层4中间有凹槽;所述增强型功率HEMT表面覆盖绝缘栅介质10;所述第三窗口中沿横向方向上依次分布增强型功率HEMT第一导电材料、增强型功率HEMT第二导电材料,且两者之间有间距;所述增强型功率HEMT第一导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为源电极;所述增强型功率HEMT第二导电材料覆盖在势垒层4凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述第四窗口设有增强型功率HEMT第三导电材料;所述增强型功率HEMT第三导电材料向下延伸,贯穿绝缘栅介质10并延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为漏电极;所述顶部GaN层5表面靠近左端窗口处设有增强型功率HEMT第四导电材料;所述增强型功率HEMT第四导电材料向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触;
所述具有极化结的功率SBD制作在顶部GaN层5上层另一端并与增强型功率HEMT相邻;具有极化结的功率SBD对应的顶部GaN层5远离增强型功率HEMT一端开有窗口以露出势垒层4,定义为第五窗口,第五窗口中设有功率SBD第三导电材料;所述功率SBD第三导电材料向下延伸入势垒层4中,且和势垒层4的接触为欧姆接触,其引出端为阴极;功率SBD与增强型功率HEMT相邻一端设有功率SBD第二导电材料;所述功率SBD第二导电材料向下延伸,贯穿顶部GaN层5,并延伸入势垒层4中,且和势垒层4的接触为肖特基接触,其引出端为阳极,并向阴极方向延伸到顶部GaN层5左端,且和顶部GaN层5的接触为欧姆接触;所述势垒层4和顶部GaN层5无电极覆盖的表面被绝缘栅介质10覆盖;
增强型的p-MOS、增强型的n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容之间均具有隔离区12,且在器件表面覆盖有连续不间断的钝化层11;
所述增强型p-MOS和增强型n-MOS漏电极电气连接,引出端为输出端VOUT,且栅电极电气连接,引出端为输入端VIN;所述增强型p-MOS源电极引出端为电压端VDD;所述增强型n-MOS源电极引出端为地端GND。
进一步的,所述顶部GaN层5包括沿垂直方向自下而上依次层叠设置的uid-GaN层51、p型GaN层52、p+GaN层53。
进一步的,所述具有极化结的增强型功率HEMT的第四导电材料9上表面引出端与源电极6短接。
进一步的,所述具有极化结的增强型功率HEMT的第四导电材料9上表面引出端与栅电极8短接。
进一步的,所述势垒层4采用的材料为AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
进一步的,所述隔离区12为离子注入隔离或沟槽隔离。
本发明的有益效果:
1、基于GaN双异质结外延片的增强型的p-MOS和n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容,上述增强型p-MOS和n-MOS构成的CMOS反相器实现全GaN CMOS逻辑电路和功率器件的单片集成,减小了寄生效应,提高了芯片集成度和功率密度。
2、GaN沟道层3/势垒层4异质结界面引入的2DHG降低了增强型p-MOS导通电阻,提高了p-MOS输出电流能力。
3、GaN双异质结引入的极化结用于增强型功率HEMT和功率SBD,器件阻断状态下,极化结改善电场集中效应,调制器件漂移区电场,提高功率器件的击穿电压。
附图说明
图1是实施例1GaN双异质结单片集成芯片结构示意图;
图2是实施例1CMOS反相器结构示意图;
图3是实施例2GaN双异质结单片集成芯片结构示意图;
图4是实施例2CMOS反相器结构示意图;
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方案:
实施例1
如图1和图2所示,本例的一种基于GaN双异质结的单片集成芯片,包含增强型的p-MOS和n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容,其中增强型p-MOS和n-MOS构成CMOS反相器;
需要说明的是,在本例中,将各组成模块中采用相同材料的导电材料定义为相同标记以简化对其的描述,例如各个模块中的第一导电材料因采用相同的材料,因此均定义为第一导电材料6以便于理解和描述,其他同理。
GaN双异质结外延片包括沿垂直方向自下而上依次层叠设置的衬底层1、GaN缓冲层2、GaN沟道层3、AlGaN势垒层4、顶部GaN层5;所述AlGaN势垒层4和GaN沟道层3形成异质结,异质结界面产生二维电子气(2DEG);所述顶部GaN层5和AlGaN势垒层4形成异质结,异质结界面产生二维空穴气(2DHG);
所述增强型p-MOS制作在顶部GaN层5层的一端,其中部有凹槽,且上表面覆盖绝缘栅介质10;所述增强型p-MOS表面沿横向方向上依次分布第一导电材料6、第二导电材料8和第三导电材料7,且三者彼此有间距;所述第一导电材料6向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触,其引出端为源电极;所述第二导电材料8覆盖在顶部GaN层5凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述第三导电材料7向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触,其引出端为漏电极;
所述增强型n-MOS制作在AlGaN势垒层4上并与增强型p-MOS相邻,增强型n-MOS对应位置AlGaN势垒层4之上的顶部GaN层5被刻蚀掉;所述增强型n-MOS中部有凹槽,且上表面覆盖绝缘栅介质10;所述增强型n-MOS表面沿横向方向上依次分布第一导电材料6、第二导电材料8和第三导电材料7,且三者彼此有间距;所述第一导电材料6向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为漏电极;所述第二导电材料8覆盖在AlGaN势垒层4凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述第三导电材料7向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为源电极;
所述耗尽型n-MOS制作在AlGaN势垒层4上并与增强型n-MOS相邻,耗尽型n-MOS对应位置AlGaN势垒层4之上的顶部GaN层5被刻蚀掉,且AlGaN势垒层4上表面覆盖绝缘栅介质10;所述耗尽型n-MOS表面沿横向方向上依次分布第一导电材料6、第二导电材料8和第三导电材料7,且三者彼此有间距;所述第一导电材料6向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为源电极;所述第二导电材料8与绝缘栅介质10接触,其引出端为栅电极;所述第三导电材料7向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为漏电极;
所述电阻制作在AlGaN势垒层4上并与耗尽型n-MOS相邻,电阻对应位置AlGaN势垒层4之上的顶部GaN层5被刻蚀掉,且AlGaN势垒层4上表面覆盖绝缘栅介质10;所述电阻表面左右两端分别设置有第一导电材料6、第三导电材料7;所述第一导电材料6和第三导电材料7向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触;
所述pn结电容制作在顶部GaN层5上并与电阻相邻,pn结电容对应顶部GaN层5在pn结电容两端分别开有窗口以露出AlGaN势垒层4,将两个窗口分别定义为第一窗口和第二窗口,其中第一窗口与电阻相邻;所述第一窗口中设有第一导电材料6;所述第一导电材料6向下延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触;所述第二窗口中设有第三导电材料7;所述第三导电材料7向下延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触;所述顶部GaN层5上设置有第二导电材料8;所述第二导电材料8向下伸入顶部GaN层5中,且和顶部GaN层5的接触为肖特基接触;所述AlGaN势垒层4和顶部GaN层5无电极覆盖的表面被绝缘栅介质10覆盖;
所述具有极化结的增强型功率HEMT制作在顶部GaN层5上并与pn结电容相邻,极化结的增强型功率HEMT对应的顶部GaN层5左右两端开有窗口以露出AlGaN势垒层4,将两个窗口分别定义为第三窗口和第四窗口,且第三窗口和pn结电容相邻,且第三窗口对应的AlGaN势垒层4中间有凹槽;所述增强型功率HEMT表面覆盖绝缘栅介质10;所述第三窗口中沿横向方向上依次分布第一导电材料6、第二导电材料8,且两者之间有间距;所述第一导电材料6向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为源电极;所述第二导电材料8覆盖在AlGaN势垒层4凹槽处,与绝缘栅介质10构成MIS栅结构,其引出端为栅电极;所述第四窗口设有第三导电材料7;所述第三导电材料7向下延伸,贯穿绝缘栅介质10并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为漏电极;所述顶部GaN层5表面靠近左端窗口处设有第四导电材料9;所述第四导电材料9向下延伸,贯穿绝缘栅介质10并延伸入顶部GaN层5中,且和顶部GaN层5的接触为欧姆接触,其引出端与栅电极8短接;
所述具有极化结的功率SBD制作在顶部GaN层5上层另一端并与增强型功率HEMT相邻;具有极化结的功率SBD对应的顶部GaN层5远离增强型功率HEMT一端开有窗口以露出AlGaN势垒层4,定义为第五窗口,第五窗口中设有第三导电材料7;所述第三导电材料7向下延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为欧姆接触,其引出端为阴极;功率SBD与增强型功率HEMT相邻一端设有第二导电材料8;所述第二导电材料8向下延伸,贯穿顶部GaN层5,并延伸入AlGaN势垒层4中,且和AlGaN势垒层4的接触为肖特基接触,其引出端为阳极,并向阴极方向延伸到顶部GaN层5左端,且和顶部GaN层5的接触为欧姆接触;所述AlGaN势垒层4和顶部GaN层5无电极覆盖的表面被绝缘栅介质10覆盖;
增强型的p-MOS、增强型的n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容之间均具有离子注入隔离区12,且在器件表面覆盖有连续不间断的钝化层11;
所述增强型p-MOS和增强型n-MOS漏电极电气连接,引出端为输出端VOUT,且栅电极电气连接,引出端为输入端VIN;所述增强型p-MOS源电极引出端为电压端VDD;所述增强型n-MOS源电极引出端为地端GND。
本发明提出了一种基于GaN双异质结的单片集成芯片,通过基于GaN双异质结外延片的上述器件实现全GaN CMOS逻辑电路和功率器件的单片集成,减小了寄生效应,提高了芯片集成度和功率密度;本发明提出的GaN双异质结外延片结构,在GaN沟道层3/AlGaN势垒层4和AlGaN势垒层4/顶部GaN层5异质界面分别引入2DEG和2DHG,通过选择性保留2DHG实现低导通电阻增强型p-MOS;同时双异质结引入的极化结用于增强型功率HEMT和功率SBD,器件阻断状态下,极化结改善电场集中效应,调制器件漂移区电场,提高功率器件的击穿电压。
实施例2
如图3和图4所示,本例与实施例1的区别是,一种基于GaN双异质结的单片集成芯片,所述顶部GaN层5包括沿垂直方向自下而上依次层叠设置的uid-GaN层51、p型GaN层52、p+GaN层53;所述具有极化结的增强型功率HEMT的第四导电材料9上表面引出端与源电极6短接。相比于实例1,本例的优点是uid-GaN层51的引入提高了2DHG的迁移率,p+GaN层53的引入降低了p型欧姆接触电阻,减小了增强型p-MOS导通电阻,提高了其输出电流能力;增强型功率HEMT可通过与源电极短接的第四导电材料9进行反向续流,无需额外的反向续流二极管,有效利用芯片面积。
Claims (6)
1.一种基于GaN双异质结的单片集成芯片,包含增强型的p-MOS和n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容,其中增强型p-MOS和n-MOS构成CMOS反相器;
GaN双异质结外延片包括沿垂直方向自下而上依次层叠设置的衬底层(1)、GaN缓冲层(2)、GaN沟道层(3)、势垒层(4)、顶部GaN层(5);所述势垒层(4)和GaN沟道层(3)形成异质结,异质结界面产生二维电子气(2DEG);所述顶部GaN层(5)和势垒层(4)形成异质结,异质结界面产生二维空穴气(2DHG);
所述增强型p-MOS制作在顶部GaN层(5)层的一端,其中部有凹槽,且上表面覆盖绝缘栅介质(10);所述增强型p-MOS表面沿横向方向上依次分布增强型p-MOS第一导电材料、增强型p-MOS第二导电材料和增强型p-MOS第三导电材料,且三者彼此有间距;所述增强型p-MOS第一导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入顶部GaN层(5)中,且和顶部GaN层(5)的接触为欧姆接触,其引出端为源电极;所述增强型p-MOS第二导电材料覆盖在顶部GaN层(5)凹槽处,与绝缘栅介质(10)构成MIS栅结构,其引出端为栅电极;所述增强型p-MOS第三导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入顶部GaN层(5)中,且和顶部GaN层(5)的接触为欧姆接触,其引出端为漏电极;
所述增强型n-MOS制作在势垒层(4)上并与增强型p-MOS相邻,增强型n-MOS对应位置势垒层(4)之上的顶部GaN层(5)被刻蚀掉;所述增强型n-MOS中部有凹槽,且上表面覆盖绝缘栅介质(10);所述增强型n-MOS表面沿横向方向上依次分布增强型n-MOS第一导电材料、增强型n-MOS第二导电材料和增强型n-MOS第三导电材料,且三者彼此有间距;所述增强型n-MOS第一导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为漏电极;所述增强型n-MOS第二导电材料覆盖在势垒层(4)凹槽处,与绝缘栅介质(10)构成MIS栅结构,其引出端为栅电极;所述增强型n-MOS第三导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为源电极;
所述耗尽型n-MOS制作在势垒层(4)上并与增强型n-MOS相邻,耗尽型n-MOS对应位置势垒层(4)之上的顶部GaN层(5)被刻蚀掉,且势垒层(4)上表面覆盖绝缘栅介质(10);所述耗尽型n-MOS表面沿横向方向上依次分布耗尽型n-MOS第一导电材料、耗尽型n-MOS第二导电材料和耗尽型n-MOS第三导电材料,且三者彼此有间距;所述耗尽型n-MOS第一导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4) 的接触为欧姆接触,其引出端为源电极;所述耗尽型n-MOS第二导电材料与绝缘栅介质(10)接触,其引出端为栅电极;所述耗尽型n-MOS第三导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为漏电极;
所述电阻制作在势垒层(4)上并与耗尽型n-MOS相邻,电阻对应位置势垒层(4)之上的顶部GaN层(5)被刻蚀掉,且势垒层(4)上表面覆盖绝缘栅介质(10);所述电阻表面左右两端分别设置有电阻第一导电材料、电阻第三导电材料;所述电阻第一导电材料和电阻第三导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触;
所述pn结电容制作在顶部GaN层(5)上并与电阻相邻,pn结电容对应顶部GaN层(5)在pn结电容两端分别开有窗口以露出势垒层(4),将两个窗口分别定义为第一窗口和第二窗口,其中第一窗口与电阻相邻;所述第一窗口中设有pn结电容第一导电材料;所述pn结电容第一导电材料向下延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触;所述第二窗口中设有pn结电容第三导电材料;所述pn结电容第三导电材料向下延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触;所述顶部GaN层(5)上设置有pn结电容第二导电材料;所述pn结电容第二导电材料向下伸入顶部GaN层(5)中,且和顶部GaN层(5)的接触为肖特基接触;所述势垒层(4)和顶部GaN层(5)无电极覆盖的表面被绝缘栅介质(10)覆盖;
所述具有极化结的增强型功率HEMT制作在顶部GaN层(5)上并与pn结电容相邻,极化结的增强型功率HEMT对应的顶部GaN层(5)左右两端开有窗口以露出势垒层(4),将两个窗口分别定义为第三窗口和第四窗口,且第三窗口和pn结电容相邻,且第三窗口对应的势垒层(4)中间有凹槽;所述增强型功率HEMT表面覆盖绝缘栅介质(10);所述第三窗口中沿横向方向上依次分布增强型功率HEMT第一导电材料、增强型功率HEMT第二导电材料,且两者之间有间距;所述增强型功率HEMT第一导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为源电极;所述增强型功率HEMT第二导电材料覆盖在势垒层(4)凹槽处,与绝缘栅介质(10)构成MIS栅结构,其引出端为栅电极;所述第四窗口设有增强型功率HEMT第三导电材料;所述增强型功率HEMT第三导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为漏电极;所述顶部GaN层(5)表面靠近左端窗口处设有增强型功率HEMT第四导电材料;所述增强型功率HEMT第四导电材料向下延伸,贯穿绝缘栅介质(10)并延伸入顶部GaN层(5)中,且和顶部GaN层(5)的接触为欧姆接触;
所述具有极化结的功率SBD制作在顶部GaN层(5)上层另一端并与增强型功率HEMT相邻;具有极化结的功率SBD对应的顶部GaN层(5)远离增强型功率HEMT一端开有窗口以露出势垒层(4),定义为第五窗口,第五窗口中设有功率SBD第三导电材料;所述功率SBD第三导电材料向下延伸入势垒层(4)中,且和势垒层(4)的接触为欧姆接触,其引出端为阴极;功率SBD与增强型功率HEMT相邻一端设有功率SBD第二导电材料;所述功率SBD第二导电材料向下延伸,贯穿顶部GaN层(5),并延伸入势垒层(4)中,且和势垒层(4)的接触为肖特基接触,其引出端为阳极,并向阴极方向延伸到顶部GaN层(5)左端,且和顶部GaN层(5)的接触为欧姆接触;所述势垒层(4)和顶部GaN层(5)无电极覆盖的表面被绝缘栅介质(10)覆盖;
增强型的p-MOS、增强型的n-MOS、耗尽型n-MOS、具有极化结的增强型功率HEMT和功率SBD、电阻、pn结电容之间均具有隔离区(12),且在器件表面覆盖有连续不间断的钝化层(11);
所述增强型p-MOS和增强型n-MOS漏电极电气连接,引出端为输出端VOUT,且栅电极电气连接,引出端为输入端VIN;所述增强型p-MOS源电极引出端为电压端VDD;所述增强型n-MOS源电极引出端为地端GND。
2.根据权利要求1所述一种基于GaN双异质结的单片集成芯片,其特征在于,所述顶部GaN层(5)包括沿垂直方向自下而上依次层叠设置的uid-GaN层(51)、p型GaN层(52)、p+GaN层(53)。
3.根据权利要求1所述一种基于GaN双异质结的单片集成芯片,其特征在于,所述具有极化结的增强型功率HEMT第四导电材料(9)上表面引出端与源电极(6)短接。
4.根据权利要求1所述一种基于GaN双异质结的单片集成芯片,其特征在于,所述具有极化结的增强型功率HEMT第四导电材料(9)上表面引出端与栅电极(8)短接。
5.根据权利要求1所述一种基于GaN双异质结的单片集成芯片,其特征在于,所述势垒层(4)采用的材料为AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
6.根据权利要求1所述一种基于GaN双异质结的单片集成芯片,其特征在于,所述隔离区(12)为离子注入隔离或沟槽隔离。
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