TWI779612B - Enhancement-mode III-V semiconductor device with good lattice matching and method of making the same - Google Patents

Abstract

An enhanced III-V group semiconductor element, comprising: a substrate; a buffer layer formed on the substrate; a GaN channel layer formed on the buffer layer; an AlGaN barrier formed on the channel layer barrier layer; an etching stop layer of AlGaN formed on the barrier layer, its chemical composition formula is Al _x Ga _(1-x) N, wherein 0.4<=x<=0.7, and the etching stop of the AlGaN The thickness of the layer corresponding to the source and drain regions is smaller than the thickness of the AlGaN etch stop layer corresponding to the gate region; the pGaN layer formed in the gate region of the AlGaN etch stop layer; and the pGaN layer formed respectively in the Source and drain on the source and drain regions of the etch stop layer of AlGaN. The embodiment of the present invention provides the advantages of the enhanced III-V group semiconductor device having good lattice matching, high device breakdown voltage, and good characteristics of dynamic resistance transistors.

Description

Enhanced III-V group semiconductor device with good lattice matching and its manufacturing method

The present invention relates to an enhanced III-V group semiconductor element, and in particular to an enhanced III-V group semiconductor element with good lattice matching, high element breakdown voltage and good dynamic resistance transistor characteristics and its manufacturing method.

At present, aluminum gallium nitride/gallium nitride high-speed electron mobility field-effect transistor (AlGaN/GaN HEMT) with silicon substrate is often used because gallium nitride has inherent material advantages and excellent carrier transport characteristics. It is used in the field of microwave radio frequency and power conversion field. The traditional aluminum gallium nitride/gallium nitride transistor mainly uses its material properties to generate polarized charges at the heterojunction, and these polarized charges attract electron pairs to form a high-density two-dimensional electron gas at the junction, allowing Part of the conduction band is lower than the Fermi energy level, forming a normally open element, that is, when the gate is under zero bias, there is current conduction, so in the circuit design, an additional negative bias must be applied to the gate metal to make the element operate in the off state state.

P-type gallium nitride (pGaN) transistors form a pGaN layer by doping magnesium (Mg) in the gallium nitride layer and activating it at high temperature during epitaxy, forming a PN depletion region with aluminum gallium nitride, and then The P-type gate is formed by etching the pGaN layer in the non-gate region to avoid excessive depletion of two-dimensional electron gas, thereby achieving the effect of an enhancement device. The etching accuracy of the pGaN layer is very important. Use the inductively coupled plasma etcher to enter the mixed gas of BCl ₃ /Cl ₂ to etch the pGaN layer. If the etching is too much to the aluminum gallium nitride layer, it will cause polarization at the heterojunction The effect becomes low, and the concentration of the two-dimensional electron gas is reduced. Conversely, if there is residual pGaN outside the gate region, holes will be injected into the channel layer, resulting in a decrease in the concentration of two-dimensional electron gas, which is not good for device characteristics. To put it simply, the method of calculating the etch rate of the machine and performing the etching of the pGaN layer will cause the problem of insufficient etching or excessive etching of the pGaN layer due to the instability of the machine.

Please refer to FIG. 1 , which is a schematic vertical cross-sectional view of a conventional III-V semiconductor device. At present, in order to improve the etching accuracy, it has been proposed that an epitaxial layer of aluminum nitride (AlN) between the pGaN layer 103 and the AlGaN layer (barrier layer 105) is used as the etching stop layer 104, and BCl ₃ /Cl ₂ /SF ₆ mixed gas etching pGaN layer 103 to AlN layer (etching stop layer 104), due to the high concentration of aluminum ions will bond with the fluorine ions of SF ₆ to form aluminum fluoride (AlF ₃ ) with high hardness and non-volatile , blocking the BCl ₃ /Cl ₂ gas to continue etching to achieve the purpose of etching stop. However, adding AlN to the etch stop layer 104 causes lattice mismatch due to the large lattice difference between AlN and GaN, which affects the reliability of the gate 102 and the characteristics of the enhanced III-V semiconductor device.

According to the purpose of the present invention, there is provided an enhanced III-V group semiconductor device, which includes: a substrate; a buffer layer formed on the substrate; a GaN channel layer formed on the buffer layer; a GaN channel layer formed on the channel A barrier layer of AlGaN above the barrier layer; an etch stop layer of AlGaN formed on the barrier layer has a chemical composition formula of Al _x Ga _(1-x) N, wherein 0.4<=x<=0.7, And the thickness of the etch stop layer of the AlGaN corresponding to the source and drain regions is smaller than the thickness of the etch stop layer of the AlGaN corresponding to the gate region; the pGaN layer formed in the gate region of the etch stop layer of the AlGaN and a source and a drain respectively formed on the source region and the drain region of the AlGaN etch stop layer.

According to the purpose of the present invention, a method for manufacturing an enhanced III-V group semiconductor device is provided, which includes: providing an enhanced III-V group semiconductor structure without forming a source, drain and gate and having a two-dimensional electron gas, Wherein the channel layer and the barrier layer of the enhanced III-V semiconductor structure are respectively the channel layer of GaN and the barrier layer of AlGaN; the barrier layer of AlGaN is formed on the barrier layer of the enhanced III-V semiconductor structure an etch stop layer whose chemical composition is _{AlxGa (1-x)} N, wherein 0.4<=x<=0.7; a pGaN layer is formed on the AlGaN etch stop layer, and a mask layer is formed on the pGaN layer , to define a gate region, a source region and a drain region; performing gas plasma etching to etch all of the pGaN layer on the source region and the drain region and to etch the source region and the drain region part of the etch stop layer on the AlGaN, and remove the mask layer and use silicon dioxide etchant to remove residual aluminum fluoride for surface treatment; and in the gate region, source region and drain A gate, a source and a drain are formed on the region.

Optionally, the thickness of the AlGaN etch stop layer in the gate region is 2 to 10 nm, and the etching loss original thickness of the AlGaN etch stop layer is 10% to 90%.

Optionally, the chemical composition formula of the barrier layer of AlGaN is Al _z Ga _1-z N, 0.1<=z <=0.3, and its thickness is 5 to 30 nm.

Optionally, the pGaN layer is doped with Mg at a concentration of 10 ⁻¹⁸ to 10 ⁻²⁰ , and the pGaN layer has a thickness of 60 to 150 nm.

Optionally, the enhanced III-V semiconductor device further includes: a nucleation layer formed between the substrate and the buffer layer; and an etch stop layer forming the barrier layer and the AlGaN layers in between.

Optionally, use an inductively coupled plasma (ICP) etching machine, set the gas flow BCl ₃ /Cl ₂ /SF ₆ to 1-50sccm/1-50sccm/1-50sccm, the RF bias power to 10-100 watts, ICP The etching is carried out at a power of 100-500W and an internal pressure of 7.5-75mTorr, wherein the measured etching rate is less than 0.65nm/s, and the etching time is at least 120 seconds.

In a word, compared with the prior art, the enhanced III-V semiconductor device provided by the embodiment of the present invention has the advantages of good lattice matching, high device breakdown voltage, and good dynamic resistance transistor characteristics.

For the benefit of the examiner to understand the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail in the form of embodiments in conjunction with the accompanying drawings, and the drawings used therein, its The subject matter is only for illustration and auxiliary instructions, and not necessarily the true proportion and precise configuration of the present invention after implementation, so it should not be interpreted based on the proportion and configuration relationship of the attached drawings, and limit the scope of rights of the present invention in actual implementation. Together first describe.

In order to solve the technical problem of poor lattice matching in the prior art, the embodiment of the present invention uses an AlGaN layer as an etching stop layer, wherein the chemical composition formula is _{AlxGa (1-x)} N, and x is 0.4 to 0.7 (including 0.4 and 0.7), which is mainly to reduce the molar concentration of aluminum to make the lattice match better. Afterwards, when the mixed gas of BCl ₃ /Cl ₂ /SF ₆ is introduced to etch the etching stop layer from P-type gallium nitride to aluminum gallium nitride, due to the high concentration of aluminum ions will bond with the fluorine ions of SF ₆ to form a higher hardness And the non-volatile aluminum fluoride (AlF ₃ ), blocks the BCl ₃ /Cl ₂ gas to continue etching, and then the silicon dioxide etching solution removes the residual aluminum fluoride, ensuring that the device characteristics will not be affected by aluminum fluoride. In addition to improving the lattice matching of the transistor and enhancing the reliability of the gate, the above-mentioned method can be used because the etch stop layer of AlGaN is epitaxially formed between the P-type GaN layer and the barrier layer of AlGaN. It can have a high etching selectivity, so it can improve the transistor characteristics of the breakdown voltage and dynamic resistance of the device.

First, please refer to FIG. 3E , the final product of the method for manufacturing an enhanced III-V group semiconductor device with good lattice matching according to the embodiment of the present invention is shown in FIG. 3E . The enhanced III-V group semiconductor device includes a source 100, a drain 101, a gate 102, a P-type gallium nitride layer 103, an etching stop layer 104A of aluminum gallium nitride, a barrier layer 105 of aluminum gallium nitride, a nitrogen GaN channel layer 106 , buffer layer 107 and substrate 108 . The AlGaN etching stop layer 104A has a chemical composition formula of _{AlxGa (1-x)} N, where 0.4<=x<=0.7, and its thickness on the gate region is 2 to 10 nm ( Including two endpoints of 2nm and 10nm), and the etching loss of the original thickness is 10% to 90% (including two endpoints of 10% and 90%).

The buffer layer 107 is formed on the substrate 108 , and optionally, there may be a nucleation layer (not shown) between the buffer layer 107 and the substrate 108 in the vertical direction. The GaN channel layer 106 is formed on the buffer layer 107 , and the AlGaN barrier layer 105 is formed on the GaN channel layer 106 . The AlGaN etch stop layer 104A is formed on the AlGaN barrier layer 105, and the left part, middle part and right part in the horizontal direction correspond to the source region, the gate region and the drain region respectively , wherein the thickness of the left part and the right part of the etch stop layer 104A of AlGaN is smaller than the thickness of the middle part of the etch stop layer 104A of AlGaN, and the thickness ratio is related to the original thickness of the etch loss, and the etch stop of AlGaN The thickness of the middle portion of the layer 104A is about 1:0.9 to 1:0.1 (both endpoint values of 1:0.9 and 1:0.1 are included) compared to the thickness of the left portion and the right portion of the AlGaN etch stop layer 104A. . In addition, optionally, in the vertical direction, the AlGaN etching stop layer 104A and the AlGaN barrier layer 105 may have a cap layer (not shown). The source 100 and the drain 101 are respectively located on the left part and the right part of the AlGaN etching stop layer 104A, the P-type GaN layer 103 is located on the middle part of the AlGaN etching stop layer 104A, and the gate The pole 102 is located on the P-type GaN layer 103 .

The substrate 108 can be, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), sapphire substrate or other substrates capable of epitaxially enhancing III-V semiconductors, and the invention is not limited thereto. If a nucleation layer is selected, the nucleation layer is, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer or a high-temperature AlN layer, and the present invention is not limited thereto. The buffer layer 107 can be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a super crystal (super lattice) AlN/GaN layer, a super crystal AlGaN/GaN layer, a super crystal AlN/AlGaN, a carbon-doped GaN layer, an iron-doped GaN layer or an undoped GaN layer, and the present invention is not limited thereto. When the buffer layer 107 is an AlGaN layer, the chemical composition formula of AlGaN is _{AlyGa1 -yN} , 0.05<=y. The chemical composition formula of AlGaN in the barrier layer 105 is AlzGa1 _{-zN ,} 0.1<=z<=0.3, and the thickness is 5 to 30nm (including the two endpoints of 5nm and 30nm). If a covering layer is selected, the covering layer is, for example, a GaN layer, a GaN layer, an AlN layer, an AlGaN layer or an InGaN layer.

Each of the source electrode 100 and the drain electrode 101 is a metal stack layer forming an ohmic contact electrode, which for example includes a first structure layer and a second structure layer arranged from bottom to top, and the first structure layer may be a Ti/Al double layer. layer structure, and the second structure layer can be Ni/Au double layer structure, Ti/Ta double layer structure, Ti layer, TiN layer, Cu layer or W layer, and the present invention is not limited thereto. The gate 102 is a Schottky electrode controlling a channel, which is a metal stack layer formed by at least one of Ti, Al, N, and Au, such as a Ni/Au double-layer structure, and the invention is not limited thereto. The p-type gallium nitride layer 103 is doped with Mg at a concentration of 10 ⁻¹⁸ to 10 ⁻²⁰ (both endpoints of 10 ⁻¹⁸ and 10 ⁻²⁰ are included), and the thickness of the p-type gallium nitride layer 103 is 60 to 60 to 150nm (including the two endpoints of 60nm and 150nm).

Next, please refer to FIG. 2 and FIG. 3A to FIG. 3E. FIG. A schematic cross-sectional view of each step of the method for manufacturing an enhanced III-V group semiconductor device with good lattice matching according to the embodiment. First, in step S21, an enhanced III-V group semiconductor structure with no source, drain and gate and two-dimensional electron gas is provided. As shown in FIG. 3A, the enhanced III-V group semiconductor structure includes The substrate 108 , the buffer layer 107 , the GaN channel layer 106 and the AlGaN barrier layer 105 are stacked sequentially from top to bottom. Next, in step S22, an etching stop layer 104B of AlGaN is formed on the barrier layer 105 of AlGaN of the enhanced III-V semiconductor structure, as shown in FIG. 3B, wherein the AlGaN The chemical composition formula of AlGaN in the etching stop layer 104A is _{AlxGa (1-x)} N, 0.4<=x<=0.7, and its thickness is between 2nm and 10nm (including two endpoint values of 2nm and 10nm). ). Then, in step S23, a P-type GaN layer 103A and a mask layer 109 (for example, but not limited to a photoresist material) are sequentially formed on the AlGaN etching stop layer 104A to define a gate , source and drain regions, as shown in Figure 3C, wherein the P-type gallium nitride layer 103A is doped with Mg at a concentration of 10 ^-18 to 10 ^-20 (including the two endpoints of 10 ^-18 and 10 ^-20 value), and the thickness of the P-type GaN layer 103A is 60 to 150 nm (including the two endpoint values of 60 nm and 150 nm).

Afterwards, in step S24, gas plasma etching is performed, and the mask layer 109 is removed and the residual aluminum fluoride is removed using a silicon dioxide etching solution for surface treatment, wherein the P-type GaN layer 103A corresponds to the source region and the drain region. The left and right portions of the pole region are completely etched, leaving only the P-type GaN layer 103 corresponding to the gate region, and the left and right portions of the AlGaN etching stop layer 104A corresponding to the source region and the drain region for about 10% to 90% are etched (etching loss of 10% to 90% of the original thickness) to form the etched AlGaN etch stop layer 104 , as shown in FIG. 3D . Further, in step S24, an inductively coupled plasma (ICP) etching machine is used, the gas flow rate BCl ₃ /Cl ₂ /SF ₆ is set to 1-50 sccm/1-50 sccm/1-50 sccm, and the RF bias power is 10 -100 watts, ICP power of 100-500W and cavity internal pressure of 7.5-75mTorr for etching, wherein the measured etching rate is less than 0.65nm/s, and the etching stops when the etching period is 120 seconds, and etch to 240 Seconds (that is, the actual etching time is at least 120 seconds), to prove that the AlGaN etching stop layer can solve the problem of excessive etching, and the calculated etching selectivity ratio is as high as 37.5:1. Next, in step S25 , a source 100 , a drain 101 and a gate 102 are respectively formed in the source region, the drain region and the gate region, as shown in FIG. 3E .

In summary, the embodiments of the present invention provide an enhanced III-V group semiconductor device with good lattice matching, high device breakdown voltage and good dynamic resistance transistor characteristics and a manufacturing method thereof. Further, after X-ray diffraction measurement (XRD), the helical dislocation and edge dislocation of the enhanced III-V group semiconductor device according to the embodiment of the present invention are compared with the helical dislocation and edge dislocation of the traditional III-V group semiconductor device. The disparity is low (indicating good grid matching); through electrical measurement, the threshold voltage, leakage current, source-drain turn-on resistance (R _{DS_ON} ) and The dynamic resistance ratio is lower than the threshold voltage, leakage current, source-drain turn-on resistance and dynamic resistance ratio of traditional III-V semiconductor devices. The enhanced III-V semiconductor device of the embodiment of the present invention has saturation current, breakdown The voltage is higher than the saturation current and breakdown voltage of traditional III-V semiconductor devices.

Looking at the above, it can be seen that the present invention has indeed achieved the effect of the desired enhancement under the breakthrough of the previous technology, and it is not easy for those who are familiar with the art to think about it. Moreover, the present invention has not been disclosed before the application, and its features Progressiveness and practicability have obviously met the requirements for patent application. I file a patent application in accordance with the law. I sincerely request your office to approve this invention patent application to encourage inventions. I am very grateful.

The above-described embodiments are only to illustrate the technical ideas and characteristics of the present invention, and its purpose is to enable those skilled in this art to understand the content of the present invention and implement it accordingly, and should not limit the patent scope of the present invention. That is to say, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

100: source 101: drain 102: Gate 103, 103A: pGaN layer 104, 104A, 104B: etch stop layer 105: Barrier layer 106: Channel layer 107: buffer layer 108: Substrate 109: mask layer S21～S25: Steps

The multiple drawings of the present invention are only used to make the present invention easy to be understood by those skilled in the art to which the present invention belongs, and the dimensions and configuration relationships thereof are only for illustration, and are not used to limit the present invention. A brief description of each of the drawings is as follows : 1 is a schematic vertical cross-sectional view of a conventional III-V semiconductor device; 2 is a flow chart of a method for manufacturing an enhanced III-V group semiconductor element with good lattice matching according to an embodiment of the present invention; and 3A to 3E are cross-sectional schematic diagrams of finished products in each step of the method for manufacturing an enhanced III-V group semiconductor device with good lattice matching according to an embodiment of the present invention.

100: source

101: drain

102: Gate

103: pGaN layer

104A: etch stop layer

105: Barrier layer

106: Channel layer

107: buffer layer

108: Substrate

Claims (10)

An enhanced III-V group semiconductor element, comprising: a substrate (108); a buffer layer (107) formed on the substrate (108); a GaN channel formed on the buffer layer (107) layer (106); an AlGaN barrier layer (105) formed on the channel layer (106); an AlGaN etch stop layer (104A) formed on the barrier layer (105), Its chemical composition formula is Al _x Ga _(1-x) N, wherein 0.4<=x<=0.7, and the thickness of the etching stop layer (104A) of the AlGaN corresponding to the source and drain regions is smaller than that of the AlGaN The etch stop layer (104A) has a thickness corresponding to the gate region; a pGaN layer (103) formed in the gate region of the AlGaN etch stop layer (104A); and the etch stop layer ( 104A) a source (100) and a drain (101) on the source region and the drain region; wherein the etching loss of the AlGaN etch stop layer (104A) is 10% to 90% of the original thickness. The enhanced III-V group semiconductor device according to claim 1, wherein the thickness of the AlGaN etch stop layer (104A) in the gate region is 2 to 10 nm. The enhanced III-V group semiconductor device as claimed in claim 2, wherein the chemical composition formula of the AlGaN barrier layer (105) is Al _z Ga _1-z N, 0.1<=z<=0.3, and its The thickness is 5 to 30 nm. The enhanced III-V group semiconductor device according to claim 3, wherein the pGaN layer (103) is doped with Mg at a concentration of 10 ^-18 to 10 ^-20 , and the thickness of the pGaN layer (103) 60 to 150nm. The enhanced III-V group semiconductor device according to one of claims 1-4, further comprising: a nucleation layer formed between the substrate (108) and the buffer layer (107); and forming the A cover layer between the barrier layer (105) and the AlGaN etch stop layer (104A). A method for manufacturing an enhanced III-V group semiconductor device, comprising: providing an enhanced III-V group semiconductor structure with no source, drain and gate formed and having a two-dimensional electron gas, wherein the enhanced III-V A channel layer (106) and a barrier layer (105) of the group semiconductor structure are respectively the channel layer (106) of the GaN and the barrier layer (105) of the AlGaN; An AlGaN etching stop layer (104) is formed on the barrier layer (105) of the semiconductor structure, and its chemical composition formula is _{AlxGa (1-x)} N, wherein 0.4<=x<=0.7; in the AlGaN A pGaN layer (103) is formed on the etching stop layer (104), and a mask layer (109) is formed on the pGaN layer (103) to define a gate region, a source region and a drain region; slurry etching to etch all of the pGaN layer (103) on the source and drain regions and part of the etch stop layer (104) of AlGaN on the source and drain regions, and remove The mask layer (109) is treated with a silicon dioxide etchant to remove residual aluminum fluoride; and a gate (102) is formed on the gate region, the source region and the drain region, A source (100) and a drain (101). The method for manufacturing an enhanced III-V group semiconductor device as claimed in claim 6, wherein the thickness of the AlGaN etch stop layer (104A) in the gate region is 2 to 10 nm, and the AlGaN etch stop layer ( 104A) has an etching loss of 10% to 90% of the original thickness. The method for manufacturing an enhanced III-V semiconductor device as described in Claim 7, wherein the chemical composition formula of the AlGaN barrier layer (105) is Al _z Ga _1-z N, 0.1<=z<=0.3 , and its thickness is 5 to 30 nm. The method for manufacturing an enhanced III-V group semiconductor device as claimed in claim 8, wherein the pGaN layer (103) is doped with Mg at a concentration of 10 ^-18 to 10 ^-20 , and the pGaN layer (103 ) with a thickness of 60 to 150 nm. The method for manufacturing an enhanced III-V group semiconductor device as described in one of claim items 6-9, wherein an inductively coupled plasma (ICP) etching machine is used, and the gas flow rate BCl ₃ /Cl ₂ /SF ₆ is set to 1- 50sccm/1-50sccm/1-50sccm, RF bias power of 10-100 watts, ICP power of 100-500W and cavity internal pressure of 7.5-75mTorr for etching, wherein the measured etching rate is less than 0.65nm/s, And the etching time is at least 120 seconds.

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