CN104201104A - Manufacturing method for gallium nitride-based enhanced device - Google Patents
Manufacturing method for gallium nitride-based enhanced device Download PDFInfo
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- CN104201104A CN104201104A CN201410456503.XA CN201410456503A CN104201104A CN 104201104 A CN104201104 A CN 104201104A CN 201410456503 A CN201410456503 A CN 201410456503A CN 104201104 A CN104201104 A CN 104201104A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 27
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000460 chlorine Substances 0.000 claims abstract description 9
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 9
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 5
- 238000005036 potential barrier Methods 0.000 claims description 55
- CHPZKNULDCNCBW-UHFFFAOYSA-N gallium nitrate Chemical compound [Ga+3].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O CHPZKNULDCNCBW-UHFFFAOYSA-N 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229940044658 gallium nitrate Drugs 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 9
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 8
- 229910001882 dioxygen Inorganic materials 0.000 claims description 8
- 238000009616 inductively coupled plasma Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 2
- 210000002381 plasma Anatomy 0.000 abstract description 17
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 15
- 230000004888 barrier function Effects 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 238000012876 topography Methods 0.000 abstract description 3
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- 229910004140 HfO Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000013213 extrapolation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method for a gallium nitride-based enhanced device. According to the manufacturing method disclosed by the invention, a two-step etching method is mainly used, the first step is rapid etching, and chlorine or boron chloride is used for etching 1/3 to 2/3 of the total thickness of heterojunction barrier layers; the second step is slow etching, an oxygen plasma reaction technology is adopted, and the remainder heterojunction barrier layers are oxidized by oxygen plasmas so as to oxidize the surfaces of the heterojunction barrier layers; then a wet etching technology is adopted, and the heterojunction barrier layers are etched off one by one until the remainder thickness of the heterojunction barrier layers is 0.5-2nm. According to the manufacturing method disclosed by the invention, surface topography after etching of III-group nitride etching is effectively improved, and surface electric leakage after etching is reduced; the method is capable of increasing the two-dimensional electron gas migration rate of the channel of a gallium nitride-based groove gate enhanced device, and obtaining the high-performance gallium nitride-based enhanced device. The manufacturing method disclosed by the invention is especially suitable for the gallium nitride-based enhanced device.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of manufacture method of gallium nitrate based enhancement device.
Background technology
As the Typical Representative of third generation wide bandgap semiconductor, gallium nitride (GaN) material has a lot of good characteristics: high critical breakdown electric field (～3.5 × 10
6v/cm), high electron mobility (～2000cm
2/ Vs), high two-dimensional electron gas (2-DEG) concentration (～10
13cm
-2) and good hot operation ability etc.Based on AlGaN/GaN (or AlInN/GaN) heterojunction High Electron Mobility Transistor (HEMT) (or HFET HFET, modulation-doped FET MODFET, below be referred to as HEMT device) be applied at semiconductor applications, be especially applied to radio communication, satellite communication etc. in RF/Microwave field.In addition, such device based on broad stopband gallium nitride material has the characteristics such as reverse blocking voltage is high, forward conduction resistance is low, operating frequency is high, efficiency is high, can meet that following power electronic system is more high-power to device for power switching, higher frequency, the more requirement of small size, more low-power consumption and more severe operational environment.
Transistor occupies extremely important status at semiconductor applications, and in recent years, the heterojunction transistor based on gallium nitride material has also been obtained large development.But because of gallium nitride radical heterojunction piezoelectric polarization and spontaneous polarization generation two-dimensional electron gas, making traditional gallium nitride based transistor is depletion device (threshold voltage is negative value), is not easy to the practical application of power electronic system.Therefore, the research tool of enhancement type gallium nitride based transistor is of great significance.
Realize enhancement type gallium nitride transistor, target is the two-dimensional electron gas that exhausts grid below, thereby makes the threshold voltage of device be greater than zero.Relatively common are at present three kinds of schemes.The first scheme is to inject electronegative ion, after Implantation, the conduction band of potential barrier of heterogenous junction layer can be improved, and exhausts the two-dimensional electron gas of anion injection zone, realizes enhancement device.First scheme is growth p-GaN gate technique, by the conduction band of the whole heterojunction of p-GaN lifting below grid, thereby makes to exhaust the two-dimensional electron gas in heterojunction conducting channel, realizes enhancement device.The third scheme is that attenuate grid below potential barrier of heterogenous junction layer forms notched gates, reduces polarized electric field, exhausts the two-dimensional electron gas in raceway groove, realizes enhancement device.In these methods, notched gates technique is easier to technique and realizes and have higher stability, becomes a kind of GaN enhancement device implementation of the advantage of having more.
The simplest method efficiently of potential barrier of heterogenous junction layer of attenuate grid below is dry etching (inductively coupled plasma etching (ICP etching) or reactive ion etching (RIE etching)), the main chlorine or boron chloride or both plasmas of mixing of using carries out etching at present, although it is high that this method forms the efficiency of groove, its defect is that etch rate is very fast and wayward, etching rear surface roughness is high and etching causes lattice damage can greatly reduce the two-dimensional electron gas mobility in enhancement type channel and then greatly reduce the performance of enhancement device.
Summary of the invention
Object of the present invention, is exactly for the problems referred to above, and the manufacture method of a kind of high efficiency, high accuracy, low damage, stable gallium nitrate based enhancement device is provided.
Technical scheme of the present invention: a kind of manufacture method of gallium nitrate based enhancement device, it is characterized in that, comprise the following steps:
The first step: epitaxial growth stress-buffer layer, gallium nitride layer and potential barrier of heterogenous junction layer successively on Semiconductor substrate upper strata;
Second step: adopt photoetching technique, generate metal ohmic contact in the leakage source region of potential barrier of heterogenous junction layer upper surface two terminal device;
The 3rd step: the potential barrier of heterogenous junction layer upper surface growth of passivation layer between metal ohmic contact;
The 4th step: adopt inductively coupled plasma etching technology, use the potential barrier of heterogenous junction layer at the quick etched features area of grid of the plasma place of III group-III nitride gas, generate groove; Etch period is 20～1200 seconds, and etching depth is 1/3rd to 2/3rds of potential barrier of heterogenous junction layer gross thickness; Described III group-III nitride gas is the one in chlorine, boron chloride and chlorine and boron chloride mist;
The 5th step: adopt oxygen gas plasma reaction technology, use in oxygen gas plasma oxidation the 4th step the not potential barrier of heterogenous junction layer of etching, by potential barrier of heterogenous junction layer surface oxidation; Then adopt wet etching technique, device is put into acid solution or aqueous slkali, remove surface oxide layer;
The 6th step: adopting sub-nanometer etching technology, repeat etching potential barrier of heterogenous junction layer, is 0.5～2nm by potential barrier of heterogenous junction layer eating away to residual thickness;
The 7th step: at potential barrier of heterogenous junction layer upper surface groove deposition dielectric, generate gate insulator; After deposit dielectric, carry out high-temperature quick thermal annealing;
The 8th step: adopt photoetching technique, generate gate metal on gate insulator.
Beneficial effect of the present invention is, the present invention is technical the gallium nitrate based enhancement device of notched gates, adopt two-step etching method, in ensureing etched recesses efficiency, improve the surface topography of etching late barrier layer, greatly reduced surface leakage, and can accurately control etching precision and reach dust magnitude
the gallium nitrate based enhancement device of notched gates that the present invention announces retains the barrier layer of 0.5～2nm in notched gates etching, this remaining barrier layer not only can exhaust the two-dimensional electron gas of grooved area but also can avoid the damage of etching process applying plasma to heterojunction conducting channel, thereby significantly improve the mobility of two-dimensional electron gas in enhancement type channel, the conducting resistance of device is significantly reduced, and the current density of device significantly improves.In addition, two-step etching of the present invention, all carries out at low temperatures, the damage of having avoided high temperature etching or high-temperature oxydation to cause device performance, therefore utilize method that the present invention announces can be acquired can better gallium nitrate based enhancement device.
Brief description of the drawings
Fig. 1 is the structural representation of embodiment;
Fig. 2 be in the manufacturing process flow of embodiment after substrate top surface generates epitaxial loayer structural representation;
Fig. 3 be in the manufacturing process flow of embodiment at heterojunction upper surface deposit ohmic metal, and form ohmic contact;
Fig. 4 is at heterojunction upper surface growth one deck dielectric layer in the manufacturing process flow of embodiment;
Fig. 5 is the dielectric layer that etches away grooved area upper surface in the manufacturing process flow of embodiment;
Fig. 6 carries out first step etching to grooved area potential barrier of heterogenous junction layer in the manufacturing process flow of embodiment;
Fig. 7 carries out second step etching to grooved area potential barrier of heterogenous junction layer in the manufacturing process flow of embodiment;
Fig. 8 is at heterojunction upper surface growth one deck insulating medium layer in the manufacturing process flow of embodiment;
Fig. 9 is at grooved area deposit gate metal in the manufacturing process flow of embodiment;
Figure 10 is groove surfaces pattern and the roughness that uses atomic force microscope to obtain after dry etching;
Figure 11 is groove surfaces pattern and the roughness that uses atomic force microscope to obtain after two-step etching etching;
Figure 12 is the depth of groove figure that in embodiment, sample uses atomic force microscope to obtain after two-step etching etching;
Figure 13 is the gallium nitrate based enhancement device transfer characteristic curve of high-performance and gallium nitrate based depletion device transfer characteristic curve comparison diagram prepared by the embodiment of the present invention;
Figure 14 is the gallium nitrate based enhancement device output characteristic curve of high-performance prepared by the embodiment of the present invention;
Figure 15 is low mobility curve of the gallium nitrate based enhancement device of high-performance prepared by the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail
The present invention has announced a kind of high efficiency, high accuracy, low damage, stable III group-III nitride (III-Nitride) lithographic method, in ensureing etching efficiency, effectively improve the surface topography after III group-III nitride etching, reduce the surface leakage after etching, the method can improve the two-dimensional electron gas mobility of gallium nitrate based notched gates enhancement device raceway groove, obtains the gallium nitrate based enhancement device of high-performance.
For achieving the above object, the present invention adopts following technical scheme:
A preparation method for the gallium nitrate based enhancement device of high-performance based on two-step etching, it comprises the following steps:
(1) utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating, gallium nitride layer and potential barrier of heterogenous junction layer successively on substrate;
(2) adopt photoetching technique, evaporation (or sputter) ohmic metal, and under pure nitrogen gas environment, carry out rapid thermal annealing;
(3) adopt ion implantation technique or dry etching mesa technique, form device interval from;
(4) using plasma strengthens chemical vapour deposition (CVD) or low-pressure chemical vapour deposition (CVD) or ald or inductively coupled plasma chemical vapour deposition (CVD) or physical vapour deposition (PVD) or magnetron sputtering, the etch mask layer of one deck dielectric layer as notched gates etching of evenly growing on potential barrier of heterogenous junction layer;
(5) adopt two-step etching below grid potential barrier of heterogenous junction layer to forming a groove between Two-dimensional electron gas channel.The first step is quick etching, adopt inductively coupled plasma etching technology, the quick etching potential barrier of heterogenous junction of the plasma layer that uses chlorine or boron chloride or both mixing, etch period is 20～1200 seconds, etching depth is 1/3rd to 2/3rds of potential barrier of heterogenous junction layer gross thickness.Second step is etching at a slow speed, adopts oxygen gas plasma reaction technology, uses oxygen gas plasma to be oxidized remaining potential barrier of heterogenous junction layer, by potential barrier of heterogenous junction layer surface oxidation; Then adopt wet etching technique, gallium nitride-based material is put into acid solution or aqueous slkali, remove surface oxide layer.Second step at a slow speed lithographic technique is Ya Na meter etching, adjusts the parameters such as oxygen flow, RF power, chamber pressure, cavity temperature, and lithographic technique speed is 0.1～1nm/ time at a slow speed, as shown in table 1.Repeat this lithographic technique at a slow speed, potential barrier of heterogenous junction layer is in layer etched away, until potential barrier of heterogenous junction layer residual thickness is 0.5～2nm.
(6) adopt ald or plasma enhanced chemical vapor deposition or low-pressure chemical vapour deposition (CVD) or inductively coupled plasma chemical vapour deposition (CVD) or physical vapour deposition (PVD) or magnetron sputtering, dielectric on potential barrier of heterogenous junction layer surface deposition, as gate insulator.
(7) after deposit dielectric, carry out high-temperature quick thermal annealing, improve the interface quality between gate insulator quality and gate medium and semiconductor, reduce the removable electric charge in gate insulator dielectric layer.Annealing temperature is 400～500 degrees Celsius, and the time is 1～10 minute.
(8) adopt photoetching technique, evaporation (or sputter) gate metal.
The speed of etching at a slow speed under table 1. different condition
Further, the described potential barrier of heterogenous junction layer of step (1) is a kind of or any several combination in AlGaN, AlInN, InGaN, AlInGaN, AlN material, and this potential barrier of heterogenous junction layer is non-doped layer or N-shaped doped layer;
Further, the described ohmic metal of step (2) for but be not limited to Ti/Al/Ni/Au, rapid thermal annealing temperature is 850 DEG C～900 DEG C, the time is 30～50 seconds, the method for deposit ohmic metal is electron beam evaporation or magnetron sputtering.
Further, the described two-step etching of step (5), first step etching temperature is 20～70 DEG C, second step etching temperature is 20～150 DEG C, is Cryo-etching.
Further, the described insulating medium layer of step (6) is Al
2o
3, AlN, SiO
2, SiNx, HfO
2, MgO, Sc
2o
3, Ga
2o
3, LaLuO
3, any or any several combination in AlHfOx, HfSiON, thickness is between 1～200nm.
Further, the described gate metal of step (8) comprises any or any several combination in Ni, Au, Ir, Pd, Pt, Mo, Se, Be, W, TiN, Ta, TaN.
Embodiment:
The structure chart of the present embodiment as shown in Figure 1, comprise substrate 1 and grow in the epitaxial loayer on substrate 1, wherein epitaxial loayer is followed successively by stress-buffer layer 2 from lower to upper, gallium nitride layer 3 and potential barrier of heterogenous junction layer 4, in source, evaporation (or sputter) metal ohmic contact 5 on drain region, even growth one deck dielectric layer 6 etch mask layers as grid lower grooves etching on potential barrier of heterogenous junction layer 4, use two-step etching to form a groove between potential barrier of heterogenous junction layer 4 to GaN layer 3 at grid lower zone, at potential barrier of heterogenous junction layer 4 surface deposition dielectric 7, area of grid evaporation (or sputter) gate metal 8.
Potential barrier of heterogenous junction layer 4 is a kind of or any several combination in AlGaN, AlInN, InGaN, AlInGaN, AlN material, and this potential barrier of heterogenous junction layer is non-doped layer or N-shaped doped layer; GaN layer 3 is high resistant GaN layer.
Insulating medium layer 7 is Al
2o
3, AlN, SiO
2, SiNx, HfO
2, MgO, Sc
2o
3, Ga
2o
3, LaLuO
3, any or any several combination in AlHfOx, HfSiON, thickness is between 1～200nm.
Metal ohmic contact 5 is Ti/Al/Ni/Au alloy, and gate metal 8 comprises following one or more combinations Ni, Au, Ir, Pd, Pt, Mo, Se, Be, W, TiN, Ta or TaN.
Fig. 2-Fig. 9 is the preparation method's of the gallium nitrate based enhancement device of high-performance of the present invention processing step schematic diagram, and its technological process is as follows:
(1) utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating 2, GaN layer 3 and potential barrier of heterogenous junction layer 4 successively on substrate 1, as shown in Figure 2;
(2) adopt photoetching technique, evaporation (or sputter) metal ohmic contact 5, and carry out rapid thermal annealing, as shown in Figure 3;
(3) adopt ion implantation technique or dry etching mesa technique, form device interval from;
(4) using plasma strengthens chemical vapour deposition (CVD), one deck passivation layer of evenly growing on potential barrier of heterogenous junction layer, as shown in Figure 4.Adopt photoetching technique, make grooved area figure by lithography, the passivation layer above grooved area is etched away with wet etching or dry etching, all the other passivation layers are as the etch mask layer of groove etching, as shown in Figure 5;
The object of four steps is before groove etching above, and non-grooved area is protected with passivation layer, and grooved area is out exposed, carries out etching at next step.
(5) adopt two-step etching below grid potential barrier of heterogenous junction layer 4 to forming a groove between Two-dimensional electron gas channel.The first step is quick etching, adopt inductively coupled plasma etching technology, use chlorine and the quick etching potential barrier of heterogenous junction of boron chloride hybrid plasma layer, etch period is 150 seconds, etching depth is about 2/3rds (15nm) of potential barrier of heterogenous junction layer gross thickness, as shown in Figure 6.Second step is etching at a slow speed, adopts oxygen gas plasma reaction technology, uses oxygen gas plasma oxidation potential barrier of heterogenous junction layer, by potential barrier of heterogenous junction layer surface oxidation; Then adopt wet etching technique, it is 20% dilute hydrochloric acid solution that gallium nitride-based material is put into concentration, removes surface oxide layer.Lithographic technique is Ya Na meter etching at a slow speed, and the speed of lithographic technique is 0.5nm/ time at a slow speed.Repeat this lithographic technique ten times at a slow speed, etching depth is about 5nm, as shown in Figure 7.Gallium nitride-based material potential barrier of heterogenous junction layer thickness is 21.5nm, uses atomic force microscope to record now potential barrier of heterogenous junction layer etching depth and is about 20nm, and residue 1.5nm, as shown in figure 12.
(6) adopt technique for atomic layer deposition, at potential barrier of heterogenous junction layer 4 surface deposition 20nm dielectric, as gate insulator 7, as shown in Figure 8.
(7) after deposit dielectric, carry out 400 degrees Celsius, the rapid thermal annealing of 10 minutes, improves the interface quality between gate insulator 7 quality and gate insulator 7 and potential barrier of heterogenous junction layer 4, reduces the removable electric charge in gate insulator dielectric layer 7.
(8) adopt photoetching technique, evaporation (or sputter) gate metal 8, as shown in Figure 9.
Two-step etching etching potential barrier of heterogenous junction layer 4, can accurately control etching precision and reach dust magnitude
in notched gates etching, retain the barrier layer of 1.5nm, this remaining barrier layer not only can exhaust the two-dimensional electron gas of grooved area but also can avoid the damage of etching process applying plasma to heterojunction conducting channel, thereby significantly improve the mobility of two-dimensional electron gas in enhancement type channel, the conducting resistance of device is significantly reduced, and the current density of device significantly improves.In addition, two-step etching of the present invention, all carries out at low temperatures, the damage of having avoided high temperature etching or high-temperature oxydation to cause device performance, therefore utilize method that the present invention announces can be acquired can better gallium nitrate based enhancement device.
Compare the plasma dry etching that simple employing chlorine or boron chloride or both mix, utilize the III group-III nitride surface roughness of the two-step etching institute etching that the present invention announces to reduce by 65.4%, as shown in Figure 10,11.
The control of the thickness of gate insulator 7 should meet gate metal 8 can well control the conductive characteristic of raceway groove, also will keep good gate insulator.
Figure 13 is transfer characteristic curve and the gallium nitrate based depletion device transfer characteristic curve comparison diagram of the prepared gallium nitrate based enhancement device of high-performance of this embodiment.Figure 14 is the gallium nitrate based enhancement device output characteristic curve of high-performance prepared by the embodiment of the present invention; It is 1.4V that this enhancement device linear extrapolation obtains threshold voltage, maximum transconductance is 172mS/mm, and when gate source voltage is 8V, maximum output current is 630mA/mm, maximum transconductance and maximum output current and depletion device basically identical (as Figure 13), low mobility is 272cm
2/ Vs (as Figure 15).
Claims (1)
1. a manufacture method for gallium nitrate based enhancement device, is characterized in that, comprises the following steps:
The first step: epitaxial growth stress-buffer layer, gallium nitride layer and potential barrier of heterogenous junction layer successively on Semiconductor substrate upper strata;
Second step: adopt photoetching technique, generate metal ohmic contact in the leakage source region of potential barrier of heterogenous junction layer upper surface two terminal device;
The 3rd step: the potential barrier of heterogenous junction layer upper surface growth of passivation layer between metal ohmic contact;
The 4th step: adopt inductively coupled plasma etching technology, use the potential barrier of heterogenous junction layer at the quick etched features area of grid of the plasma place of III group-III nitride gas, generate groove; Etch period is 20～1200 seconds, and etching depth is 1/3rd to 2/3rds of potential barrier of heterogenous junction layer gross thickness; Described III group-III nitride gas is the one in chlorine, boron chloride and chlorine and boron chloride mist;
The 5th step: adopt oxygen gas plasma reaction technology, use in oxygen gas plasma oxidation the 4th step the not potential barrier of heterogenous junction layer of etching, by potential barrier of heterogenous junction layer surface oxidation; Then adopt wet etching technique, device is put into acid solution or aqueous slkali, remove surface oxide layer;
The 6th step: adopting sub-nanometer etching technology, repeat etching potential barrier of heterogenous junction layer, is 0.5～2nm by potential barrier of heterogenous junction layer eating away to residual thickness;
The 7th step: at potential barrier of heterogenous junction layer upper surface groove deposition dielectric, generate gate insulator; After deposit dielectric, carry out high-temperature quick thermal annealing;
The 8th step: adopt photoetching technique, generate gate metal on gate insulator.
Priority Applications (1)
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| CN106158960A (en) * | 2015-04-17 | 2016-11-23 | 北京大学 | GaN enhancement mode MOSFET and preparation method is formed based on digitized wet method grid lithographic technique |
| CN106981514A (en) * | 2017-05-25 | 2017-07-25 | 中国电子科技集团公司第十三研究所 | The enhanced GaN transistor device of notched gates based on nano-channel |
| CN107230620A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The preparation method of gallium nitride transistor |
| CN107230726A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The manufacture method of enhancement type gallium nitride transistor |
| CN107393954A (en) * | 2017-08-02 | 2017-11-24 | 电子科技大学 | A kind of GaN hetero-junctions vertical field effect pipe |
| CN107623032A (en) * | 2017-10-24 | 2018-01-23 | 电子科技大学 | A kind of new GaN HFETs |
| CN107993934A (en) * | 2017-12-08 | 2018-05-04 | 中国科学院微电子研究所 | Strengthen the method for gallium oxide semiconductor device ohmic contact |
| CN109390234A (en) * | 2018-10-22 | 2019-02-26 | 张家港意发功率半导体有限公司 | A kind of lithographic method of the enhancement type gallium nitride hetero-junctions HEMT with notched gates |
| CN109411350A (en) * | 2018-10-12 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A kind of preparation method of GaN base p-type grid structure |
| CN109860048A (en) * | 2019-02-26 | 2019-06-07 | 南京大学 | The enhanced MOSFET element of the AlGaN/GaN of slot grid structure and preparation method |
| CN110402480A (en) * | 2017-03-10 | 2019-11-01 | 国立大学法人名古屋大学 | Etaching device |
| CN112086362A (en) * | 2020-08-13 | 2020-12-15 | 深圳大学 | Gallium nitride enhanced HEMT device and preparation method thereof |
| CN112713188A (en) * | 2020-12-25 | 2021-04-27 | 西安电子科技大学芜湖研究院 | GaN-based enhanced MIS-HEMT device and preparation method thereof |
| CN112736137A (en) * | 2020-12-31 | 2021-04-30 | 广东省科学院半导体研究所 | Preparation method of p-type nitride gate of enhanced HEMT, enhanced nitride HEMT and preparation method thereof |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
| CN113555283A (en) * | 2020-04-24 | 2021-10-26 | 江苏鲁汶仪器有限公司 | Method for etching heterojunction of GaN-based high-electron-mobility transistor |
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| CN107230620A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The preparation method of gallium nitride transistor |
| CN107230726A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The manufacture method of enhancement type gallium nitride transistor |
| CN110402480A (en) * | 2017-03-10 | 2019-11-01 | 国立大学法人名古屋大学 | Etaching device |
| CN106981514A (en) * | 2017-05-25 | 2017-07-25 | 中国电子科技集团公司第十三研究所 | The enhanced GaN transistor device of notched gates based on nano-channel |
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| CN109411350B (en) * | 2018-10-12 | 2021-12-10 | 中国工程物理研究院电子工程研究所 | Preparation method of GaN-based p-type gate structure |
| CN109411350A (en) * | 2018-10-12 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A kind of preparation method of GaN base p-type grid structure |
| CN109390234A (en) * | 2018-10-22 | 2019-02-26 | 张家港意发功率半导体有限公司 | A kind of lithographic method of the enhancement type gallium nitride hetero-junctions HEMT with notched gates |
| CN109390234B (en) * | 2018-10-22 | 2022-03-22 | 张家港意发功率半导体有限公司 | Etching method of enhanced gallium nitride heterojunction HEMT with groove gate |
| CN109860048A (en) * | 2019-02-26 | 2019-06-07 | 南京大学 | The enhanced MOSFET element of the AlGaN/GaN of slot grid structure and preparation method |
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| CN113555283B (en) * | 2020-04-24 | 2024-04-05 | 江苏鲁汶仪器股份有限公司 | Method for etching heterojunction of GaN-based high-electron-mobility transistor |
| CN112086362A (en) * | 2020-08-13 | 2020-12-15 | 深圳大学 | Gallium nitride enhanced HEMT device and preparation method thereof |
| CN112713188A (en) * | 2020-12-25 | 2021-04-27 | 西安电子科技大学芜湖研究院 | GaN-based enhanced MIS-HEMT device and preparation method thereof |
| CN112713188B (en) * | 2020-12-25 | 2022-12-02 | 西安电子科技大学芜湖研究院 | GaN-based enhanced MIS-HEMT device and preparation method thereof |
| CN112736137A (en) * | 2020-12-31 | 2021-04-30 | 广东省科学院半导体研究所 | Preparation method of p-type nitride gate of enhanced HEMT, enhanced nitride HEMT and preparation method thereof |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
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