CN112713188A - GaN-based enhanced MIS-HEMT device and preparation method thereof - Google Patents

GaN-based enhanced MIS-HEMT device and preparation method thereof Download PDF

Info

Publication number
CN112713188A
CN112713188A CN202011568133.0A CN202011568133A CN112713188A CN 112713188 A CN112713188 A CN 112713188A CN 202011568133 A CN202011568133 A CN 202011568133A CN 112713188 A CN112713188 A CN 112713188A
Authority
CN
China
Prior art keywords
layer
gan
etching
growth
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011568133.0A
Other languages
Chinese (zh)
Other versions
CN112713188B (en
Inventor
季亚军
吴勇
王东
陈兴
汪琼
陆俊
黄永
孙凯
何滇
操焰
崔傲
袁珂
陈军飞
张进成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhu Research Institute of Xidian University
Original Assignee
Wuhu Research Institute of Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhu Research Institute of Xidian University filed Critical Wuhu Research Institute of Xidian University
Priority to CN202011568133.0A priority Critical patent/CN112713188B/en
Publication of CN112713188A publication Critical patent/CN112713188A/en
Application granted granted Critical
Publication of CN112713188B publication Critical patent/CN112713188B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention discloses a GAN-based enhanced MIS-HEMT device, which belongs to the technical field of microelectronics and comprises a substrate, a nucleating layer, a stress control layer, a GaN channel layer, an insertion layer and Al which are sequentially stacked from bottom to topxGa1‑XThe stress control layer is composed of AlN/AlGaN/SiNXThe GaN/AlGaN/GaN cyclic growth component comprises an AlN crystal nucleus layer, an AlGaN stress control layer, a reticular SiNx thin layer and a GaN filling layer, and the stress control layer is AlN/AlGaN/SiN in the aspect of epitaxial materialsXthe/GaN grows the composite bed cyclically, has reduced the dislocation density of the material, improve the quality of crystal lattice, thus promote the characteristic such as electron mobility, breakdown voltage of the device; in-device processIn addition, the TMAH solution effectively reduces the problem of uneven grid groove interface caused by uneven thermal oxidation.

Description

GaN-based enhanced MIS-HEMT device and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a GaN-based enhanced MIS-HEMT device and a preparation method thereof.
Background
High Electron Mobility Transistors (HEMTs) based on AGaN/GaN heterojunctions have been widely used in High temperature, High frequency, High voltage, High power, radiation resistant microwave and power electronic devices due to their excellent characteristics. However, as the performance requirements for various applications are continuously increased, there still exist some problems to be solved in the aspects of epitaxial materials and device processes.
In the aspect of epitaxial materials, because the gallium nitride material and the silicon substrate have larger lattice mismatch and thermal mismatch, the traditional nucleation layer and the AlGaN or GaN buffer layer play a role in buffering between the substrate and the GaN layer, but the crystal quality of the grown GaN layer is not good enough, so that the breakdown voltage of the device is reduced, and the electron mobility is reduced, so that the performance of the current gallium nitride HEMT device is far lower than the theoretical limit.
In the aspect of device technology, due to polarization effect, an HEMT based on an AlGaN/GaN heterojunction is generally of a depletion type (normally open), and when the HEMT is applied to a circuit-level system, a negative-polarity gate drive circuit needs to be designed to realize on-off control of the device, so that the complexity and cost of the circuit are greatly increased. Therefore, the development of various enhancement-type GaN devices is an especially keen issue for researchers in this field. The groove gate technology is a simple and efficient way for realizing an enhanced GaN device, but has obvious disadvantages, particularly, damage caused by gate trench etching and interface states affect device performance, which causes problems of increased gate leakage current, reduced channel electron mobility, increased on-resistance and the like. In view of the above problems, MIS (Metal-Insulator-Semiconductor) gate structures have been proposed, i.e., a layer of high-k gate dielectric is inserted between schottky gate Metal and barrier layer, thereby effectively reducing gate leakage current and increasing gate voltage swing; in the aspect of device preparation, the gate groove etching process is the most critical, and the current main etching methods are as follows: inductively Coupled Plasma (ICP) dry etching, digital etching (digital etch) and high temperature thermal oxidation wet etching. The ICP dry etching is the most commonly used gate trench etching technique, which has the advantages of fast etching rate, simple process, high anisotropy and the like, but has the disadvantages of non-linearity of etching rate, large etching damage and the like. The digital etching technology is an etching method with low damage, eliminates the damage caused by plasma bombardment in ICP dry etching, but has a slow etching rate. Compared with the former two methods, the high-temperature thermal oxidation wet etching method has no physical bombardment process, can well solve the problems of interface damage and interface state caused by dry etching, further reduces etching damage, and has self-stopping effect in a certain temperature range, but has the disadvantages that the whole grid groove etching process needs a plurality of oxidation/corrosion cycles, the process flow is complicated, and the time cost is high.
Disclosure of Invention
The invention aims to overcome the problems and provides an epitaxial preparation method of an enhanced HEMT device with a P-GaN cap layer, wherein in the aspect of epitaxial materials, an AlN/AlGaN/SiNx/GaN cyclic growth composite layer is used as a stress control layer, so that the crystal quality can be improved; in the aspect of device process, etching the concave gate groove by a two-step method until Al is etchedXGa1-XAnd finishing etching the N barrier layer. Firstly, removing most Al by ICP dry etchingXGa1-XAn N barrier layer, and the remaining Al is thermally oxidized at high temperatureXGa1-XBarrier layer of N, and oxidation at AlXGa1-XThe N interface realizes self-termination, and then the oxide layer is corroded by a wet method. The two-step etching method fully combines the high efficiency characteristic of dry etching and the low interface damage advantage of wet etching.
The device structure comprises a substrate, a nucleating layer, a stress control layer, a GaN channel layer, an insertion layer and Al which are sequentially stacked from bottom to topxGa1-XThe stress control layer is composed of AlN/AlGaN/SiNXThe GaN/GaN cyclic growth component specifically comprises an AlN crystal nucleus layer, an AlGaN stress control layer, a reticular structure SiNx thin layer and a GaN filling layer;
etching the SiNx passivation layer in the grid region by RIE, and completely etching away Al by ICP dry method, high-temperature thermal oxidation and wet method two-step methodXGa1-XThe N barrier layer forms a recessed gate trench, Al2O3The gate dielectric layer is distributed on the passivation layer, the side wall and the bottom of the concave gate groove, and the enhanced MIS-HEMT is realized;
a source electrode, a drain electrode at both sides of the T-shaped gate, and AlXGa1-XOhmic contact is formed between the N barrier layers;
etching the concave grid groove by a two-step method until Al is etchedXGa1-XThe specific method for completing the etching of the N barrier layer comprises the following steps: firstly, removing the silicon nitride by ICP dry etchingMost of AlXGa1-XN barrier layer, TMAH wet etching to remove residual Al after high-temperature thermal oxidationXGa1-XAn N barrier layer.
Preferably, the size of the substrate is 2-6 inch, and the material is silicon.
Preferably, the nucleation layer is grown by a PECVD method at the temperature of 450-550 ℃, the total thickness of the nucleation layer is 5-15 nm, and the nucleation layer is grown in N2/Ar/O2The growth rate is 1 to 10nm/S in the mixed atmosphere.
Preferably, in the stress control layer, the AlN sub-layer is 1-5 nm thick, the AlGaN sub-layer is 2-10 nm thick, and the SiN layer is of a net structureXThe thickness of the sub-layer is 0.5-2 nm, the thickness of the GaN sub-layer is 2-10 nm, and the number of cycles is 5-30.
Preferably, the growth temperature of the GaN channel layer is 1050-1150 ℃, and the thickness of the GaN channel layer is 1.0-2.5 microns.
Preferably, the insertion layer is an AlN insertion layer, the thickness is 0.5-1.5 nm, the growth pressure is 50-100 mbar, and the growth temperature is 1000-1200 ℃;
preferably, the Al isXGa1-XThe growth thickness of the N barrier layer is 10-25 nm, the growth pressure is 50-100 mbar, the growth temperature is 900-1200 ℃, wherein the growth temperature is 0 DEG C<x<1；
Preferably, the cap layer is a GaN cap layer, the growth thickness of the cap layer is 1-3 nm, the growth pressure is 50-100 mbar, and the growth temperature is 900-1200 ℃;
preferably, the ohmic metal deposition of the source electrode and the drain electrode adopts an electron beam evaporation mode to deposit four layers of Ti/Al/Ni/Au ohmic metal, and the etching depth of the surface barrier layer is 5-15 nm;
preferably, the SiNXThe passivation layer grows by PECVD, the growth temperature is 100-350 ℃, and the thickness is 50-300 nm;
preferably, the ICP dry etching uses Cl as the gas2And BCl3，Cl2The flow rate is 10-100 sccm, BCl3The flow is 10-100 sccm, the pressure of an etching cavity is 10-100 mTorr, the RF power is 10-100W, and the ICP power is 200-2000W;
in the TMAH wet etching after high-temperature thermal oxidation, the high-temperature thermal oxidation is carried out at 550-650 ℃ in the oxygen atmosphere of an annealing furnace, the TMAH is aqueous solution with the volume ratio of 5-35%, the corrosion temperature is 40-120 ℃, and the cycle treatment times of the oxidation/corrosion process are 1-10 times.
Preferably, the gate dielectric layer distributed on the passivation layer, the side wall and the bottom of the groove is made of Al2O3Performing gate dielectric Layer Al by ALD (atomic Layer Deposition)2O3Depositing to a thickness of 2-50 nm.
Preferably, the T-shaped gate metal deposition adopts an electron beam evaporation mode to deposit Ni/Au two-layer metal. The lead electrode was metallic Ni/Au with a thickness of 50nm/450 nm.
Compared with the prior art, the invention has the following advantages: a new epitaxial structure and a growing method are provided, and the process optimization of the enhancement type HEMT device is realized. The main technology comprises the following steps:
1. in terms of epitaxial materials, the existing AlN/AlGaN/GaN and AlN/SiNXOn the basis that the/GaN circulation growth composite layer is used as a stress control layer, the invention provides AlN/AlGaN/SiNXthe/GaN circulation growth composite layer is used as a stress control layer. AlGaN stress control layer and net-shaped SiN are simultaneously introduced between AlN crystal nucleus layer and GaN filling layerXDue to the introduction of the thin layer and AlGaN, the generated compressive stress is mutually offset with the tensile stress in the epitaxial growth process and the cooling process, so that the stress regulation and control effect is achieved; network structure SiNXThe thin layer provides uniform, exposed nuclei for the fill-in layer and may block the extension of some defects. Thus, AlGaN stress control layer and reticular SiN are fully combinedXThe function of the thin layer.
2. In the aspect of device process, etching the concave gate groove by a two-step method until Al is etchedXGa1-XAnd finishing etching the N barrier layer. Firstly, removing most Al by ICP dry etchingXGa1-XAn N barrier layer, and the remaining Al is thermally oxidized at high temperatureXGa1-XThe N barrier layer is formed by oxidation of Al, since GaN is not oxidized at a temperature lower than 700 deg.CXGa1-XThe N interface realizes self termination and then is corroded by a wet methodAnd etching the oxide layer. The two-step etching method fully combines the high efficiency characteristic of dry etching and the low interface damage advantage of wet etching.
3. According to the invention, TMAH solution is used for replacing the traditional KOH solution for wet etching after high-temperature thermal oxidation, and the problem of uneven grid groove interface caused by nonuniform thermal oxidation is effectively reduced by utilizing the specific lateral etching mechanism.
Drawings
Fig. 1 is a schematic structural diagram of a GaN-based enhancement MIS-HEMT device according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a stress control layer according to an embodiment of the invention.
Fig. 3a to 3e are schematic diagrams of a two-step gate trench etching process according to an embodiment of the present invention.
Fig. 3a shows SiNx passivation layer (mask layer) growth.
FIG. 3b shows the SiNx passivation layer etched by RIE under the protection of AZ5214 photoresist.
FIG. 3c shows ICP dry etching cap layer and most barrier layer.
FIG. 3d shows a high temperature oxidation of the un-etched barrier layer and the intervening layer.
FIG. 3e shows TMAH solution wet etching after high temperature oxidation of the remaining barrier layer and the insertion layer.
Fig. 4 is a comparison of leakage current (I) -drain-source voltage (V) curves after dry trench gate etching in accordance with the two-step method provided by the embodiments of the present invention.
Fig. 5 is a schematic structural diagram of a GaN-based enhancement MIS-HEMT device obtained by another preparation method according to an embodiment of the present invention.
Wherein: 11-substrate, 12-nucleation layer, 13-stress control layer, 131-AlN crystal nucleus layer, 132-AlGaN stress control layer, 133-net structure SiNXThin layer, 134-GaN fill-level layer, 14-GaN channel layer, 15-insertion layer, 16-AlXGa1-XN barrier layer, 17-cap layer, 2-SiNx passivation layer, 3-Al2O3The grid dielectric layer, the 4-source electrode, the 5-drain electrode and the 6-T-shaped grid electrode.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
The heterojunction material structure for preparing the GaN-based MIS-HEMT device comprises a substrate 11, a nucleating layer 12, a stress control layer 13, a GaN channel layer 14, an AlN insert layer 15 and Al from bottom to topXGa1-XAn N-barrier layer 16 and a GaN cap layer 17. Etching the SiNx passivation layer 2 in the grid region by RIE, and completely etching away Al by ICP dry method, high-temperature thermal oxidation and wet method two-step methodXGa1-XThe N barrier layer 16 forms a concave gate groove, and the Al2O3 gate dielectric layer 3 is distributed on the passivation layer 2, the side wall and the bottom of the concave gate groove, so that the enhancement type MIS-HEMT is realized. The source electrode 4 and the drain electrode 5 are positioned at two sides of the T-shaped grid electrode 6, and ohmic contact is formed between the metal of the source electrode 4 and the drain electrode 5 and the AlGaN barrier layer 16. Device fabrication may be performed in an ohmic contact followed by passivation (see fig. 1) or in a passivation followed by ohmic contact (see fig. 5).
The device structure is prepared by the following steps:
example 1:
the device fabrication was performed in this case in an ohmic contact followed by passivation (see figure 1). The specific steps and process conditions are as follows:
s1, firstly, putting a Si substrate 11 into a reaction chamber, heating to 1050-1150 ℃, and reacting at H2Removing the oxide film on the surface under the condition;
s2, growing an AlN nucleating layer 12 on the substrate 11 by adopting a PECVD method at the temperature of 350-550 ℃, the total thickness of the AlN nucleating layer is 5-15 nm, and the thickness of the AlN nucleating layer is N2/Ar/O2The growth rate is 1-10 nm/S under the mixed atmosphere;
s3, growing a stress control layer 13 on the nucleation layer 12 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the stress control layer 13 is AlN/AlGaN/SiN as shown in figure 2XThe composite layer grows in a GaN circulation mode, hydrogen and nitrogen are used as carrier gases, the growth temperature is 1050-1150 ℃, the pressure of a reaction chamber is 50-200 torr, the thickness of an AlN sub-layer is 1-5 nm, the thickness of an AlGaN sub-layer is 2-10 nm, and SiN in a net structureXThe thickness of the sub-layer is 0.5-2 nm, the thickness of the GaN sub-layer is 2-10 nm, and the number of cycles is 5-30;
s4, growing a GaN channel layer 14 on the stress regulation layer 13 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth temperature is 1050-1150 ℃;
s5, growing an AlN insert layer 15 on the GaN channel layer 14 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 1000-1200 ℃;
s6, growing Al on the AlN insert layer 15 by Metal Organic Chemical Vapor Deposition (MOCVD)XGa1-XThe N barrier layer 16 has the growth pressure of 50-100 mbar, the growth temperature of 900-1200 ℃ and the growth thickness of 25 nm;
s7, adding AlXGa1-XGrowing a GaN cap layer 17 on the N barrier layer 16 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 900-1200 ℃;
and S8, etching the source and drain ohmic contact grooves. The barrier layer 16 is etched by using the photoresist AZ5214 as a mask and using an ICP (inductively Coupled Plasma) etching technique. The etching depth of the surface barrier layer 16 is 5-15 nm, and source and drain ohmic contact windowing is realized;
s9, source drain ohmic contact. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ti/Al/Ni/Au with a thickness of 20nm/140nm/50nm/150 nm. The annealing conditions are 100-800 ℃, 20-60 s and nitrogen atmosphere
And S10, isolating an active area. Isolating by adopting an N ion implantation technology, wherein the ion implantation energy is 100-400 KeV, and the implantation depth exceeds the channel layer by about 0.5-1.0 mu m;
s11, growing SiN by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) methodXPassivation layer 2, SiN as shown in FIG. 3aXThe passivation layer 2 has the effects of inhibiting current collapse, protecting the surface of a device, serving as a process barrier layer and the like, the growth temperature is 100-350 ℃, and the thickness is 50-500 nm;
s12, windowing the groove grid. With the photoresist AZ5214 as a mask (1-2 μm), Reactive Ion Etching (RIE) is performed on SiN in the gate regionXEtching the passivation layer 2 to realize the gate windowing, as shown in fig. 3 b;
and S13, etching the gate groove. And etching the groove on the basis of windowing the groove gate. The first step is ICP dry etching, as shown in fig. 3c, etching AlXGa1-XThe N-barrier layer 16 is 23nm thick. Using photoresist AZ5214 as mask, SiNXThe passivation layer 2 is used as a barrier layer, the Cl2 flow is 10-100 sccm, and BCl3The flow is 10-100 sccm, the pressure of an etching cavity is 10-100 mTorr, the RF power is 10-100W, and the ICP power is 200-2000W; the second step is TMAH wet etching (see FIG. 3e) of the remaining Al after high temperature thermal oxidation (see FIG. 3d)XGa1-XAn N barrier layer 16 and an AlN insertion layer 15. Performing high-temperature thermal oxidation at 550-650 ℃ in an oxygen atmosphere of an annealing furnace, wherein a 5-35% volume ratio aqueous solution is adopted as a wet etching solution TMAH, the corrosion temperature is 40-120 ℃, and the cycle treatment times of the oxidation/corrosion process are 1-10 times;
s14, depositing a gate dielectric layer 3. Removing the photoresist, and performing ALD (atomic Layer Deposition) to obtain gate dielectric Layer Al2O33, depositing to a thickness of 2-50 nm;
s15, depositing grid metal. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ni/Au with a thickness of 50nm/300 nm.
And S16, preparing a lead electrode. And preparing lead electrode metal after the window of the lead electrode, wherein the material is Ni/Au, and the thickness is 50nm/450 nm.
Example 2:
the device fabrication was performed in this case in an ohmic contact followed by passivation (see figure 1). The specific steps and process conditions are as follows:
s1, firstly, putting a Si substrate 11 into a reaction chamber, heating to 1050-1150 ℃, and reacting at H2Removing the oxide film on the surface under the condition;
s2, growing an AlN nucleating layer 12 on the substrate 11 by adopting a PECVD method at the temperature of 350-550 ℃, the total thickness of the AlN nucleating layer is 5-15 nm, and the thickness of the AlN nucleating layer is N2/Ar/O2The growth rate is 1-10 nm/S under the mixed atmosphere;
s3, growing a stress control layer 13 on the nucleation layer 12 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the stress control layer 13 is AlN/AlGaN/SiN as shown in figure 2X/GGrowing a composite layer in aN aN circulation mode, taking hydrogen and nitrogen as carrier gases, controlling the growth temperature to be 1050-1150 ℃, the pressure of a reaction chamber to be 50-200 torr, the thickness of aN AlN sub-layer to be 1-5 nm, the thickness of aN AlGaN sub-layer to be 2-10 nm, and the SiN in a net structureXThe thickness of the sub-layer is 0.5-2 nm, the thickness of the GaN sub-layer is 2-10 nm, and the number of cycles is 5-30;
s4, growing a GaN channel layer 14 on the stress regulation layer 13 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth temperature is 1050-1150 ℃;
s5, growing an AlN insert layer 15 on the GaN channel layer 14 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 1000-1200 ℃;
s6, growing Al on the AlN insert layer 15 by Metal Organic Chemical Vapor Deposition (MOCVD)XGa1-XThe N barrier layer 16 has the growth pressure of 50-100 mbar, the growth temperature of 900-1200 ℃ and the growth thickness of 25 nm;
s7, adding AlXGa1-XGrowing a GaN cap layer 17 on the N barrier layer 16 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 900-1200 ℃;
and S8, etching the source and drain ohmic contact grooves. The barrier layer 16 is etched by using the photoresist AZ5214 as a mask and using an ICP (inductively Coupled Plasma) etching technique. The etching depth of the surface barrier layer 16 is 5-15 nm, and source and drain ohmic contact windowing is realized;
s9, source drain ohmic contact. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ti/Al/Ni/Au with a thickness of 20nm/140nm/50nm/150 nm. The annealing condition is 100-800 ℃, 20-60 s and nitrogen atmosphere;
and S10, isolating an active area. Isolating by adopting an N ion implantation technology, wherein the ion implantation energy is 100-400 KeV, and the implantation depth exceeds the channel layer by about 0.5-1.0 mu m;
s11, growing SiN by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) methodXPassivation layer 2, SiN as shown in FIG. 3aXThe passivation layer 2 has the functions of inhibiting current collapse, protecting the surface of a device, serving as a process barrier layer and the like, and has the growth temperature100-350 ℃ and 50-500 nm in thickness;
s12, windowing the groove grid. With the photoresist AZ5214 as a mask (1-2 μm), Reactive Ion Etching (RIE) is performed on SiN in the gate regionXEtching the passivation layer 2 to realize the gate windowing, as shown in fig. 3 b;
and S13, etching the gate groove. And etching the groove on the basis of windowing the groove gate. The first step is ICP dry etching, as shown in fig. 3c, etching AlXGa1-XThe N-barrier layer 16 is 21nm thick. Using photoresist AZ5214 as mask, SiNXThe passivation layer 2 is used as a barrier layer, the Cl2 flow is 10-100 sccm, and BCl3The flow is 10-100 sccm, the pressure of an etching cavity is 10-100 mTorr, the RF power is 10-100W, and the ICP power is 200-2000W; the second step is TMAH wet etching (see FIG. 3e) of the remaining Al after high temperature thermal oxidation (see FIG. 3d)XGa1-XAn N barrier layer 16 and an AlN insertion layer 15. Performing high-temperature thermal oxidation at 550-650 ℃ in an oxygen atmosphere of an annealing furnace, wherein a 5-35% volume ratio aqueous solution is adopted as a wet etching solution TMAH, the corrosion temperature is 40-120 ℃, and the cycle treatment times of the oxidation/corrosion process are 1-10 times;
s14, depositing a gate dielectric layer 3. Removing the photoresist, and performing ALD (atomic Layer Deposition) to obtain gate dielectric Layer Al2O33, depositing to a thickness of 2-50 nm;
s15, depositing grid metal. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ni/Au with a thickness of 50nm/300 nm.
And S16, preparing a lead electrode. And preparing lead electrode metal after the window of the lead electrode, wherein the material is Ni/Au, and the thickness is 50nm/450 nm.
Example 3:
the device fabrication was performed in this case in a passivation followed by ohmic contact (see figure 5). The specific steps and process conditions are as follows:
s1, firstly, putting a Si substrate 11 into a reaction chamber, heating to 1050-1150 ℃, and reacting at H2Removing the oxide film on the surface under the condition;
s2, growing the AlN nucleating layer 12 on the substrate 11 by adopting a PECVD method at the temperature of 350-550 DEG CThe total thickness is 5 to 15nm, in N2/Ar/O2The growth rate is 1-10 nm/S under the mixed atmosphere;
s3, growing a stress control layer 13 on the nucleation layer 12 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the stress control layer 13 is AlN/AlGaN/SiN as shown in figure 2XThe composite layer grows in a GaN circulation mode, hydrogen and nitrogen are used as carrier gases, the growth temperature is 1050-1150 ℃, the pressure of a reaction chamber is 50-200 torr, the thickness of an AlN sub-layer is 1-5 nm, the thickness of an AlGaN sub-layer is 2-10 nm, and SiN in a net structureXThe thickness of the sub-layer is 0.5-2 nm, the thickness of the GaN sub-layer is 2-10 nm, and the number of cycles is 5-30;
s4, growing a GaN channel layer 14 on the stress regulation layer 13 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth temperature is 1050-1150 ℃;
s5, growing an AlN insert layer 15 on the GaN channel layer 14 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 1000-1200 ℃;
s6, growing Al on the AlN insert layer 15 by Metal Organic Chemical Vapor Deposition (MOCVD)XGa1-XThe N barrier layer 16 has the growth pressure of 50-100 mbar, the growth temperature of 900-1200 ℃ and the growth thickness of 25 nm;
s7, adding AlXGa1-XGrowing a GaN cap layer 17 on the N barrier layer 16 by Metal Organic Chemical Vapor Deposition (MOCVD), wherein the growth pressure is 50-100 mbar, and the growth temperature is 900-1200 ℃;
s8, growing SiN by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) methodXPassivation layer 2, SiNXThe passivation layer 2 has the effects of inhibiting current collapse, protecting the surface of a device, serving as a process barrier layer and the like, the growth temperature is 100-350 ℃, and the thickness is 50-500 nm;
and S9, isolating the active area. Isolating by adopting an N ion implantation technology, wherein the ion implantation energy is 100-400 KeV, and the implantation depth exceeds the channel layer by about 0.5-1.0 mu m;
s10, windowing the groove grid. With the photoresist AZ5214 as a mask (1-2 μm), Reactive Ion Etching (RIE) is performed on SiN in the gate regionXPassivation layer2, etching to realize grid windowing;
s11, etching a grid groove. And etching the groove on the basis of windowing the groove gate. The first step is ICP dry etching, as shown in fig. 3c, etching AlXGa1-XThe N-barrier layer 16 is 23nm thick. Using photoresist AZ5214 as mask, SiNXThe passivation layer 2 is used as a barrier layer, the flow rate of Cl2 is 10-100 sccm, the flow rate of BCl3 is 10-100 sccm, the pressure of an etching cavity is 10-100 mTorr, the RF power is 10-100W, and the ICP power is 200-2000W; the second step is TMAH wet etching of the residual Al after high-temperature thermal oxidationXGa1-XAn N barrier layer 16 and an AlN insertion layer 15. Performing high-temperature thermal oxidation at 550-650 ℃ in an oxygen atmosphere of an annealing furnace, wherein a 5-35% volume ratio aqueous solution is adopted as a wet etching solution TMAH, the corrosion temperature is 40-120 ℃, and the cycle treatment times of the oxidation/corrosion process are 1-10 times;
s12, depositing a gate dielectric layer 3. Removing the photoresist, and performing ALD (atomic Layer Deposition) to obtain gate dielectric Layer Al2O33, depositing to a thickness of 2-50 nm;
s13, depositing grid metal. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ni/Au with a thickness of 50nm/300 nm.
S14, etching the source and drain ohmic contact grooves. Etching Al by using photoresist AZ5214 as mask and chlorine-containing plasma2O3Gate dielectric layer 3, plasma etch SiN containing fluorineXAnd etching the barrier layer 16 of the passivation layer 2 by using an ICP (inductively Coupled Plasma) etching technique. The etching depth of the surface barrier layer 16 is 5-15 nm, and source and drain ohmic contact windowing is realized;
s15, source-drain ohmic contact. Adopting an electron beam evaporation technology, and preparing conditions are as follows: metal Ti/Al/Ni/Au with a thickness of 20nm/140nm/50nm/150 nm. The annealing conditions are 100-800 ℃, 20-60 s and nitrogen atmosphere.
Fig. 4 shows the comparison of the leakage performance of the GaN-based MIS-HEMT device of the present invention fabricated under the conditions of example 1 with the leakage performance of the device fabricated under the conventional ICP dry etching gate trench technology with other conditions being unchanged:
the leakage current of the grid groove etched by adopting the two-step method is far lower than that of the grid groove etched by the ICP dry method, because a large amount of trap charges and dangling bonds exist after the ICP dry method is etched to form a surface leakage channel, and the grid groove etched by the two-step method can well solve the problems of interface damage and interface state caused by the dry method while the etching efficiency is ensured, so that the leakage performance is improved.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.

Claims (10)

1. The GaN-based enhanced MIS-HEMT device is characterized by comprising a substrate (11), a nucleating layer (12), a stress control layer (13), a GaN channel layer (14), an insertion layer (15) and Al which are sequentially stacked from bottom to topxGa1-XAn N barrier layer (16) and a cap layer (17), wherein the stress control layer (13) is made of AlN/AlGaN/SiNXThe GaN/GaN cyclic growth composition specifically comprises an AlN crystal nucleus layer (131), an AlGaN stress control layer (132), a network structure SiNx thin layer (133) and a GaN filling layer (134);
etching the SiNx passivation layer (2) in the grid region by RIE, and completely etching away Al by ICP dry method, high-temperature thermal oxidation and wet method two-step methodXGa1-XThe N barrier layer (16) forms a concave gate groove, Al2O3The gate dielectric layer (3) is distributed on the passivation layer, the side wall and the bottom of the concave gate groove, and the enhancement type MIS-HEMT is realized;
a source electrode (4), a drain electrode (5) are positioned at two sides of the T-shaped grid electrode (6), the source electrode (4), the drain electrode (5) and AlXGa1-XOhmic contact is formed between the N barrier layers (16);
etching the concave grid groove by a two-step method until Al is etchedXGa1-XThe specific method for etching the N barrier layer (16) comprises the following steps: firstly, removing most Al by ICP dry etchingXGa1-XN barrier layer (16), and removing the rest Al by TMAH wet etching after high-temperature thermal oxidationXGa1-XAn N barrier layer (16).
2. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the substrate (11) is 2-6 inch in size and made of silicon.
3. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the nucleating layer (12) is grown by a PECVD method at the temperature of 450-550 ℃, the total thickness of the nucleating layer is 5-15 nm, and the growing temperature is N2/Ar/O2The growth rate is 1 to 10nm/S in the mixed atmosphere.
4. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: in the stress control layer (13), the AlN sub-layer (131) is 1-5 nm thick, the AlGaN sub-layer (132) is 2-10 nm thick, and the SiN sub-layer is of a net structureXThe thickness of the sub-layer (133) is 0.5-2 nm, the thickness of the GaN sub-layer (134) is 2-10 nm, and the number of cycles is 5-30.
5. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the growth temperature of the GaN channel layer (14) is 1050-1150 ℃, and the thickness of the GaN channel layer is 1.0-2.5 microns.
6. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the insertion layer (15) is an AlN insertion layer, the thickness of the AlN insertion layer is 0.5-1.5 nm, the growth pressure is 50-100 mbar, and the growth temperature is 1000-1200 ℃.
7. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the Al isXGa1-XThe growth thickness of the N barrier layer (16) is 10-25 nm, the growth pressure is 50-100 mbar, the growth temperature is 900-1200 ℃, wherein the growth temperature is 0 DEG C<x<1。
8. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the cap layer (17) is a GaN cap layer, the growth thickness of the cap layer is 1-3 nm, the growth pressure is 50-100 mbar, and the growth temperature is 900-1200 ℃.
9. The GaN-based enhanced MIS-HEMT device of claim 1, wherein: the ohmic metal deposition of the source electrode (4) and the drain electrode (5) adopts an electron beam evaporation mode to deposit four layers of Ti/Al/Ni/Au ohmic metal, and the etching depth of the surface barrier layer is 5-15 nm;
the SiNXThe passivation layer (2) grows by PECVD, the growth temperature is 100-350 ℃, and the thickness is 50-300 nm;
10. the GaN-based enhanced MIS-HEMT device of claim 1, wherein: the ICP dry etching uses Cl as gas2And BCl3，Cl2The flow rate is 10-100 sccm, BCl3The flow is 10-100 sccm, the pressure of an etching cavity is 10-100 mTorr, the RF power is 10-100W, and the ICP power is 200-2000W;
in the TMAH wet etching after high-temperature thermal oxidation, the high-temperature thermal oxidation is carried out at 550-650 ℃ in the oxygen atmosphere of an annealing furnace, the TMAH is aqueous solution with the volume ratio of 5-35%, the corrosion temperature is 40-120 ℃, and the cycle treatment times of the oxidation/corrosion process are 1-10 times.
CN202011568133.0A 2020-12-25 2020-12-25 GaN-based enhanced MIS-HEMT device and preparation method thereof Active CN112713188B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011568133.0A CN112713188B (en) 2020-12-25 2020-12-25 GaN-based enhanced MIS-HEMT device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011568133.0A CN112713188B (en) 2020-12-25 2020-12-25 GaN-based enhanced MIS-HEMT device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN112713188A true CN112713188A (en) 2021-04-27
CN112713188B CN112713188B (en) 2022-12-02

Family

ID=75545470

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011568133.0A Active CN112713188B (en) 2020-12-25 2020-12-25 GaN-based enhanced MIS-HEMT device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112713188B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116544275A (en) * 2023-04-18 2023-08-04 山东大学 GaN HEMTs and method for reducing ohmic contact resistance of device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104201104A (en) * 2014-09-09 2014-12-10 电子科技大学 Manufacturing method for gallium nitride-based enhanced device
CN108598234A (en) * 2018-04-26 2018-09-28 吉林大学 In a kind of reduction SiC substrate in GaN film tensile stress epitaxial structure and preparation method thereof
CN108666359A (en) * 2017-03-29 2018-10-16 北京大学 A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104201104A (en) * 2014-09-09 2014-12-10 电子科技大学 Manufacturing method for gallium nitride-based enhanced device
CN108666359A (en) * 2017-03-29 2018-10-16 北京大学 A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer
CN108598234A (en) * 2018-04-26 2018-09-28 吉林大学 In a kind of reduction SiC substrate in GaN film tensile stress epitaxial structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116544275A (en) * 2023-04-18 2023-08-04 山东大学 GaN HEMTs and method for reducing ohmic contact resistance of device

Also Published As

Publication number Publication date
CN112713188B (en) 2022-12-02

Similar Documents

Publication Publication Date Title
JP7178121B2 (en) Semiconductor device manufacturing method and use thereof
US20210273087A1 (en) Normally-off hemt transistor with selective generation of 2deg channel, and manufacturing method thereof
JP2021510461A (en) Group III nitride enhancement type HEMT based on the composite barrier layer structure and its manufacturing method
CN112542508B (en) ScAlN/GaN high electron mobility transistor and manufacturing method thereof
CN113054002B (en) Enhanced high-mobility gallium nitride semiconductor device and preparation method thereof
CN112736131A (en) YAlN/GaN high electron mobility transistor and manufacturing method thereof
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN210429824U (en) Enhanced AlN/AlGaN/GaN HEMT device
CN112713188B (en) GaN-based enhanced MIS-HEMT device and preparation method thereof
CN109300974B (en) Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof
CN111509042A (en) MIS structure GaN high electron mobility transistor and preparation method thereof
CN114121655B (en) Self-termination etching method and device based on enhanced device
CN109599437A (en) High electron mobility transistor and preparation method thereof based on InGaN double channel heterojunction structure
CN114725214A (en) Multilayer passivation groove gate MIS-HEMT device and preparation method thereof
CN114823303A (en) Semiconductor device and method for manufacturing the same
CN111613669B (en) AlGaN high electron mobility transistor with high breakdown voltage and preparation method thereof
CN110444598B (en) High electron mobility transistor and preparation method thereof
CN113314590B (en) Nitride high electron mobility transistor and manufacturing method thereof
CN113540231B (en) P-GaN high electron mobility transistor based on in-situ growth MIS structure and preparation method
CN212380426U (en) Two-dimensional AlN/GaN HEMT radio frequency device
CN113517335B (en) Adjustable composite groove gate E-HEMT device and preparation method
CN116387246A (en) p-GaN enhanced MIS-HEMT device and preparation method thereof
WO2022099636A1 (en) Method for manufacturing semiconductor structure
WO2021142823A1 (en) Gan-based normally-off high-electron-mobility transistor and preparation method therefor
US20210143264A1 (en) Method for preparing a p-type semiconductor layer, enhanced device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 241000 building 7, science and Technology Industrial Park, high tech Industrial Development Zone, Yijiang District, Wuhu City, Anhui Province

Applicant after: Wuhu Research Institute of Xidian University

Address before: No. 8, Wen Jin Xi Road, Yijiang District, Wuhu, Anhui Province

Applicant before: Wuhu Research Institute of Xidian University

GR01 Patent grant
GR01 Patent grant