CN106981514B - Groove gate enhanced GaN transistor device based on nano channel - Google Patents

Groove gate enhanced GaN transistor device based on nano channel Download PDF

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CN106981514B
CN106981514B CN201710380274.1A CN201710380274A CN106981514B CN 106981514 B CN106981514 B CN 106981514B CN 201710380274 A CN201710380274 A CN 201710380274A CN 106981514 B CN106981514 B CN 106981514B
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nano
gate
channel
gan
transistor device
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CN106981514A (en
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周幸叶
冯志红
吕元杰
谭鑫
王元刚
宋旭波
徐鹏
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CETC 13 Research Institute
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
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Abstract

The invention discloses a groove gate enhanced GaN transistor device based on a nano channel, which relates to the technical field of microelectronic devices and comprises a substrate layer, a GaN buffer layer, an AlGaN barrier layer, a gate dielectric layer, a passivation layer, a source electrode, a drain electrode and a gate electrode from bottom to top; the heterojunction below the gate electrode of the AlGaN/GaN transistor device with high electron mobility is etched to form a nano channel, two-dimensional electron gas does not exist in the regions on two sides of the nano channel, the gate electrode is wrapped above and on the two side walls of the nano channel, and electrons in the channel are modulated from three directions by the gate electrode, so that the gate control capability is high, and the short channel effect can be well restrained. When the width of the nano channel is small, the two-dimensional electron gas in the channel is exhausted, and the device realizes enhancement. By adopting the groove gate structure, the nano channel and the groove gate act together, so that the device can have larger nano channel width and reduce on-resistance while realizing enhancement.

Description

Groove gate enhanced GaN transistor device based on nano channel
Technical Field
The invention relates to the technical field of microelectronic devices, in particular to a groove gate enhanced GaN transistor device based on a nano channel.
Background
The GaN has the advantages of high critical breakdown electric field, high electron saturation velocity, good heat stability, strong radiation resistance and the like, and particularly, the AlGaN/GaN heterostructure material has extremely high two-dimensional electron gas concentration and electron mobility due to spontaneous polarization and piezoelectric polarization effects, and is considered as an excellent material for preparing high-temperature-resistant, radiation-resistant, high-frequency high-power microwave power devices, high-speed and high-voltage power switching devices and radiation-resistant high-speed digital circuits.
AlGaN/GaN high electron mobility transistors are typically depletion mode devices due to polarization effects, making enhancement mode devices difficult and very slow to develop. The application of depletion mode devices has limitations. First, in rf power applications, depletion mode devices must be biased with a negative voltage to gate, requiring the design of a separate power supply system. Second, in power switching applications, depletion mode devices also require that the negatively biased system operate prior to the power supply being energized in order to ensure overall safety of the system. In addition, in high-speed digital circuit applications, the enhancement device is an integral component of an inverter, which is the core unit of a complex digital system. Therefore, it is very important to develop an enhancement type GaN transistor with high reliability.
At present, one research thinking of an enhanced GaN device internationally is to dig a groove below a gate electrode to make channel two-dimensional electron gas below the gate depleted, and the concentration of the rest two-dimensional electron gas of the channel is unchanged, so that the enhanced GaN device is realized. However, as device dimensions continue to shrink, gate lengths become shorter and shorter, and short channel effects of conventional planar-structured high electron mobility transistors become more pronounced. In 2013, ki-Sik Im et al prepared single nano-channel enhancement mode AlGaN/ganisfet with threshold voltage of 2.1V, and the device structure adopted a common gate structure, in order to realize enhancement mode device, the nano-channel width was only 50nm, and the two ends of the nano-channel extended to the source-drain electrode region, so the on-resistance of the device was larger.
Disclosure of Invention
The invention aims to solve the technical problems of the prior art and provides a groove gate enhanced GaN transistor device based on a nano channel, wherein the transistor has the characteristics of strong gate control capability, capability of inhibiting short channel effect and small on-resistance.
In order to solve the technical problems, the invention adopts the following technical scheme: the groove gate enhanced GaN transistor device based on the nano channel comprises a substrate layer, a GaN buffer layer, an AlGaN barrier layer, a gate dielectric layer, a passivation layer, a source electrode, a drain electrode and a gate electrode from bottom to top; the method is characterized in that: the AlGaN barrier layer and the GaN buffer layer form an AlGaN/GaN heterojunction, a groove is formed above the AlGaN barrier layer, and a gate electrode is positioned in the groove and wrapped above and on two sides of the AlGaN/GaN heterojunction to form a three-dimensional ring gate structure; the AlGaN/GaN heterojunction under the gate electrode is provided with a nano pattern to form a nano channel; the two ends of the nano channel are provided with channel expansion areas; the gate dielectric layer is positioned below the gate electrode, between the source electrode and the drain electrode, covers the top of the AlGaN/GaN heterojunction and wraps the two side walls of the nano channel.
Preferably, the substrate layer is sapphire, siC or GaN.
Preferably, the thickness of the GaN buffer layer is 0.5-2.5um.
Preferably, the AlGaN barrier layer has a thickness of 10-20nm, and the Al content is 15% -30%.
Preferably, the number n of the nano channels is not less than 1, and the length L ch Is 0 to<L ch <Source and drain electrode spacing, width W ch 10-200nm.
Preferably, the distance D between the bottom of the groove on the AlGaN barrier layer and the AlGaN/GaN heterojunction ch1 A distance D between the bottom of the nano channel and the AlGaN/GaN heterojunction is 0-15nm ch2 0-150nm.
Preferably, the gate dielectric layer is SiN, al 2 O 3 、SiO 2 Or a stacked structure of multiple dielectric layers with a thickness of 1-15nm.
Preferably, the passivation layer is SiN, al 2 O 3 、SiO 2 Or a stacked structure of a plurality of passivation layers, and the thickness is 50-150nm.
Preferably, the gate electrode is a straight gate or a T-shaped gate, and the gate length L g =L ch Or L g >L ch Or L g <L ch 。
Preferably, the source electrode and the drain electrode are in ohmic contact and are positioned on the channel expansion regions at two ends of the nano-channel.
The beneficial effects of adopting above-mentioned technical scheme to produce lie in: the heterojunction below the gate electrode of the AlGaN/GaN transistor device with high electron mobility is etched to form a nano channel, two-dimensional electron gas does not exist in the regions on two sides of the nano channel, the gate electrode is wrapped above and on the two side walls of the nano channel, and electrons in the channel are modulated from three directions by the gate electrode, so that the gate control capability is high, and the short channel effect can be well restrained. When the width of the nano channel is small, the two-dimensional electron gas in the channel is exhausted, and the device realizes enhancement. By adopting the groove gate structure, the nano channel and the groove gate act together, so that the device can have larger nano channel width and reduce on-resistance while realizing enhancement. The two ends of the nano channel are provided with extension regions, so that the on-resistance can be further reduced, and the frequency of the device can be improved.
Drawings
FIG. 1 is a top view of an overall structure of an embodiment of the present invention.
Fig. 2 is a cross-sectional view of the plane of fig. 1 A-A.
Fig. 3 is a cross-sectional view of the plane of fig. 1B-B.
Fig. 4 is a cross-sectional view of the plane of fig. 1C-C.
Fig. 5 is a top view of a unitary structure of a second embodiment of the present invention.
Fig. 6 is a top view of a three-piece structure of an embodiment of the present invention.
Fig. 7 is a cross-sectional view of a fourth overall structure of an embodiment of the present invention.
In the figure: 1. a source electrode; 2. a drain electrode; 3. a gate electrode; 4. a channel extension region; 5. a nanochannel; 6. a substrate layer; 7. a GaN buffer layer; 8. an AlGaN barrier layer; 9. a gate dielectric layer; 10. and a passivation layer.
Detailed Description
The invention will be described in further detail with reference to the drawings and the detailed description.
As shown in fig. 1, 2, 3 and 4, the device of the present invention includes a substrate layer 6, a GaN buffer layer 7, an AlGaN barrier layer 8, a gate dielectric layer 9, a passivation layer 10, a source electrode 1, a drain electrode 2 and a gate electrode 3. Wherein the lowest layer is a substrate layer 6 adopting sapphire, siC or GaN; above the substrate layer 6 is a GaN buffer layer 7; above the buffer layer is an AlGaN barrier layer 8; the AlGaN barrier layer 8 and the GaN buffer layer 7 form an AlGaN/GaN heterojunction, a groove is arranged above the AlGaN barrier layer 8, the gate electrode 3 is positioned in the groove and wrapped above and on two sides of the heterojunction to form a three-dimensional ring gate structure; the AlGaN/GaN heterojunction under the gate electrode 3 has a nano pattern to form a nano channel 5; the two ends of the nano channel 5 are provided with channel expansion regions 4; the gate dielectric layer 9 is positioned between the AlGaN barrier layer 8 and the gate electrode 3, covers the top of the AlGaN/GaN heterojunction and wraps the two side walls of the nano channel 5; the source electrode 1 and the drain electrode 2 are respectively positioned above the expansion area 4 of the nano-channel 5; the passivation layer 10 covers the entire surface of the device.
The invention will be described in further detail with reference to the accompanying drawings, in conjunction with specific embodiments.
Embodiment one: a single nano-channel based recessed gate enhancement mode GaN transistor device.
Fig. 1 is a top view of an overall structure of an embodiment of the present invention, and fig. 2, 3 and 4 are cross-sectional views of the A-A, B-B and C-C planes of fig. 1, respectively. The groove gate enhanced GaN transistor device based on the single nano-channel 5 comprises a substrate layer 6, a GaN buffer layer 7, an AlGaN barrier layer 8, a gate dielectric layer 9, a passivation layer 10, a source electrode 1, a drain electrode 2 and a gate electrode 3 from bottom to top.
The substrate layer 6 is made of sapphire, siC or GaN.
Above the substrate layer 6 is a GaN buffer layer 7 with a thickness of 0.5-2.5 μm.
Above the buffer layer is an AlGaN barrier layer 8 with a thickness of 10-20nm and an Al composition of 15% -30%.
The AlGaN barrier layer 8 and the GaN buffer layer 7 form an AlGaN/GaN heterojunction, a groove is arranged above the AlGaN barrier layer 8, the gate electrode 3 is positioned in the groove and wrapped above and on two sides of the heterojunction, and a three-dimensional ring gate structure is formed. Wherein the distance D between the bottom of the gate groove and the AlGaN/GaN heterojunction ch1 0-15nm.
The AlGaN/GaN heterojunction under the gate electrode 3 has a nanopattern, forming nano-channels 5, wherein the number n of the nano-channels 5 is n=1, and the length L ch Is L ch Length of gate electrode 3L g The method comprises the steps of carrying out a first treatment on the surface of the Width W of nano channel 5 ch Distance D between the bottom of the nano channel 5 and AlGaN/GaN heterojunction is 10-200nm ch2 0-150nm.
The nanochannel 5 has channel extension regions 4 at both ends.
The gate dielectric layer 9 is positioned between the AlGaN barrier layer 8 and the gate electrode 3, covers the top of the AlGaN/GaN heterojunction and wraps the two side walls of the nano channel 5, and the gate dielectric layer 9 adopts SiN and Al 2 O 3 、SiO 2 Or a stacked structure of multiple dielectric layers with a thickness of 1-15nm.
Passivation layer 10 is located on the surface of the entire device except the electrode, passivation layer 10 is made of SiN, al 2 O 3 、SiO 2 Or a stacked structure of a plurality of passivation layers 10, with a thickness of 50-150nm.
The source electrode 1 and the drain electrode 2 are ohmic contacts and are positioned on the channel expansion regions 4 at two ends of the nano-channel 5.
Embodiment two: a single nano-channel based recessed gate enhancement mode GaN transistor device.
As shown in fig. 5, the single-nano-channel 5-based recessed gate enhancement type GaN transistor device of the present embodiment has the same structure as that of the first embodiment, but the length L of the nano-channel 5 ch Is L ch >Gate length L g 。
Embodiment III: a recessed gate enhancement mode GaN transistor device based on multiple nano-channels.
As shown in fig. 6, the recessed gate enhancement type GaN transistor device based on multiple nano-channels of the present embodiment has the same structure as that of the first embodiment, but the number n of nano-channels 5 is n >1.
Embodiment four: t-shaped groove gate enhanced GaN transistor device based on single nanometer channel.
As shown in fig. 7, the single-nano-channel 5-based T-type recess gate enhancement type GaN transistor device of the present embodiment has the same structure as that of the first embodiment, but the gate electrode 3 adopts a T-type gate structure.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. The groove gate enhanced GaN transistor device based on the nano-channel comprises a substrate layer (6), a GaN buffer layer (7), an AlGaN barrier layer (8), a gate dielectric layer (9), a passivation layer (10), a source electrode (1), a drain electrode (2) and a gate electrode (3) from bottom to top; the method is characterized in that: the AlGaN barrier layer (8) and the GaN buffer layer (7) form an AlGaN/GaN heterojunction, a groove is formed above the AlGaN barrier layer (8), and the gate electrode (3) is positioned in the groove and wraps the upper side and the two sides of the AlGaN/GaN heterojunction to form a three-dimensional ring gate structure; the AlGaN/GaN heterojunction under the gate electrode (3) is provided with a nano pattern to form a nano channel (5); two ends of the nano channel (5) are provided with channel expansion regions (4); the gate dielectric layer (9) is positioned below the gate electrode (3), between the source electrode (1) and the drain electrode (2), covers the top of the AlGaN/GaN heterojunction and wraps the two side walls of the nano channel (5).
2. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the substrate layer (6) is sapphire, siC or GaN.
3. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the thickness of the GaN buffer layer (7) is 0.5-2.5um.
4. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the thickness of the AlGaN barrier layer (8) is 10-20nm, and the Al content is 15% -30%.
5. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the number of nanochannels (5)n is not less than 1, length L ch Is 0 to<L ch <The distance between the source electrode (1) and the drain electrode (2), the width W ch 10-200nm.
6. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: distance D between the bottom of the groove on the AlGaN barrier layer (8) and the AlGaN/GaN heterojunction ch1 A distance D between the bottom of the nano channel (5) and the AlGaN/GaN heterojunction is 0-15nm ch2 0-150nm.
7. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the gate dielectric layer (9) is SiN, al 2 O 3 、SiO 2 Or a stacked structure of multiple dielectric layers with a thickness of 1-15nm.
8. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the passivation layer (10) is SiN, al 2 O 3 、SiO 2 Or a stacked structure of a plurality of passivation layers (10) having a thickness of 50-150nm.
9. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the gate electrode (3) is a straight gate or a T-shaped gate, and the gate length L g =L ch Or L g >L ch Or L g <L ch 。
10. The nano-channel based recessed gate enhancement mode GaN transistor device of claim 1, wherein: the source electrode (1) and the drain electrode (2) are in ohmic contact and are positioned on the channel expansion regions (4) at two ends of the nano channel (5).
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CN107919397A (en) * 2017-11-20 2018-04-17 西安电子科技大学 A kind of High Linear FET device and preparation method thereof
CN108470768B (en) * 2018-03-02 2020-12-22 华南理工大学 Preparation method of HEMT device nano grid
CN108666216B (en) * 2018-05-15 2021-05-07 西安电子科技大学 HEMT device based on laminated passivation structure and preparation method thereof
US11349003B2 (en) * 2019-05-15 2022-05-31 Cambridge Electronics, Inc. Transistor structure with a stress layer
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JP2009049288A (en) * 2007-08-22 2009-03-05 Nec Corp Semiconductor device
CN104201104A (en) * 2014-09-09 2014-12-10 电子科技大学 Manufacturing method for gallium nitride-based enhanced device
RU160576U1 (en) * 2015-10-29 2016-03-27 федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) TRANSISTOR HETEROSTRUCTURE OF TYPE P-HEMT WITH VARIZONAL BARRIER AlX (Z) Ga1-X (Z) As
CN206947353U (en) * 2017-05-25 2018-01-30 中国电子科技集团公司第十三研究所 The enhanced GaN transistor device of notched gates based on nano-channel

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