CN114843187B - Preparation method of GaN-based nano-channel high electron mobility transistor - Google Patents

Preparation method of GaN-based nano-channel high electron mobility transistor Download PDF

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CN114843187B
CN114843187B CN202110141892.7A CN202110141892A CN114843187B CN 114843187 B CN114843187 B CN 114843187B CN 202110141892 A CN202110141892 A CN 202110141892A CN 114843187 B CN114843187 B CN 114843187B
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CN114843187A (en
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张斌
王金延
李梦军
陶倩倩
王鑫
汪晨
吴文刚
谢勇
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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Abstract

The invention discloses a preparation method of a GaN-based nano-channel high electron mobility transistor, and belongs to the technical field of microelectronic devices. The method adopts a high-temperature oxidation corrosion method, and a nano-channel array structure is formed by wet etching. Because no plasma is introduced in the wet etching, no damage is generated on the side face of the nano channel array; meanwhile, in a certain temperature range, only AlGaN materials are oxidized, but GaN materials are not oxidized, so that corrosion can be stopped on the surface of GaN, consistency between channels and between devices is ensured, and the method is suitable for large-scale commercial production.

Description

Preparation method of GaN-based nano-channel high electron mobility transistor
Technical Field
The invention belongs to the technical field of microelectronic devices, and particularly relates to a preparation method of a GaN-based multi-nano-channel high-electron-mobility transistor.
Background
The GaN material belongs to a third-generation semiconductor material, has the advantages of large forbidden bandwidth, high breakdown field intensity, high electron saturation rate and the like, and the AlGaN/GaN heterostructure can generate high-concentration and high-electron mobility two-dimensional electron gas in a channel under the actions of spontaneous polarization and piezoelectric polarization, so that the GaN-based HEMT device is considered as an optimal option for preparing high-speed and high-voltage power electronic switching devices and high-frequency high-power microwave power devices.
AlGaN/GaN high electron mobility transistors are typically depletion mode devices due to spontaneous polarization and piezoelectric polarization effects, and the fabrication methods of enhancement mode devices are difficult, making large scale commercialization difficult. Depletion mode devices have limitations in the application process. In the application of a power electronic circuit, in order to drive a depletion type GaN device, a complex driving circuit is required to be designed, and even a negative bias system is required to ensure that the device is turned off, so that on one hand, the design complexity is increased; on the other hand, the reliability of the operation of the circuit is affected, and once the negative bias system fails, a large current flows in the device, so that the reliability of the device is caused, and even the device is burnt out. Therefore, it is very important to develop an enhancement type GaN transistor with mass production and high reliability.
Along with the continuous reduction of the gate length, the short channel effect of the GaN-based HEMT device with the traditional planar structure is more remarkable, and the short channel effect is particularly characterized by reduced gate control capability, increased electric leakage of the device in an off state, reduced switching rate and the like. In order to inhibit the short channel effect of the device, a high electron mobility transistor adopting a nano channel structure with three-sided ring gates is adopted at present, and the gate control capability of the high electron mobility transistor is obviously enhanced because three sides of a channel of the structure are surrounded by the gates. At present, plasma etching is mostly adopted to etch AlGaN and GaN materials in a non-channel region to form a nano channel, however, the plasma has higher damage, so that damage can be generated at the edge of the channel, and a certain leakage path can be introduced into the device due to the damage, so that the reliability problem of the device is caused; in addition, the rate of plasma etching is affected by the equipment and epitaxial wafer material characteristics, and it is difficult to achieve device-to-device uniformity on a mass production scale.
Disclosure of Invention
Aiming at the defects of the preparation method of the high electron mobility transistor, the invention provides a brand-new preparation method of the GaN-based multi-nano-channel high electron mobility transistor, namely a high-temperature oxidation corrosion method is adopted, and a nano-channel array structure is formed by wet etching. Because no plasma is introduced in the wet etching, no damage is generated on the side face of the nano channel array; at the same time, only AlGaN material is oxidized at a certain temperature, but GaN material is not oxidized, so that corrosion can be stopped on the surface of GaN, consistency between channels and devices is ensured, and the method is suitable for large-scale commercial production.
The invention provides a preparation method of a GaN-based nano-channel high electron mobility transistor, which comprises the following steps:
1) Preparing an epitaxial wafer, namely growing a heterojunction structure with a GaN cap layer/AlGaN barrier layer/GaN buffer layer on a substrate;
2) Etching the GaN cap layer along the channel direction to form a nano channel mask array, wherein the width of each nano channel mask in the array is 0.1-0.5 um, the length is 1-2 um, the interval of the nano channel masks is 0.5-1 um, and the AlGaN barrier layer is exposed; the area which is not etched with the GaN cap layer is used as a mask layer for high-temperature oxidation corrosion;
3) Sending the epitaxial wafer into a high-temperature oxidation furnace, wherein the GaN cap layer and the AlGaN layer below the GaN cap layer are not oxidized, and the AlGaN layer which is not covered by the GaN cap layer is completely oxidized;
4) Placing the epitaxial wafer in corrosive liquid, and completely corroding the oxidized AlGaN layer to form a non-damaged multi-nano-channel structure;
5) Depositing an AlN layer by an atomic layer deposition technology, and then growing the SiN layer by LPCVD to be used as a gate dielectric stack;
6) Etching the SiN dielectric layer of the ohmic region by adopting an ICP technology, etching the AlN layer, growing an ohmic metal lamination, stripping, leaving the metal lamination in the ohmic contact region, and annealing at a high temperature in a rapid thermal annealing furnace to form ohmic contact;
7) F plasma injection is adopted for non-device areas to destroy the lattice structure, so that electrical isolation among devices is realized;
8) And depositing a gate metal lamination, stripping, and leaving the metal lamination in the gate area to finish the manufacture of the GaN-based nano-channel high electron mobility transistor.
The substrate in the step 1) is silicon or sapphire or silicon carbide.
In the step 1), a heterojunction structure is grown by adopting an MOCVD technology, specifically a 2.5-3 nm GaN cap layer, a 20-25 nm AlGaN barrier layer, a 400-420 nm i-GaN layer and a 4-4.5 um GaN buffer layer.
And in the step 2), a reactive plasma etching technology is adopted to etch the GaN cap layer.
And 3) oxidizing in an oxygen atmosphere at 620-680 ℃ for 40-60 minutes.
The etching solution in the step 4) is TMAH or KOH solution with the temperature of 70-90 ℃ and the etching time is 50-70 minutes.
The invention has the technical effects that:
1) The high-temperature oxidation corrosion process can ensure that no damage is caused to the nano channel of the device because no plasma is introduced;
2) The high-temperature oxidation corrosion has the characteristic of self-stopping, so that consistency between channels and between devices can be realized;
3) The structure of the multiple nano channels can improve the on-current of the device, improve the gate control capability and inhibit the short channel effect.
Drawings
FIG. 1 is a top view of a GaN-based multichannel high electron mobility transistor fabricated using the present invention;
FIG. 2 is a cross-sectional view taken along the direction A1-A2 of FIG. 1;
FIG. 3 is a cross-sectional view in the direction B1-B2 of FIG. 1;
Fig. 4 is an epitaxial wafer prepared for fabrication of a device;
FIG. 5 is a process of etching a non-nano-channel region GaN cap layer; wherein (a) is the A1-A1 direction; (B) is the B1-B2 direction;
FIG. 6 is a process of etching a non-nano-channel region GaN cap layer and forming a nano-channel; wherein (a) is the A1-A2 direction; (B) is the B1-B2 direction;
FIG. 7 is a process of growing an AlN and SiN dielectric stack; wherein (a) is the A1-A2 direction; (B) is the B1-B2 direction;
Fig. 8 is a process of fabricating an ohmic contact in the B1-B2 direction;
FIG. 9 is a process of F-plasma implantation to form electrical isolation between devices; wherein (a) is the A1-A2 direction; (B) is the B1-B2 direction;
In the above figures, a 1-Si substrate; 2-GaN buffer layer; 3-AlGaN barrier layer; 4-GaN cap layer; 5-nano-channels; 6-ohmic metal stack (Ti/Al/Ni/Au); 7-AlN dielectric layer; 8-a SiN dielectric layer; 9-gate metal stack (Ni/Au).
Detailed Description
The method for implementing the GaN-based multi-nano-channel high electron mobility transistor according to the present invention is further described below by way of specific examples with reference to the accompanying drawings.
In the invention, si is taken as a substrate, a GaN cap layer/AlGaN barrier layer/GaN buffer layer is grown on the substrate by MOCVD technology, and the specific implementation steps are as shown in figures 4-9:
(1) The prepared epitaxial wafer takes Si as a substrate, and 2.5nm GaN/25nm AlGaN/420nm i-GaN/4.2um buffer/1000um Si grows on the substrate through MOCVD technology, as shown in figure 4;
(2) Etching the GaN cap layer along the channel direction by adopting a reactive plasma etching technology to form a nano-channel mask array, wherein the width of the mask array is about 0.2um so as to achieve a better gate control effect, the length is 1um, the interval of the mask array is about 0.5um, the number of the arrays is 10, the AlGaN barrier layer is exposed, the GaN cap layer is used as a mask layer for high-temperature oxidation corrosion in the area where the GaN cap layer is not etched, the sectional view along the A1-A2 direction after etching is shown in FIG. 5 (a), and the sectional view along the B1-B2 direction is shown in FIG. 5 (B);
(3) Feeding the epitaxial wafer into a high-temperature oxidation furnace, and oxidizing for 40 minutes in an oxygen atmosphere at 630 ℃, wherein at the temperature, the GaN cap layer and the AlGaN layer below the GaN cap layer are not oxidized, and the AlGaN layer which is not covered by the GaN cap layer is completely oxidized;
(4) Placing the epitaxial wafer in a TMAH solution at 80 ℃ for 1 hour, completely etching the oxidized AlGaN layer to form a non-damaged multi-nano-channel structure, wherein the width of the nano-channel array is about 0.2um, the length of the nano-channel array is 1um, the interval of the mask array is about 0.5um, the number of the arrays is 10, the cross section of the formed multi-nano-channel structure along the A1-A2 direction is shown in FIG. 6 (a), and the cross section along the B1-B2 direction is shown in FIG. 6 (B);
(5) ALD grows a 5nm AlN layer, LPCVD grows a 25nm SiN layer as a gate dielectric stack, a cross section along the A1-A2 direction after the passivation layer is grown is shown in FIG. 7 (a), and a cross section along the B1-B2 direction is shown in FIG. 7 (B);
(6) Etching the SiN dielectric layer in the ohmic region by adopting an ICP technology, etching the AlN layer by adopting a BOE solution of 5:1, then growing an ohmic metal lamination Ti/Al/Ni/Au, leaving the metal lamination in the ohmic contact region after stripping, and forming ohmic contact by annealing for 33s at a high temperature of 860 ℃ in a rapid thermal annealing furnace, wherein FIG. 8 is a sectional view of the device along the direction B1-B2 after the ohmic contact is grown;
(7) F plasma implantation is adopted to the non-device area to break the lattice structure, so that the electrical isolation between devices is realized, the cross section of the plasma implantation process along the direction A1-A2 is shown in FIG. 9 (a), and the cross section along the direction B1-B2 is shown in FIG. 9 (B);
(8) Depositing gate metal lamination Ni/Au, stripping, and leaving the metal lamination in the gate area to finish the manufacture of the GaN-based multi-nano-channel high electron mobility transistor by a thermal oxidation wet etching process. Fig. 1 to 3 are views showing a GaN-based multi-nano-channel high electron mobility transistor based on a thermal oxidation wet etching process, respectively.
While the invention has been described in terms of preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (9)

1. A preparation method of a GaN-based nano-channel high electron mobility transistor comprises the following steps:
1) Preparing an epitaxial wafer, namely growing a heterojunction structure with a GaN cap layer/AlGaN barrier layer/GaN buffer layer on a substrate;
2) Etching the GaN cap layer along the channel direction to form a nano channel mask array, wherein the width of each nano channel mask in the array is 0.1-0.5 um, the length is 1-2 um, the interval of the nano channel masks is 0.5-1 um, and the AlGaN barrier layer is exposed; the area which is not etched with the GaN cap layer is used as a mask layer for high-temperature oxidation corrosion;
3) Sending the epitaxial wafer into a high-temperature oxidation furnace, wherein the GaN cap layer and the AlGaN layer below the GaN cap layer are not oxidized, and the AlGaN layer which is not covered by the GaN cap layer is completely oxidized;
4) Placing the epitaxial wafer in corrosive liquid, and completely corroding the oxidized AlGaN layer to form a non-damaged multi-nano-channel structure;
5) Depositing an AlN layer by an atomic layer deposition technology, and then growing the SiN layer by LPCVD to be used as a gate dielectric stack;
6) Etching the SiN dielectric layer of the ohmic region by adopting an ICP technology, etching the AlN layer, growing an ohmic metal lamination, stripping, leaving the metal lamination in the ohmic contact region, and annealing at a high temperature in a rapid thermal annealing furnace to form ohmic contact;
7) F plasma injection is adopted for non-device areas to destroy the lattice structure, so that electrical isolation among devices is realized;
8) And depositing a gate metal lamination, stripping, and leaving the metal lamination in the gate area to finish the manufacture of the GaN-based nano-channel high electron mobility transistor.
2. The method of claim 1, wherein the substrate in step 1) is silicon or sapphire or silicon carbide.
3. The method of claim 1, wherein the heterojunction structure is grown in step 1) by using MOCVD technique, specifically 2.5-3 nm GaN cap layer/20-25 nm AlGaN barrier layer/400-420 nm i-GaN/4-4.5 um GaN buffer layer.
4. The method of claim 1, wherein the GaN cap layer is etched in step 2) using a reactive plasma etching technique.
5. The method according to claim 1, wherein step 3) is performed in an oxygen atmosphere at 620 to 680 ℃ for 40 to 60 minutes.
6. The method according to claim 1, wherein the etching solution in step 4) is a TMAH or KOH solution at 70-90 ℃ and the etching time is 50-70 minutes.
7. The method according to claim 1, wherein the AlN layer has a thickness of 3 to 5nm and the SiN layer has a thickness of 25 to 30nm in step 5).
8. The method of claim 1, wherein step 6) etches the AlN layer with a 5:1 BOE solution.
9. The method according to claim 1, wherein the high-temperature annealing in step 6) is performed at 850 to 880℃for 30 to 40 seconds.
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Citations (6)

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JP2012054376A (en) * 2010-09-01 2012-03-15 Nec Corp Photon generator, optical device, and method of manufacturing the photon generator
CN105118780A (en) * 2015-07-30 2015-12-02 中国电子科技集团公司第五十五研究所 Method of reducing GaN HEMT device ohm contact resistance
CN105762078A (en) * 2016-05-06 2016-07-13 西安电子科技大学 GaN-based nanometer channel transistor with high electron mobility and manufacture method
CN106887454A (en) * 2017-03-14 2017-06-23 西安电子科技大学 GaN base fin grid enhancement device and preparation method thereof
CN106981514A (en) * 2017-05-25 2017-07-25 中国电子科技集团公司第十三研究所 The enhanced GaN transistor device of notched gates based on nano-channel
CN110676167A (en) * 2018-07-02 2020-01-10 西安电子科技大学 AlInN/GaN high electron mobility transistor with multi-channel fin structure and manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012054376A (en) * 2010-09-01 2012-03-15 Nec Corp Photon generator, optical device, and method of manufacturing the photon generator
CN105118780A (en) * 2015-07-30 2015-12-02 中国电子科技集团公司第五十五研究所 Method of reducing GaN HEMT device ohm contact resistance
CN105762078A (en) * 2016-05-06 2016-07-13 西安电子科技大学 GaN-based nanometer channel transistor with high electron mobility and manufacture method
CN106887454A (en) * 2017-03-14 2017-06-23 西安电子科技大学 GaN base fin grid enhancement device and preparation method thereof
CN106981514A (en) * 2017-05-25 2017-07-25 中国电子科技集团公司第十三研究所 The enhanced GaN transistor device of notched gates based on nano-channel
CN110676167A (en) * 2018-07-02 2020-01-10 西安电子科技大学 AlInN/GaN high electron mobility transistor with multi-channel fin structure and manufacturing method

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