CN107742644B - A high performance normally-off GaN field effect transistor and a method for preparing the same - Google Patents

Abstract

The present invention relates to the technical field of semiconductor device preparation, and more specifically, to a high-performance normally-off GaN field effect transistor and a preparation method thereof. The device includes a substrate and an epitaxial layer, a gate dielectric layer, a gate, a drain, and a source grown on the substrate. The epitaxial layer includes a stress buffer layer and a GaN channel layer grown by a primary epitaxial growth. Through mask patterning and etching processes, the mask is retained only in the gate area. After the mask residue and surface contamination in the access area are removed by in-situ etching, an AlGaN/GaN heterojunction structure is selectively grown in the area to form a groove channel. The gate metal is covered at the groove channel, and source and drain regions are formed at both ends of the device and covered with metal to form the source and drain. The device structure and preparation process of the present invention are simple and reliable. In-situ etching of the access area can reduce defect impurities introduced into the device access area during mask preparation, obtain a high-quality access area interface, ensure the quality of the secondary epitaxial AlGaN/GaN heterostructure, and thus improve the conduction performance of the normally-off GaN field effect transistor.

Description

A high performance normally-off GaN field effect transistor and its preparation method

Technical Field

The present invention relates to the technical field of semiconductor device preparation, and more specifically, to a high-performance normally-off GaN field effect transistor and a preparation method thereof, and more specifically to an improved method for selectively epitaxially preparing a secondary growth interface of an access region of a recessed gate normally-off GaN field effect transistor.

Background technique

As a representative of the third generation of semiconductor materials, GaN has the characteristics of large bandgap width, large critical breakdown electric field strength, high power density and high carrier saturation velocity. GaN power switching devices can significantly increase the upper limit operating frequency while maintaining the low noise performance and high rated power of metal semiconductor field effect tubes, and have the advantages of higher operating voltage, higher power density and high temperature resistance, which makes GaN-based devices gradually replace the original Si-based and GaAs-based devices in some power devices and high-frequency circuits.

The preparation method of the groove in the traditional groove gate normally-off GaN power device is to epitaxially grow an AlGaN/GaN heterostructure once, and then reduce the concentration of the two-dimensional electron gas in the area under the gate while keeping the concentration of the two-dimensional electron gas in the access area unchanged. Generally, there are the following methods: plasma etching groove structure, F plasma injection, adding a P-type cap layer, etc. However, these methods inevitably use plasma processing technology. The lattice damage to the area under the gate caused by plasma etching grooves or injection treatment will increase the leakage current of the device and reduce the gate control ability; while the P-type cap layer scheme will cause lattice damage to the access area, affecting the stability of the two-dimensional electron gas channel and the reliability of the device. Compared with the above methods, the selective area growth (SAG) method can avoid the damage to the active layer of the device caused by plasma treatment, improve the interface quality of the gate area, and improve the stability and reliability of the device. However, in the selective area epitaxial GaN groove gate structure field effect transistor, the AlGaN/GaN heterojunction structure in the device access area is formed by secondary epitaxy, and the quality of the secondary epitaxial AlGaN/GaN heterojunction structure directly determines the performance of the device. Before the secondary growth of AlGaN/GaN epitaxial layer, the epitaxial wafer covered with _SiO2 mask layer needs to be deeply cleaned, which makes the substrate with GaN channel layer exposed to the air, and its surface is oxidized by air and contaminated by C and Si impurities. At the same time, when the AlGaN/GaN epitaxial layer is secondary grown by metal organic chemical vapor deposition method, the Si substrate needs to be treated at high temperature to clean the Si substrate, but only _H2 is used as carrier gas during the heating process. This heating condition will damage the surface of GaN material, because GaN is easy to decompose in _H2 environment, and its reaction equation is:

GaN reacts with _H2 at high temperatures to produce Ga droplets and ammonia. Ga droplets can cause unevenness in the secondary epitaxial growth interface, thereby deteriorating the quality of the secondary epitaxial AlGaN/GaN heterojunction structure. More seriously, the preparation of the selective area epitaxial mask pattern requires the use of plasma enhanced chemical vapor deposition to grow a _SiO2 mask layer on the surface of the substrate with a GaN channel layer, and then remove the _SiO2 mask covering the access area by dry/wet etching. This process has the risk of Si residue. The introduction of too many impurities will deteriorate the quality of the secondary epitaxial heterostructure, reduce the two-dimensional electron gas concentration of the conductive channel in the access area, and is not conducive to improving the conduction performance of the device. Therefore, it is necessary to seek a method for optimizing the interface quality of the access area of a normally-off GaN field effect transistor to overcome the disadvantage of introducing defect impurities into the device access area caused by the selective area growth method, so as to obtain a high-performance normally-off GaN field effect transistor.

Summary of the invention

In order to overcome at least one defect of the above-mentioned prior art, the present invention provides a high-performance normally-off GaN field effect transistor and a preparation method thereof. By in-situ etching the GaN channel layer of the access area, before growing the secondary epitaxial layer, the impurities such as Si and C/O introduced into the interface of the access area during the mask preparation process are reduced, and the mask residue and surface contamination of the access area are removed, thereby improving the secondary growth interface quality of the access area of the device, and keeping the two-dimensional electron gas concentration of the access area channel basically unchanged, thereby preparing a high-performance normally-off GaN field effect transistor.

The technical solution of the present invention is: a high-performance normally-off GaN field effect transistor, which includes, from bottom to top, a substrate, a stress buffer layer, a GaN channel layer, in-situ etching of the GaN channel layer in the access area and then growing a secondary epitaxial layer, removing the gate mask to form a groove gate structure and depositing a gate dielectric layer on the surface, removing the gate dielectric layer at both ends of the device and forming a source and a drain, and the gate dielectric layer in the groove gate area is covered with a gate.

Furthermore, the substrate is any one of a sapphire substrate, a silicon carbide substrate, a silicon substrate, and a gallium nitride self-supporting substrate.

The stress buffer layer is any one or a combination of AlGaN, GaN and AlN; the thickness of the stress buffer layer is 100nm-10μm.

The GaN channel layer is an unintentionally doped GaN channel layer or a doped high-resistance GaN channel layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN channel layer under the groove area is 100nm-20μm, which is 10-50nm less than the thickness of the GaN channel layer under the lower access area.

The secondary epitaxial layer is an AlGaN/GaN heterojunction, the thickness of the AlGaN layer is 10-50nm, the concentration of the aluminum component can be changed, and the thickness of the GaN layer is 10-500nm.

The groove gate structure is formed by in-situ etching the GaN channel layer of the access area to remove surface contamination and grow a secondary epitaxial layer, presenting a U-shaped or trapezoidal structure. The method of in-situ etching the access area is that the GaN channel layer of the access area has mask residues and impurities introduced when forming the gate mask layer. In-situ etching the GaN channel layer of the access area can remove surface defect states of the access area, while reducing the introduction of environmental impurities, and obtain a high-quality secondary epitaxial interface.

The gate dielectric layer is Al ₂ O ₃ or Si ₃ N ₄ compound, and has a thickness of 10-100 nm.

The source and drain materials include but are not limited to Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy, and various other metals or alloys that can achieve ohmic contact can be used as source and drain materials; the gate material includes but is not limited to Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Al/Ti/TiN alloy, and various other metals or alloys that can achieve high threshold voltage can be used as gate materials.

A method for preparing a high-performance normally-off GaN field effect transistor, comprising the following steps:

S1, growing a stress buffer layer on a substrate;

S2, growing a GaN channel layer on the stress buffer layer;

S3, depositing a layer of SiO ₂ on the GaN channel layer as a mask layer;

S4, retaining the mask layer above the gate region by photolithography combined with a dry or wet etching method;

S5, in-situ etching of the GaN channel layer in the access area, with an etching depth of 10 to 50 nm;

S6, growing a secondary epitaxial layer in a selected area to form a groove-type gate structure;

S7, removing the mask layer above the gate region;

S8, depositing to form a gate dielectric layer;

S9, dry etching to complete the mesa isolation of the device, and at the same time etch out the source and drain ohmic contact areas;

S10, evaporating source and drain metals on the source and drain regions, and forming ohmic contacts by annealing the ohmic alloy;

S11, evaporating a gate metal in the gate region on the gate dielectric layer at the groove.

The growth methods of the stress buffer layer in step S1, the GaN channel layer in step S2 and the secondary epitaxial layer in step S6 are high-quality film-forming methods such as metal organic chemical vapor deposition and molecular beam epitaxy; the growth method of the mask layer in step S3 is plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering; the in-situ etching method in step S5 is dry etching, and the etching gas environment is any one or a combination of _N2 and _NH3 ; the growth method of the gate dielectric layer in step S8 is low pressure chemical vapor deposition.

Compared with the prior art, the beneficial effects are: the present invention improves the quality of the secondary growth interface of the device access region, keeps the concentration of the two-dimensional electron gas in the access region channel basically unchanged, thereby improving the conduction performance of the device. The present invention adds a step to the conventional selective area growth method, before growing the secondary epitaxial layer AlGaN/GaN heterojunction structure, the GaN channel layer without _SiO2 mask layer is in-situ etched to remove the _SiO2 mask residue on the access region and the interface containing more C and Si donor impurities, while reducing the environmental impurities introduced in the preparation stage before the secondary growth of the epitaxial layer, thereby improving the quality of the secondary epitaxial heterojunction structure, keeping the concentration of the two-dimensional electron gas in the access region channel basically unchanged, and improving the conduction performance of the device. The device structure of the present invention is simple, the process repeatability and reliability are high, while maintaining the high quality of the lower interface of the device gate region, the quality of the interface of the device access region is improved, thereby providing a technology for preparing a high-performance normally-off GaN field effect transistor device.

BRIEF DESCRIPTION OF THE DRAWINGS

1-11 are schematic diagrams of the device manufacturing method according to Example 1 of the present invention.

12-14 are schematic diagrams of a process for preparing a mask layer on a gate region according to Embodiment 2 of the present invention.

Detailed ways

The drawings are only for illustrative purposes and cannot be construed as limiting the present invention. To better illustrate the present embodiment, some parts of the drawings may be omitted, enlarged, or reduced, and do not represent the size of the actual product. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the drawings. The positional relationships described in the drawings are only for illustrative purposes and cannot be construed as limiting the present invention.

Example 1

As shown in Figure 11, it is a schematic diagram of the device structure of this embodiment, which includes a substrate 1, a stress buffer layer 2, a GaN channel layer 3 from bottom to top, the GaN channel layer 3 in the access area is in-situ etched and then a secondary epitaxial layer 4 is grown, the gate mask is removed to form a groove gate structure and a gate dielectric layer 5 is deposited on the surface, the gate dielectric layer is removed at both ends of the device to form a source 6 and a drain 7, and the gate dielectric layer in the groove gate area is covered with a gate 8.

The above-mentioned method for preparing a high-performance normally-off GaN field effect transistor is shown in Figures 1 to 10, and comprises the following steps:

S1, growing a stress buffer layer 2 on a Si substrate 1 by using a metal organic chemical vapor deposition method, as shown in FIG1 ;

S2, growing a GaN channel layer 3 on the stress buffer layer 2 by using a metal organic chemical vapor deposition method, as shown in FIG2 ;

S3, using a plasma enhanced chemical vapor method to deposit a layer of SiO ₂ as a mask layer 9, as shown in FIG3 ;

S4, using photolithography combined with reactive coupled plasma etching to retain the mask layer 9 above the gate region, as shown in FIG4 ;

S5, in-situ etching the access area in a _N2 gas environment using a dry etching method, as shown in FIG5 ;

S6, using a metal organic chemical vapor deposition method, selectively growing a secondary epitaxial AlGaN/GaN layer 4 on the substrate having the mask layer 9 to form a groove structure, as shown in FIG6 ;

S7, using a wet etching method to remove the mask layer 9 on the gate region, as shown in FIG7 ;

S8, growing a gate dielectric layer 5 by low pressure chemical vapor deposition method, as shown in FIG8 ;

S9, using reactive coupled plasma etching to complete the mesa isolation of the device, and at the same time etching out the source and drain ohmic contact regions, as shown in FIG9 ;

S10, vapor-depositing Ti/Al/Ni/Au alloy on the source and drain regions as the ohmic contact metal of the source 6 and the drain 7, and forming ohmic contacts by annealing the ohmic alloy, as shown in FIG10 ;

S11 , evaporating Ni/Au alloy on the gate dielectric layer in the recessed gate region as the gate 9 metal, as shown in FIG. 11 .

At this point, the entire device preparation process is completed. FIG11 is a schematic diagram of the device structure of Example 1.

Example 2

Figures 12-14 are schematic diagrams of the process of preparing the _SiO2 mask layer on the gate region in Example 2 of the present invention, which differs from the method for preparing the _SiO2 mask layer on the gate region in Example 1 only in that the mask pattern on the gate region is formed by reactive coupled plasma etching in Example 1, while the mask pattern on the gate region is formed by a stripping method in Example 2. The specific process includes the following steps:

S1, partially forming a photoresist protection layer 10 with a patterned structure on the secondary epitaxial layer 3, as shown in FIG12;

S2, depositing a layer of SiO ₂ as a mask layer 9 on the substrate having the photoresist protection layer 10 by using a plasma enhanced chemical vapor method, as shown in FIG. 13 ;

S3, using a photoresist stripping solution to remove the photoresist protective layer 10, and at the same time remove the mask layer 9 on the protective layer, retaining the mask layer on the gate region, so that the mask layer is patterned, as shown in FIG. 14 .

The use of a stripping process to prepare the _SiO2 mask on the gate region can effectively solve the problem of easy damage to the growth interface when the mask layer is made by traditional photolithography and etching processes. However, since the GaN channel layer 3 is exposed to the air before the secondary epitaxial layer 4 is grown, its surface is oxidized by air and contaminated by C and Si impurities. Therefore, the stripping process still cannot completely solve the defect problem of the interface in the device access area. The preparation method provided by this patent can obtain a higher quality secondary epitaxial growth interface in the access area.

In addition, it should be noted that the drawings of the above embodiments are for illustrative purposes only and therefore do not necessarily need to be drawn to scale.

Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims (8)

1. A high-performance normally-off GaN field effect transistor, characterized in that it comprises, from bottom to top, a substrate (1), a stress buffer layer (2), a GaN channel layer (3), a secondary epitaxial layer (4) is grown after in-situ etching of the GaN channel layer in the access area, a gate mask is removed to form a groove gate structure and a gate dielectric layer (5) is deposited on the surface, the gate dielectric layer (5) is removed at both ends of the device and a source (6) and a drain (7) are formed, and a gate (8) is covered on the gate dielectric layer (5) in the groove gate area; the groove gate structure is formed by in-situ etching of the GaN channel layer (3) in the access area to remove surface contamination and growing the secondary epitaxial layer (4), presenting a U-shaped or trapezoidal structure; when the gate mask layer is formed, the GaN channel layer (3) in the access area has mask residues and impurities introduced, and the in-situ etching of the GaN channel layer (3) in the access area can remove surface defect states in the access area and reduce the introduction of environmental impurities, thereby obtaining a high-quality secondary epitaxial interface. 2. A high-performance normally-off GaN field effect transistor according to claim 1, characterized in that: the substrate (1) is any one of a sapphire substrate, a silicon carbide substrate, a silicon substrate, and a gallium nitride self-supporting substrate. 3. A high-performance normally-off GaN field effect transistor according to claim 1, characterized in that: the stress buffer layer (2) is any one or a combination of AlGaN, GaN, and AlN; and the thickness of the stress buffer layer is 100nm to 10μm. 4. A high-performance normally-off GaN field effect transistor according to claim 1, characterized in that: the GaN channel layer (3) is an unintentionally doped GaN channel layer or a doped high-resistance GaN channel layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN channel layer under the groove area is 100nm~20μm, which is 10~50nm less than the thickness of the GaN channel layer under the lower access area. 5. A high-performance normally-off GaN field effect transistor according to claim 1, characterized in that: the secondary epitaxial layer (4) is an AlGaN/GaN heterojunction, the thickness of the AlGaN layer is 10 to 50 nm, the concentration of the aluminum component can be changed, and the thickness of the GaN layer is 10 to 500 nm. 6. A high-performance normally-off GaN field effect transistor according to claim 1, characterized in that: the gate dielectric layer (5) is Al2O3 or Si3N4 compound, with a thickness of 10 to 100 nm; the source (6) and drain (7) materials are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the gate (8) material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Al/Ti/TiN alloy. 7. The method for preparing a high-performance normally-off GaN field effect transistor according to claim 1, characterized in that it comprises the following steps: S1, growing a stress buffer layer (2) on a substrate (1); S2, growing a GaN channel layer (3) on the stress buffer layer (2); S3, depositing a layer of SiO2 on the GaN channel layer (3) as a mask layer (9); S4, retaining the mask layer (9) above the gate region by photolithography combined with a dry or wet etching method; S5, in-situ etching the GaN channel layer (3) in the access area, with an etching depth of 10 to 50 nm; S6, growing a secondary epitaxial layer (4) in a selected area to form a groove-type gate structure; S7, removing the mask layer (9) above the gate region; S8, depositing to form a gate dielectric layer (5); S9, dry etching to complete the mesa isolation of the device, and at the same time etch out the source and drain ohmic contact areas; S10, evaporating source (6) and drain (7) metals in the source and drain regions, and forming ohmic contacts by annealing the ohmic alloy; S11, evaporating a gate (8) metal in the gate region on the gate dielectric layer at the groove. 8. A method for preparing a high-performance normally-off GaN field effect transistor according to claim 7, characterized in that: the growth method of the stress buffer layer (2) in step S1, the GaN channel layer (3) in step S2 and the secondary epitaxial layer (4) in step S6 is a high-quality film-forming method such as metal organic chemical vapor deposition and molecular beam epitaxy; the growth method of the mask layer (9) in step S3 is plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering; the in-situ etching method in step S5 is dry etching, and the etching gas environment is any one or a combination of N2 and NH3; the growth method of the gate dielectric layer in step S8 is low pressure chemical vapor deposition.