CN107742644A - A kind of GaN field-effect transistors of high-performance normally-off and preparation method thereof - Google Patents
A kind of GaN field-effect transistors of high-performance normally-off and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The present invention relates to technical field prepared by semiconductor devices, more particularly, to a kind of GaN field-effect transistors of high-performance normally-off and preparation method thereof.The device includes substrate and the epitaxial layer, gate dielectric layer, grid, drain electrode, the source electrode that are grown on substrate.The epitaxial layer includes the stress-buffer layer and GaN channel layers of an epitaxial growth, pass through mask pattern and etching technics, only retain mask in area of grid, after being stained using the mask residual in situ for etching removal access area and surface, selective area growth AlGaN/GaN heterojunction structures form recess channel.Gate metal is covered at recess channel, and device both ends, which form source electrode and drain region and cover metal, forms source electrode and drain electrode.Device architecture of the present invention and preparation technology are simple and reliable, original position etching access area can reduce in mask preparation process the impurity device access area introduces the defects of, obtain the access area interface of high quality, ensure secondary epitaxy AlGaN/GaN heterojunction structure quality, so as to improve the conduction property of normally-off GaN field-effect transistors.
Description
Technical field
The present invention relates to technical field prepared by semiconductor devices, more particularly, to a kind of GaN of high-performance normally-off
Field-effect transistor and preparation method thereof.Notched gates normally-off GaN field-effect transistors are prepared more particularly to selection region extension
Access area diauxic growth interface improved method.
Background technology
As the representative of third generation semi-conducting material, GaN has that energy gap is big, critical breakdown electric field intensity is big, power
The features such as density is greatly and carrier saturation velocity is high.GaN device for power switching can keep metal semiconductor field effect transis
Its upper limit working frequency is increased substantially while low-noise performance and nominal power, and have higher operating voltage,
The advantages that higher power density and high temperature resistant, this causes GaN base device progressively to be taken in some power devices and high-frequency circuit
For original Si bases, GaAs base devices.
The preparation method of traditional notched gates normally-off GaN power device further grooves is an epitaxial growth AlGaN/GaN
Heterojunction structure, then the region two-dimensional electron gas in the case where keeping reducing grid in the case that access area two-dimensional electron gas is constant
Concentration, typically there are following methods：Plasma etching groove structure, the injection of F plasmas, addition p-type cap etc..But these
Method has all inevitably used plasma treatment technique.Plasma etching groove or injection processing are to region under grid
Caused by lattice damage, the leakage current of device can be increased, reduce gate control ability；And p-type block layered scheme then can be to access area
Lattice damage is caused, influences the stability of Two-dimensional electron gas channel and the reliability of device.It is compared to the above, selection region
Growth (SAG) method can avoid the damage that corona treatment is brought to device active layer, improve the interface matter of area of grid
Amount, improve the stability and reliability of device.But in selection region extension GaN slot grid structure field-effect transistors, device
Access area AlGaN/GaN heterojunction structures are formed by secondary epitaxy, and the quality of secondary epitaxy AlGaN/GaN heterojunction structures is straight
Connect the performance for determining device., it is necessary to covered with SiO before diauxic growth AlGaN/GaN epitaxial layers2The extension of mask layer
Piece carries out depth cleaning, and this to have the substrate of GaN channel layers to expose in atmosphere, and its surface has air oxidation and C, Si are miscellaneous
Matter stains.Meanwhile when using metallo-organic compound chemical gaseous phase deposition method diauxic growth AlGaN/GaN epitaxial layers,
Need to carry out Si substrates high-temperature process so as to realize the cleaning to Si substrates, but H is used only in temperature-rise period2As load
Gas, this Elevated Temperature Conditions can destroy GaN material surface, because GaN is in H2Easily decomposed under environment, its reaction equation is：
GaN and H2Reaction can produce Ga drops and ammonia in the case of a high temperature.Ga drops can cause secondary epitaxy to grow boundary
The out-of-flatness in face is so as to deteriorating secondary epitaxy AlGaN/GaN heterojunction structure quality.More seriously, selection region extension is covered
The preparation of film pattern needs to utilize plasma reinforced chemical vapour deposition method growth SiO in the substrate surface for having GaN channel layers2
Mask layer, the SiO of access area covering is then removed by the method for dry/wet etching2The wind of Si residuals be present in mask, the technique
Danger.The quality of secondary epitaxy heterojunction structure can be deteriorated by crossing polymictic introducing, reduce the two-dimensional electron gas of access area conducting channel
Concentration, it is unfavorable for the lifting of break-over of device performance.It is therefore desirable to seek a kind of normally-off GaN field-effect transistors access regional boundary
Face quality optimization method, to overcome the shortcomings that introducing defect impurity to device access area as caused by selective area growth method,
So as to obtain high performance normally-off GaN field-effect transistors.
The content of the invention
The present invention is to overcome at least one defect described in above-mentioned prior art, there is provided a kind of GaN of high-performance normally-off
Field-effect transistor and preparation method thereof, by the GaN channel layers in situ for etching access area, before secondary epitaxy layer is grown, subtract
The impurity such as Si, the C/O introduced in few mask preparation process at access area interface, and remove the mask residual and surface flaw of access area
Dirt, the access area diauxic growth interface quality of device is improved, keep access area raceway groove two-dimensional electron gas to be basically unchanged, so as to
Prepare a kind of high performance normally-off GaN field-effect transistors.
The technical scheme is that：A kind of GaN field-effect transistors of high-performance normally-off, wherein, including from it is lower toward
On include substrate successively, stress-buffer layer, GaN channel layers, grow secondary epitaxy after the GaN channel layers of original position etching access area
Layer, remove gate mask and form notched gates structure and one layer of gate dielectric layer is deposited on surface, device both ends remove gate dielectric layer simultaneously
Source electrode and drain electrode are formed, covered with grid on the gate dielectric layer in groove grids region.
Further, described substrate is in Sapphire Substrate, silicon carbide substrates, silicon substrate, gallium nitride self-supported substrate
It is any.
Described stress-buffer layer is any of AlGaN, GaN, AlN or combination；Stress-buffer layer thickness be 100nm~
10μm。
Described GaN channel layers for unintentional doping GaN channel layers or doping high resistant GaN channel layer, the doping
The doped chemical of resistive formation is carbon or iron；GaN channel layers thickness under recess region is 100nm~20 μm, compared to relatively connecing down
The GaN channel layers thickness entered under area reduces by 10~50nm.
Described secondary epitaxy layer is AlGaN/GaN hetero-junctions, AlGaN layer thickness is 10~50nm, wherein aluminium component
Varying concentrations, GaN layer thickness are 10~500nm.
Described notched gates structure is stained and grown secondary outer by the GaN channel layers removal surface in situ for etching access area
Prolong layer to be formed, U-shaped or trapezium structure is presented.The method effect of original position etching access area is that the GaN channel layers of access area exist
Mask residual when forming gate mask layer be present and impurity introduces, the GaN channel layers of original position etching access area can remove access area
Surface defect state, while the introducing of ambient impurities is reduced, obtain the secondary epitaxy interface of high quality.
Described gate dielectric layer is Al2O3Or Si3N4Compound, thickness are 10~100nm.
Described source electrode and drain material includes but is not limited to Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys, Ti/
Al/Mo/Au alloys or Ti/Al/Ti/TiN alloys, other various metal or alloy that can realize Ohmic contact can be used as source
Pole and drain material；Grid material includes but is not limited to Ni/Au alloys, Pt/Al alloys, Pd/Au alloys or TiN/Ti/Al/Ti/
TiN alloys, other can realize that the various metal or alloy of high threshold voltage can be used as grid material.
A kind of preparation method of the GaN field-effect transistors of high-performance normally-off, wherein：Comprise the following steps：
S1, in Grown stress-buffer layer；
S2, GaN channel layers are grown on stress-buffer layer；
S3, one layer of SiO is deposited on GaN channel layers2, as mask layer；
S4, by photoetching and combine dry or wet etch method, retain area of grid on mask layer；
S5, the GaN channel layers of etching access area in situ, etching depth is 10~50nm；
S6, selective area growth secondary epitaxy layer, form fluted body grid structure；
Mask layer on S7, removal area of grid；
S8, deposition form gate dielectric layer；
S9, dry etching complete the mesa-isolated of device, while etch source electrode and drain ohmic contact region；
S10, source electrode and drain metal on source electrode and drain region evaporation, and anneal by ohmic alloy to form ohm and connect
Touch；
S11, the area of grid evaporation gate metal on groove gate dielectric layer.
The secondary epitaxy layer in the GaN channel layers and step S6 in stress-buffer layer and step S2 in the step S1
Growing method is the high quality film formation methods such as Metalorganic Chemical Vapor Deposition, molecular beam epitaxy；Covered in the step S3
The growing method of film layer is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetic control
Sputtering method；Lithographic method in situ in the step S5 is dry etching, and etching gas environment is N2、NH3Any or group
Close；The growing method of gate dielectric layer in the step S8 is Low Pressure Chemical Vapor Deposition.
Compared with prior art, beneficial effect is：The present invention improves the quality at device access area diauxic growth interface, protects
Hold access area raceway groove two-dimensional electron gas to be basically unchanged, so as to improve the conduction property of device.Choosing of the present invention in routine
Select and a step is added in region growing method, before secondary epitaxy layer AlGaN/GaN heterojunction structures are grown, to without SiO2
The GaN channel layers of mask layer covering carry out etching in situ, by the SiO on access area2Mask remains and contained more C, Si alms giver
The interface of impurity removes, while reduces the ambient impurities of the introducing of the preparatory stage before secondary growth epitaxial layer, and then improves two
The quality of secondary extension heterojunction structure, keep access area raceway groove two-dimensional electron gas to be basically unchanged, obtain break-over of device performance
To lifting.Device architecture of the present invention is simple, and process repeatability and reliability are high, the interface high quality under retainer member area of grid
While, the quality at device access area interface is improved, high-performance normally-off GaN field effect transistors are prepared so as to provide one kind
The technology of tube device.
Brief description of the drawings
Fig. 1-11 is the device preparation method process schematic representation of the embodiment of the present invention 1.
Figure 12-14 is the process schematic representation for preparing mask layer on area of grid of the embodiment of the present invention 2.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；It is attached in order to more preferably illustrate the present embodiment
Scheme some parts to have omission, zoom in or out, do not represent the size of actual product；To those skilled in the art,
Some known features and its explanation may be omitted and will be understood by accompanying drawing.Being given for example only property of position relationship described in accompanying drawing
Explanation, it is impossible to be interpreted as the limitation to this patent.
Embodiment 1
It is the device architecture schematic diagram of the present embodiment as shown in figure 11, its structure includes substrate 1, stress successively from lower to upper
Cushion 2, GaN channel layers 3, original position grow secondary epitaxy layer 4 after etching the GaN channel layers 3 of access area, remove gate mask shape
One layer of gate dielectric layer 5 is deposited into notched gates structure and on surface, device both ends remove gate dielectric layer and form source electrode 6 and drain electrode 7, recessed
Covered with grid 8 on the gate dielectric layer of groove area of grid.
A kind of preparation method of above-mentioned high-performance normally-off GaN field-effect transistors as shown in Fig. 1-Figure 10, including with
Lower step：
S1, using mocvd method, a ply stress cushion 2 is grown on Si substrates 1, such as Fig. 1
It is shown；
S2, utilize mocvd method, the growth GaN channel layers 3 on stress-buffer layer 2, such as Fig. 2 institutes
Show；
S3, utilize one layer of SiO of plasma enhanced chemical vapor process deposition2, as mask layer 9, as shown in Figure 3；
S4, using photoetching association reaction coupled plasma etch method, retain the mask layer 9 on area of grid, such as
Shown in Fig. 4；
S5, using dry etching method in N2Etching in situ is carried out to access area in gaseous environment, as shown in Figure 5；
S6, using mocvd method, selective area growth is secondary outer on the substrate for having mask layer 9
Prolong AlGaN/GaN layers 4, form groove structure, as shown in Figure 6；
S7, using wet etching method, remove the mask layer 9 on area of grid, as shown in Figure 7；
S8, using low-pressure chemical vapor deposition method grow one layer of gate dielectric layer 5, as shown in Figure 8；
S9, using react coupled plasma etch complete device mesa-isolated, while etch source electrode and drain electrode Europe
Nurse contact area, as shown in Figure 9；
S10, Ti/Al/Ni/Au alloys are golden as source electrode 6 and the Ohmic contact of drain electrode 7 on source electrode and drain region evaporation
Category, and anneal to form Ohmic contact by ohmic alloy, as shown in Figure 10；
S11, Ni/Au alloys are deposited as the metal of grid 9 on the gate dielectric layer in groove grids region, as shown in figure 11.
So far, that is, the preparation process of whole device is completed.Figure 11 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
Figure 12-14 prepares SiO on area of grid for the embodiment of the present invention 22The process schematic representation of mask layer, itself and implementation
SiO on area of grid in example 12The preparation method of mask layer differs only in：Using reaction coupling plasma in embodiment 1
Body etches the mask pattern to be formed on area of grid, and embodiment 2 forms covering on area of grid using stripping means
Film pattern.Specific process comprises the following steps：
S1, the photoetching compound protective layer 10 for being partially formed in secondary epitaxy layer 3 patterned structures, as shown in figure 12；
S2, deposit one layer using plasma enhanced chemical vapor process on the substrate for having photoetching compound protective layer 10
SiO2, as mask layer 9, as shown in figure 13；
S3, using photoresist lift off liquid photoetching compound protective layer 10 is removed, while remove the mask layer 9 on protective layer, retained
Mask layer on area of grid so that mask layer is graphical, as shown in figure 14.
SiO on area of grid is prepared using stripping technology2Mask, can solve conventional lithography and corrosion work well
The problem of skill easily damages growth interface when making mask layer.But because before secondary epitaxy layer 4 is grown, GaN channel layers 3 are sudden and violent
In atmosphere, be present staining for air oxidation and C, Si impurity in its surface to dew, therefore still can not be solved completely using stripping technology
Certainly problem the defects of the interface of device access area, and the preparation method provided using this patent can then obtain higher-quality access
Area's secondary epitaxy growth interface.
Furthermore, it is necessary to explanation, the accompanying drawing of above example merely to the purpose of signal, therefore be not necessarily to by than
Example is drawn.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (10)
1. a kind of GaN field-effect transistors of high-performance normally-off, it is characterised in that including including substrate successively from lower to upper
（1）, stress-buffer layer（2）, GaN channel layers（3）, original position grows secondary epitaxy layer after etching the GaN channel layers of access area（4）,
Gate mask is removed to form notched gates structure and deposit one layer of gate dielectric layer on surface（5）, device both ends remove gate dielectric layer（5）
And form source electrode（6）And drain electrode（7）, the gate dielectric layer in groove grids region（5）On covered with grid（8）.
A kind of 2. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
Substrate（1）For any of Sapphire Substrate, silicon carbide substrates, silicon substrate, gallium nitride self-supported substrate.
A kind of 3. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
Stress-buffer layer（2）For any of AlGaN, GaN, AlN or combination；Stress-buffer layer thickness is 100nm ~ 10 μm.
A kind of 4. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
GaN channel layers（3）The high resistant GaN channel layer of GaN channel layers or doping for unintentional doping, the doping of the doping resistive formation
Element is carbon or iron；GaN channel layers thickness under recess region is 100nm ~ 20 μm, compared to the GaN ditches relatively descended under access area
Channel layer thickness reduces by 10 ~ 50nm.
A kind of 5. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
Secondary epitaxy layer（4）For AlGaN/GaN hetero-junctions, AlGaN layer thickness is 10 ~ 50nm, wherein aluminium component varying concentrations,
GaN layer thickness is 10 ~ 500nm.
A kind of 6. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
Notched gates structure passes through the GaN channel layers in situ for etching access area（3）Surface is removed to stain and grow secondary epitaxy layer（4）Carry out shape
Into the U-shaped or trapezium structure of presentation.
A kind of 7. GaN field-effect transistors of high-performance normally-off according to claim 6, it is characterised in that：Access area
GaN channel layers（3）Mask residual when forming gate mask layer be present and impurity introduces, the GaN ditches of original position etching access area
Channel layer（3）Access area surface defect state is can remove, while reduces the introducing of ambient impurities, obtains secondary epitaxy circle of high quality
Face.
A kind of 8. GaN field-effect transistors of high-performance normally-off according to claim 1, it is characterised in that：Described
Gate dielectric layer（5）For Al2O3Or Si3N4Compound, thickness are 10 ~ 100nm；
Described source electrode（6）And drain electrode（7）Material is Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys, Ti/Al/Mo/Au conjunctions
Gold or Ti/Al/Ti/TiN alloys；Grid（8）Material is Ni/Au alloys, Pt/Al alloys, Pd/Au alloys or TiN/Ti/Al/
Ti/TiN alloys.
A kind of 9. preparation method of the GaN field-effect transistors of high-performance normally-off described in claim 1, it is characterised in that：
Comprise the following steps：
S1, in substrate（1）Upper growth stress cushion（2）；
S2, in stress-buffer layer（2）Upper growth GaN channel layers（3）；
S3, in GaN channel layers（3）One layer of SiO of upper deposition2, as mask layer（9）；
S4, by photoetching and combine dry or wet etch method, retain area of grid on mask layer（9）；
S5, the GaN channel layers of etching access area in situ（3）, etching depth is 10 ~ 50nm；
S6, selective area growth secondary epitaxy layer（4）, form fluted body grid structure；
Mask layer on S7, removal area of grid（9）；
S8, deposition form gate dielectric layer（5）；
S9, dry etching complete the mesa-isolated of device, while etch source electrode and drain ohmic contact region；
S10, the source electrode on source electrode and drain region evaporation（6）And drain electrode（7）Metal, and anneal to form ohm by ohmic alloy
Contact；
S11, the area of grid evaporation grid on groove gate dielectric layer（8）Metal.
10. a kind of preparation method of the GaN field-effect transistors of high-performance normally-off according to claim 9, its feature
It is：Stress-buffer layer in the step S1（2）With the GaN channel layers in step S2（3）And the secondary epitaxy in step S6
Layer（4）Growing method be the high quality film formation method such as Metalorganic Chemical Vapor Deposition, molecular beam epitaxy；The step
Mask layer in S3（9）Growing method for plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vapour deposition (PVD)
Method or magnetron sputtering method；Lithographic method in situ in the step S5 is dry etching, and etching gas environment is N2、NH3Any
Kind or combination；The growing method of gate dielectric layer in the step S8 is Low Pressure Chemical Vapor Deposition.
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