CN104638010B - A kind of GaN normally-off MISFET devices laterally turned on and preparation method thereof - Google Patents
A kind of GaN normally-off MISFET devices laterally turned on and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of GaN normally-off MISFET devices laterally turned on, which includes substrate and grows epitaxial layer on substrate and grid, source electrode, drain electrode, insulating layer.The epitaxial layer includes the stress-buffer layer and GaN epitaxial layer of an epitaxial growth, and the secondary epitaxy layer of selective area growth thereon, the secondary epitaxy layer is contaminant filter layer from bottom to top, undoped epitaxial gan layers and heterostructure barriers layer, secondary epitaxy grows to form recess channel, the surface of recess channel and heterostructure barriers layer covers insulating layer, grid is covered at the recess channel on insulating layer, etching insulating layer both ends form source electrode and drain region, evaporation metal is formed and the source electrode of heterostructure barriers layer Ohmic contact and drain electrode at source electrode and drain region.Device architecture of the present invention is simple, process repeatability and reliability are high, diauxic growth interface impurity can effectively be inhibited to spread to secondary epitaxy layer, so as to effectively reduce the impurity scattering of 2DEG in the heterostructure-channel of diauxic growth, improve its mobility, device on-resistance is reduced, device is made to obtain High Output Current density and high on-off ratio.
Description
Technical field
The present invention relates to the technical field of semiconductor devices, more particularly, to a kind of GaN normally-off laterally turned on
MISFET devices and preparation method thereof.
Background technology
GaN semi-conducting materials have energy gap is big, breakdown electric field is high, saturated electron drift velocity is big and thermal conductivity is high etc.
Superior performance and there are high concentrations and the two-dimensional electron gas of high electron mobility in AlGaN/GaN heterojunction boundaries
（2DEG）, compared with Si materials, it is more suitable for preparing the power electronic devices of high-power high-capacity, high switching speed, becomes
The ideal substitute of next-generation device for power switching.
In the power electronic equipment based on Semiconductor Converting Technology, the power switch transistor of control unsteady flow process is all normal
(also known as enhanced) of pass type, this point are to ensure the basis of power electronics circuit " fail safe ".However, AlGaN/GaN is different
The two-dimensional electron gas for the high concentration that polarization field generates in matter knot, it is difficult by Schottky contacts to result in conducting channel in field-effect tube
The depletion region of formation blocks, and realizes that the normally-off GaN device for power switching that performance is stablized is still current International Technology circle and industry
The difficult point that boundary generally acknowledges.Current to make GaN base normally-off field-effect tube, mainly by the way of hetero-junctions, main method has：It is recessed
It is grown under grid structure, thin barrier layer construction, the injection of grid fluoride plasma, grid and grows p-type under InGaN layer, grid
AlGaN layer（Or p-type GaN layer）Deng.As mainstream technology recessed grid structure and grid fluoride plasma inject, due to wait from
Son etching and the mode of injection, inevitably cause the damage of material, so as to deteriorate the working performance of device and reliability.And
Other realization methods, there is also it is respective the shortcomings that etc..
Have relevant report and use selective area growth technology recent years（SAG）Realize laterally conducting GaN normally-off field
The process of effect transistor（Referring to document：Yuhua Wen, Zhiyuan He, Jialin Li, et al.
Enhancement-mode AlGaN/GaN heterostructure field effect transistors
fabricated by selective area growth technique. APPLIED PHYSICS LETTERS 98,
072108 (2011) and document Yao Yao, Zhiyuan He, Fan Yang, et al. Normally-off GaN
recessed-gate MOSFET fabricated by selective area growth technique. Applied
Physics Express 7, 016502 (2014)）.For designing preparation, laterally conducting GaN is often closed selective area growth technology
Type field-effect transistor avoids plasma etching or fluorine ion processing to lattice damage at recessed grid, improves device performance.It is secondary
The heterostructure-channel of epitaxial growth high quality is to ensure that device realizes the basis of low on state resistance and high switch ratio characteristic, is
One of key in this device preparation method and structure design.However in diauxic growth, often there are impurity element backgrounds
Doping.W. Lee such as Georgia Institute of Technology of the U.S. et al. are once reported in GaN diauxic growths interface, and there are the Si of high concentration is miscellaneous
Matter has a significant impact to heterostructure-channel 2DEG concentration and mobility（Referring to document：W. Lee, J.-H. Ryou, D.
Yoo, et al. Optimization of Fe doping at the regrowth interface of GaN for
applications to III-nitride-based heterostructure field-effect transistors.
APPLIED PHYSICS LETTERS 90, 093509(2007)）.Especially laterally conducting is prepared in selective area growth technology
In GaN normally-off field-effect transistors, the heterostructure-channel of diauxic growth（Conductive active layer）From diauxic growth interface very
Closely, easily polluted by diauxic growth interface background doped chemical, cause device performance degradation.
The content of the invention
The purpose of the present invention essentially consists in the property for improving the heterostructure-channel that secondary epitaxy is grown in prior art
Can, the mobility of heterostructure-channel 2DEG is improved, low on-resistance, High Output Current density, height can be realized by providing one kind
Horizontal conducting GaN normally-off MISFET devices of the superior performance of on-off ratio and preparation method thereof.
The present invention prepares laterally conducting normally-off GaN field-effect transistors using selective area growth method.Selection region is given birth to
It is long to generally require patterned mask layer to select to need the region grown, it is usually formed the key step bag of Patterned masking layer
It includes：One layer of SiO is first deposited on substrate GaN epitaxial layer2As mask layer, then by photoetching process in the SiO2Mask layer
On be formed with the photoetching compound protective layer of certain figure, then the SiO that will be exposed with etching process2Mask layer removes, Ran Houyou
Machine cleaning removal photoetching compound protective layer, the SiO finally retained in GaN epitaxial layer2I.e. patterned mask layer, in no mask layer
GaN epitaxial layer region（Diauxic growth interface）It can carry out the undoped GaN layer of diauxic growth and heterostructure barriers layer.But this
Problems with can be run into during kind masking process：SiO is removed using etching process2It is difficult by SiO during mask layer2Corrosion is clean,
A large amount of residuals are had at diauxic growth interface, when secondary epitaxy is grown, which easily spreads at high temperature
Into the heterostructure-channel of diauxic growth, raceway groove 2DEG is scattered seriously, causes being greatly lowered for 2DEG mobilities.
The production method of the present invention, one layer of contaminant filter layer is grown by secondary epitaxy, which can have first
Effect reduces the pollution for the heterostructure-channel that diauxic growth interface impurity is diffused up to secondary epitaxy growth, secondary epitaxy life
The hetero-junctions raceway groove of high quality is grown, so as to improve device performance.
In order to solve the above technical problems, the technical solution adopted by the present invention is：A kind of GaN normally-off laterally turned on
MISFET devices, structure include substrate, stress-buffer layer, GaN epitaxial layer, the impurity of secondary epitaxy growth successively from lower to upper
Filter layer and undoped GaN layer and heterostructure barriers layer, secondary epitaxy grow to form groove, recess channel and hetero-junctions structure
The exposed surface of barrier layer covers an insulating layer, and the both ends of heterostructure barriers layer are formed with source electrode and drain electrode, at recess channel
Covered with grid on insulating layer.
The groove is U-shaped or trapezoidal-structure.
The substrate is any one of Si substrates, Sapphire Substrate, silicon carbide substrates.
The stress-buffer layer is any of AlN, AlGaN, GaN or combination；Stress buffer layer thickness is 100 nm ~ 10
μ m。
The GaN epitaxial layer is the GaN epitaxial layer of unintentional doping or adulterates high resistant GaN epitaxial layer, the doping high resistant
The doped chemical of layer is carbon or iron；GaN epitaxial layer thickness is 100 nm ~ 5 μm.
The contaminant filter layer material is aluminiferous nitride, is included but not limited in AlGaN, AlInN, AlInGaN, AlN
One kind or arbitrary several combination, thickness be 1-500 nm, and aluminium concentration of component alterable.
The thickness of the undoped GaN layer is 10-500 nm；The heterostructure barriers layer material includes but not limited to
One kind or arbitrary several combination in AlGaN, AlInN, InGaN, AlInGaN, AlN, the heterostructure barriers layer thickness
For 5-50 nm.
One AlN layers is also grown between undoped GaN layer and heterostructure barriers layer, the AlN layer thickness is 1-10
nm。
The insulating layer material includes but not limited to SiO2、SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、
AlHfOxOr one kind in HfSiON or arbitrary several stacked combination, the thickness of insulating layer are 1-100 nm；
The source electrode and drain material include but not limited to Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys or Ti/Al/
Mo/Au alloys, other can realize that the various metal or alloy of Ohmic contact can be used as source electrode and drain material；The grid
Material includes but not limited to Ni/Au alloys, Pt/Al alloys or Pd/Au alloys, other can realize the various gold of high threshold voltage
Belong to or alloy can be used as grid material.
A kind of production method of the GaN normally-off MISFET devices laterally turned on, comprises the following steps：
S1, on a si substrate growth stress buffer layer；
S2, the growing high resistant GaN epitaxial layer on stress-buffer layer；
S3, one layer of SiO is deposited on high resistant GaN epitaxial layer2, as mask layer；
S4, the method by photoetching retain the mask layer formed on area of grid；
S5, selection region secondary epitaxy growth contaminant filter layer, undoped GaN layer and heterostructure barriers layer, form recessed
Slot grid；
Mask layer on S6, removal area of grid；
S7, in potential barrier of heterogenous junction layer and the insulating layer of groove site deposition grid；
S8, dry etching complete device isolation, while etch source electrode and drain ohmic contact region on the insulating layer；
S9, source electrode and drain ohmic contact metal on source electrode and drain region vapor deposition；
S10, gate metal is deposited in area of grid on groove insulating layer.
It is the contaminant filter layer in stress-buffer layer and GaN epitaxial layer and step S5 in step S1, S2, undoped
GaN layer and the growing method of heterostructure barriers layer are Metalorganic Chemical Vapor Deposition or molecular beam epitaxy；
The growing method of insulating layer is plasma enhanced chemical vapor in mask layer and step S7 in the step S3
Sedimentation, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method.
Compared with prior art, advantageous effect is：The present invention proposes a kind of GaN normally-off MISFET devices laterally turned on
Part and preparation method thereof, which uses secondary epitaxy growing technology, in a GaN epitaxial layer, secondary epitaxy growth impurity
Filter layer, undoped GaN layer and potential barrier of heterogenous junction layer, using contaminant filter layer to the barrier functionality of impurity, effectively stop two
Secondary growth interface impurity is spread under high growth temperature environment to secondary epitaxy layer, is dissipated so as to reduce 2DEG impurity in heterojunction structure
It penetrates, improves mobility, device is made to obtain low on-resistance, High Output Current density, high switch ratio characteristic.
Description of the drawings
Fig. 1-10 is the device manufacture method process schematic representation of the embodiment of the present invention 1；
Figure 11 is the device architecture schematic diagram of the embodiment of the present invention 2；
Figure 12 is experimental data figure of the thin layer AlGaN contaminant filters layer to Si Control of Impurities in GaN epitaxial structure.
Specific embodiment
Attached drawing is only for illustration, it is impossible to be interpreted as the limitation to this patent；It is attached in order to more preferably illustrate the present embodiment
Scheme some components to have omission, zoom in or out, do not represent the size of actual product；To those skilled in the art,
Some known features and its explanation may be omitted and will be understood by attached drawing.Being given for example only property of position relationship described in attached drawing
Explanation, it is impossible to be interpreted as the limitation to this patent.
This experimental group is existing to contaminant filter layer function in the correlative study work of Si substrate heteroepitaxial growths GaN to be tested
Card：In Figure 12（a）Curve is adds in the Si impurity concentrations after thin layer AlGaN contaminant filter layers in GaN epitaxial structure, Tu12Zhong
（b）Curve is the Si impurity concentrations in the epitaxial structure for remove the growth of thin layer gallium aluminium nitrogen impurity filter layer.Obviously, AlGaN is added in
After contaminant filter layer, Si impurity concentrations reduce an about magnitude water compared to free from admixture filter layer epitaxial structure in epitaxial structure
It is flat, illustrate that AlGaN contaminant filters layer can significantly inhibit Si elements and diffuse up into epitaxial structure.Contaminant filter layer function
It realizes mainly since its lattice constant is small compared with GaN layer, so as to limit the diffusivity of foreign atom.
Embodiment 1
It is the device architecture schematic diagram of the present embodiment as shown in Figure 10, structure includes substrate 1, stress successively from lower to upper
Buffer layer 2, GaN epitaxial layer 3, the contaminant filter layer 4 of secondary epitaxy growth and undoped GaN layer 5 and heterostructure barriers layer 6,
Secondary epitaxy grows to form groove, and recess channel and the exposed surface of heterostructure barriers layer 6 cover an insulating layer 7, hetero-junctions
The both ends of structure barrier layer 6 are formed with source electrode 8 and drain electrode 9, covered with grid 10 on the insulating layer 8 at recess channel.
The production method of the above-mentioned GaN normally-off MISFET devices laterally turned on is as shown in Fig. 1-Figure 10, including following step
Suddenly：
S1, using mocvd method, in Si substrates（1）One ply stress buffer layer of upper growth（2）, such as
Shown in Fig. 1；
S2, using mocvd method, in stress-buffer layer（2）Upper growing high resistant GaN epitaxial layer
（3）, as shown in Figure 2；
S3, one layer of SiO of plasma enhanced chemical vapor deposition is passed through2, as mask layer（11）, as shown in Figure 3；
S4, etched by photolithography method selection region, retain the mask layer on area of grid（11）, as shown in Figure 4；
S5, using mocvd method, having mask layer（11）Substrate on selection region it is secondary outer
Epitaxial growth contaminant filter layer（4）, undoped GaN layer（5）With heterostructure barriers layer（6）, groove grids are formed, as shown in Figure 5；
S6, using caustic solution, remove the mask layer on area of grid（11）, as shown in Figure 6；
S7, with plasma enhanced chemical vapor deposition method, in potential barrier of heterogenous junction layer（6）It sinks with groove grids region surface
One floor height K dielectric insulation layers of product（7）, as shown in Figure 7；
S8, device isolation is completed using ICP, while in potential barrier of heterogenous junction layer（6）On insulating layer（7）Both ends etch source
Pole and drain ohmic contact region, as shown in Figure 8；
S9, Ti/Al/Ni/Au alloys are deposited as source electrode in source electrode and drain region（8）And drain electrode（9）Ohm connect
Metal is touched, as shown in Figure 9；
S10, Ni/Au alloys are deposited on the insulating layer in groove grids region as grid（10）Metal, as shown in Figure 10.
So far, that is, the preparation process of entire device is completed.Figure 10 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
It is similar with 1 structure of embodiment if Figure 11 show the device architecture schematic diagram of the present embodiment, it differs only in
One layer of AlN layer 12 is inserted into undoped GaN layer 5 and heterostructure barriers layer 6, the AlN layers can improve at heterostructure-channel
2DEG mobilities.
Furthermore, it is necessary to explanation, the attached drawing of above example merely to the purpose of signal, therefore be not necessarily to by than
Example is drawn.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (8)
1. a kind of production method of the GaN normally-off MISFET devices laterally turned on, which is characterized in that described laterally to turn on
GaN normally-off MISFET devices include substrate successively from lower to upper（1）, stress-buffer layer（2）, GaN epitaxial layer（3）, it is secondary outer
The contaminant filter layer of epitaxial growth（4）And undoped GaN layer（5）With heterostructure barriers layer（6）, the GaN epitaxial layer（3）, two
The contaminant filter layer of secondary epitaxial growth（4）It contacts directly, secondary epitaxy grows to form groove, recess channel and heterostructure barriers
Layer（6）Exposed surface covers an insulating layer（7）, heterostructure barriers layer（6）Both ends be formed with source electrode（8）And drain electrode（9）,
Insulating layer at recess channel（7）On covered with grid（10）；
The production method of the GaN normally-off MISFET devices laterally turned on comprises the following steps：
S1, in Si substrates（1）Upper growth stress buffer layer（2）；
S2, the growing high resistant GaN epitaxial layer on stress-buffer layer（3）；
S3, one layer of SiO is deposited on high resistant GaN epitaxial layer2, as mask layer（11）；
S4, the method by photoetching retain the mask layer formed on area of grid（11）；
S5, selection region secondary epitaxy growth contaminant filter layer（4）, undoped GaN layer（5）With heterostructure barriers layer（6）, shape
Into groove grids；
Mask layer on S6, removal area of grid（11）；
S7, in heterostructure barriers layer and the insulating layer of groove site deposition grid（7）；
S8, dry etching complete device isolation, while in insulating layer（7）On etch source electrode and drain ohmic contact region；
S9, source electrode is deposited in source electrode and drain ohmic contact region（8）And drain electrode（9）Metal ohmic contact；
S10, grid is deposited in area of grid on groove insulating layer（10）Metal.
2. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The groove is U-shaped or trapezoidal-structure.
3. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The stress-buffer layer（2）For any of AlN, AlGaN, GaN or combination；Stress buffer layer thickness is 100 nm ~ 10
μm。
4. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The GaN epitaxial layer（3）For the GaN epitaxial layer of unintentional doping or doping high resistant GaN epitaxial layer, the doping high resistant
The doped chemical of GaN epitaxial layer is carbon or iron；GaN epitaxial layer thickness is 100 nm ~ 10 μm.
5. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The contaminant filter layer（4）Material is aluminiferous nitride, the aluminiferous nitride for AlGaN, AlInN, AlInGaN,
One kind in AlN or arbitrary several combination, thickness are 1-500 nm, and aluminium concentration of component alterable.
6. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The undoped GaN layer（5）Thickness be 10-500 nm；The heterostructure barriers layer（6）Material for AlGaN,
One kind or arbitrary several combination in AlInN, InGaN, AlInGaN, AlN, the heterostructure barriers layer（6）Thickness is 5-
50 nm；
In undoped GaN layer（5）With heterostructure barriers layer（6）Between also grow an AlN layers（12）, it is AlN layers described（12）It is thick
It spends for 1-10 nm.
7. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：The insulating layer（7）Material is SiO2、SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHfOxOr HfSiON,
The insulating layer（7）Thickness is 1-100 nm；Source electrode（8）And drain electrode（9）Material is Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au
Alloy or Ti/Al/Mo/Au alloys；Grid（10）Material is Ni/Au alloys, Pt/Al alloys or Pd/Au alloys.
8. a kind of production method of GaN normally-off MISFET devices laterally turned on according to claim 1, feature exist
In：Stress-buffer layer in step S1, S2（2）And GaN epitaxial layer（3）And the contaminant filter layer in step S5（4）, it is non-
Doped gan layer（5）With heterostructure barriers layer（6）Growing method be Metalorganic Chemical Vapor Deposition or molecular beam epitaxy
Method；
The growing method of insulating layer is plasma enhanced chemical vapor deposition in mask layer and step S7 in the step S3
Method, atomic layer deposition method, physical vaporous deposition.
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| CN105336789A (en) * | 2015-10-29 | 2016-02-17 | 中山大学 | GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor |
| WO2017166167A1 (en) * | 2016-03-31 | 2017-10-05 | 华为技术有限公司 | Field effect transistor and manufacturing method therefor |
| CN107706100B (en) * | 2017-10-30 | 2023-12-08 | 中山大学 | Graphical mask preparation and secondary growth interface optimization method for selective region epitaxy |
| CN107706241A (en) * | 2017-10-31 | 2018-02-16 | 中山大学 | A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof |
| CN107706232A (en) * | 2017-11-13 | 2018-02-16 | 江苏华功半导体有限公司 | A kind of MIS grid structure normally-off GaN base transistor in situ and preparation method |
| CN108054208B (en) * | 2017-12-19 | 2020-07-10 | 中国电子产品可靠性与环境试验研究所 | Transverse gallium nitride-based field effect transistor and manufacturing method thereof |
| CN111223933A (en) * | 2018-11-27 | 2020-06-02 | 北京大学 | Novel epitaxial layer structure for improving threshold voltage of GaN enhanced MOSFET |
| CN109873034A (en) * | 2019-03-22 | 2019-06-11 | 华南理工大学 | Normally-off HEMT power device of deposit polycrystalline AlN and preparation method thereof |
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| CN101477951A (en) * | 2009-01-13 | 2009-07-08 | 中山大学 | Enhanced AlGaN/GaN field effect tube and manufacturing method thereof |
| CN102184956A (en) * | 2011-04-15 | 2011-09-14 | 中山大学 | Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof |
| CN102368501A (en) * | 2011-10-20 | 2012-03-07 | 中山大学 | GaN based enhanced MOSHFET device and preparation method thereof |
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