CN106981514A - The enhanced GaN transistor device of notched gates based on nano-channel - Google Patents

The enhanced GaN transistor device of notched gates based on nano-channel Download PDF

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CN106981514A
CN106981514A CN201710380274.1A CN201710380274A CN106981514A CN 106981514 A CN106981514 A CN 106981514A CN 201710380274 A CN201710380274 A CN 201710380274A CN 106981514 A CN106981514 A CN 106981514A
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nano
channel
gan
algan
transistor device
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CN106981514B (en
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周幸叶
冯志红
吕元杰
谭鑫
王元刚
宋旭波
徐鹏
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CETC 13 Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788Vertical transistors
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Abstract

The invention discloses a kind of enhanced GaN transistor device of notched gates based on nano-channel, it is related to technical field of microelectronic devices, from bottom to top including substrate layer, GaN cushions, AlGaN potential barrier, gate dielectric layer, passivation layer, source electrode, drain electrode and gate electrode;Hetero-junctions below AlGaN/GaN HEMT devices gate electrodes is etched to form nano-channel, then two-dimensional electron gas is not present in nano-channel two side areas, gate electrode is wrapped in the top and two side of nano-channel, because gate electrode is modulated from three directions to the electronics in raceway groove, grid-control ability is strong, can suppress short channel effect well.When the width very little of nano-channel, the two-dimensional electron gas in raceway groove is depleted, and device is realized enhanced.Using notched gates structure, nano-channel and notched gates collective effect, it is ensured that device has larger nano-channel width while realizing enhanced reduce conducting resistance.

Description

The enhanced GaN transistor device of notched gates based on nano-channel
Technical field
The present invention relates to technical field of microelectronic devices, more particularly to a kind of notched gates based on nano-channel are enhanced GaN transistor device.
Background technology
Semiconductor material with wide forbidden band GaN have high critical breakdown electric field, high electron saturation velocities, good heat endurance with And the advantages of stronger capability of resistance to radiation, particularly AlGaN/GaN heterogeneous structure materials are imitated due to piezoelectricity and spontaneous polarization Should have high two-dimensional electron gas and electron mobility, it is considered to be prepare high temperature resistant, radioresistance, high-frequency high-power micro- The excellent material of wave power device and high speed, high voltage electric switch device and radioresistance high-speed digital circuit.
Due to the presence of polarity effect, AlGaN/GaN HEMTs are usually depletion device, prepare and increase Strong type device is relatively difficult, and progress is very slow.The application of depletion device has limitation.First, in radio-frequency power Application aspect, depletion device must use negative voltage bias grid, it is desirable to design independent power-supply system.Secondly, in electric power In terms of switch application, in order to ensure the overall security of system, depletion device also requires the operation of back bias voltage system prior to electricity Source is powered.In addition, in high-speed digital circuit application aspect, enhancement device is the indispensable element for constituting phase inverter, and phase inverter It is the core cell for constituting complex digital system.Therefore, develop the enhanced GaN transistor of high reliability have it is extremely important Meaning.
At present, a kind of Research Thinking in the world for enhanced GaN device is, by square grooving under the gate electrode, to make grid Raceway groove two-dimensional electron gas below pole exhausts, and raceway groove remainder two-dimensional electron gas is constant, so as to realize enhancement device. But, with the continuous diminution of device size, grid length is shorter and shorter, the HEMT of conventional planar structure it is short Ditch effect is more and more obvious.2013, Ki-Sik Im et al. prepared the enhanced AlGaN of single nano-channel/ GaNMISFET, threshold voltage is 2.1V, and the device architecture uses common grid structure, in order to realize enhancement device, nano-channel Width is only 50nm, and nano-channel two ends extend to source-drain electrode area, and therefore, device on-resistance is larger.
The content of the invention
The technical problem to be solved in the present invention is for above-mentioned the deficiencies in the prior art there is provided a kind of based on nano-channel The enhanced GaN transistor device of notched gates, the transistor has that grid-control ability is strong, can suppress short channel effect, realize device The characteristics of enhanced and conducting resistance is small.
In order to solve the above technical problems, the technical solution used in the present invention is:A kind of notched gates based on nano-channel Enhanced GaN transistor device, from bottom to top including substrate layer, GaN cushions, AlGaN potential barrier, gate dielectric layer, passivation layer, Source electrode, drain electrode and gate electrode;It is characterized in that:The AlGaN potential barrier and GaN cushions formation AlGaN/GaN Fluted above hetero-junctions, the AlGaN potential barrier, gate electrode is located in groove and is wrapped in AlGaN/GaN hetero-junctions Top and both sides, form three-dimensional gate-all-around structure;AlGaN/GaN hetero-junctions under the gate electrode has nano graph, and formation is received Rice raceway groove;The nano-channel two ends have raceway groove expansion area;The gate dielectric layer is located under the gate electrode, the source electricity Between pole and the drain electrode, two side walls of the nano-channel are covered at the top of the AlGaN/GaN hetero-junctions and wrapped up.
Preferably, the substrate layer is sapphire, SiC or GaN.
Preferably, the GaN buffer layer thicknesses are 0.5-2.5um.
Preferably, the AlGaN potential barrier thickness is 10-20nm, and wherein Al content is 15%-30%.
Preferably, the number n of the nano-channel is n >=1, length LchFor 0<Lch<The spacing of source electrode and drain electrode, Width WchFor 10-200nm.
Preferably, the bottom portion of groove in the AlGaN potential barrier and the AlGaN/GaN hetero-junctions apart from Dch1For 0- 15nm, the nano-channel bottom is with the AlGaN/GaN hetero-junctions apart from Dch2For 0-150nm.
Preferably, the gate dielectric layer is SiN, Al2O3、SiO2Or the stacked structure of medium layer, thickness is 1- 15nm。
Preferably, the passivation layer is SiN, Al2O3、SiO2Or the stacked structure of a variety of passivation layers, thickness is 50- 150nm。
Preferably, the gate electrode is straight grid or T-shaped grid, grid length Lg=LchOr Lg>LchOr Lg<Lch
Preferably, the source electrode and electric leakage extremely Ohmic contact, on the raceway groove expansion area at nano-channel two ends.
It is using the beneficial effect produced by above-mentioned technical proposal:By AlGaN/GaN HEMT devices Hetero-junctions below part gate electrode etches to form nano-channel, then two-dimensional electron gas, grid electricity is not present in nano-channel two side areas Pole is wrapped in the top and two side of nano-channel, because gate electrode is modulated from three directions to the electronics in raceway groove, grid Control ability is stronger, can suppress short channel effect well.When the width very little of nano-channel, the two-dimensional electron gas quilt in raceway groove Exhaust, device is realized enhanced.Using notched gates structure, nano-channel and notched gates collective effect, it is ensured that device is in reality There is larger nano-channel width while existing enhanced, reduce conducting resistance.Nano-channel two ends have expansion area, can enter One step reduces conducting resistance, improves device frequency.
Brief description of the drawings
Fig. 1 is the integrally-built top view of the embodiment of the present invention one.
Fig. 2 is the sectional view in Figure 1A-A faces.
Fig. 3 is the sectional view in Figure 1B-B faces.
Fig. 4 is the sectional view in Fig. 1 C-C faces.
Fig. 5 is the integrally-built top view of the embodiment of the present invention two.
Fig. 6 is the integrally-built top view of the embodiment of the present invention three.
Fig. 7 is the integrally-built sectional view of the embodiment of the present invention four.
In figure:1st, source electrode;2nd, drain electrode;3rd, gate electrode;4th, raceway groove expansion area;5th, nano-channel;6th, substrate layer;7、 GaN cushions;8th, AlGaN potential barrier;9th, gate dielectric layer;10th, passivation layer.
Embodiment
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
As shown in Figure 1, Figure 2, Figure 3 and Figure 4, device of the present invention include substrate layer 6, GaN cushions 7, AlGaN potential barrier 8, Gate dielectric layer 9, passivation layer 10, source electrode 1, drain electrode 2 and gate electrode 3.Wherein orlop is using sapphire, SiC or GaN Substrate layer 6;Substrate layer 6 is above GaN cushions 7;It is AlGaN potential barrier 8 above cushion;AlGaN potential barrier 8 and GaN are slow The formation AlGaN/GaN hetero-junctions of layer 7 is rushed, the top of AlGaN potential barrier 8 is fluted, and gate electrode 3 is located in groove, and is wrapped in different The top and both sides of matter knot, form three-dimensional gate-all-around structure;AlGaN/GaN hetero-junctions under gate electrode 3 has nano graph, is formed Nano-channel 5;The two ends of nano-channel 5 have raceway groove expansion area 4;Gate dielectric layer 9 be located at AlGaN potential barrier 8 and gate electrode 3 it Between, it is covered at the top of AlGaN/GaN hetero-junctions and wraps up two side walls of nano-channel 5;Source electrode 1 and the difference of drain electrode 2 position On the expansion area 4 of nano-channel 5;Passivation layer 10 is covered in the surface of whole device.
With reference to the accompanying drawings, the present invention is described in further detail in conjunction with specific embodiments.
Embodiment one:The enhanced GaN transistor device of notched gates based on single nano-channel.
Fig. 1 is the integrally-built top view of the embodiment of the present invention one, and Fig. 2, Fig. 3 and Fig. 4 are A-A faces, B-B in Fig. 1 respectively Face and the sectional view in C-C faces.The enhanced GaN transistor device of notched gates of the present embodiment based on single nano-channel 5 is from bottom to top Including substrate layer 6, GaN cushions 7, AlGaN potential barrier 8, gate dielectric layer 9, passivation layer 10 and source electrode 1, drain electrode 2 and grid electricity Pole 3.
Substrate layer 6 is sapphire, SiC or GaN using material.
Substrate layer 6 is the GaN cushions 7 that thickness is 0.5-2.5 μm above.
It is that thickness is the AlGaN potential barrier 8 that 10-20nm and Al components are 15%~30% above cushion.
AlGaN potential barrier 8 and the formation AlGaN/GaN hetero-junctions of GaN cushions 7, fluted, the grid in the top of AlGaN potential barrier 8 Electrode 3 is located in groove, and is wrapped in the top and both sides of hetero-junctions, forms three-dimensional gate-all-around structure.Wherein described grid recess bottom Portion is with AlGaN/GaN hetero-junctions apart from Dch1For 0-15nm.
AlGaN/GaN hetero-junctions under gate electrode 3 has nano graph, nano-channel 5 is formed, wherein the nano-channel 5 number n is n=1, length LchFor LchThe length L of=gate electrode 3g;The width W of nano-channel 5chFor 10-200nm, the bottom of nano-channel 5 Portion is with AlGaN/GaN hetero-junctions apart from Dch2For 0-150nm.
The two ends of nano-channel 5 have raceway groove expansion area 4.
Gate dielectric layer 9 is located between AlGaN potential barrier 8 and gate electrode 3, is covered at the top of AlGaN/GaN hetero-junctions and wraps Two side walls of nano-channel 5 are wrapped up in, gate dielectric layer 9 uses SiN, Al2O3、SiO2Or the stacked structure of medium layer, thickness is 1-15nm。
Passivation layer 10 is located at the surface of the whole device in addition to electrode, and passivation layer 10 uses SiN, Al2O3、SiO2Or it is a variety of The stacked structure of passivation layer 10, thickness is 50-150nm.
Source electrode 1 and drain electrode 2 are Ohmic contact, on the raceway groove expansion area 4 at the two ends of nano-channel 5.
Embodiment two:The enhanced GaN transistor device of notched gates based on single nano-channel.
As shown in figure 5, the enhanced GaN transistor device of the notched gates based on single nano-channel 5 of the present embodiment have with The identical structure of embodiment one, but the length L of the nano-channel 5chFor Lch>The long L of gridg
Embodiment three:The enhanced GaN transistor device of notched gates based on many nano-channels.
As shown in fig. 6, the enhanced GaN transistor device of the notched gates based on many nano-channels of the present embodiment has and reality The identical structure of example one is applied, but the number n of the nano-channel 5 is n>1.
Example IV:The enhanced GaN transistor device of T-shaped notched gates based on single nano-channel.
As shown in fig. 7, the enhanced GaN transistor device of the T-shaped notched gates based on single nano-channel 5 of the present embodiment has With the identical structure of embodiment one, but gate electrode 3 use T-shaped grid structure.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention Any modifications, equivalent substitutions and improvements made within refreshing and principle etc., should be included in the scope of the protection.

Claims (10)

1. the enhanced GaN transistor device of a kind of notched gates based on nano-channel, from bottom to top including substrate layer(6), GaN delay Rush layer(7), AlGaN potential barrier(8), gate dielectric layer(9), passivation layer(10), source electrode(1), drain electrode(2)And gate electrode(3); It is characterized in that:The AlGaN potential barrier(8)With the GaN cushions(7)Form AlGaN/GaN hetero-junctions, the AlGaN Barrier layer(8)Top is fluted, gate electrode(3)In groove and it is wrapped in the top and both sides of AlGaN/GaN hetero-junctions, Form three-dimensional gate-all-around structure;The gate electrode(3)Under AlGaN/GaN hetero-junctions there is nano graph, form nano-channel (5);The nano-channel(5)Two ends have raceway groove expansion area(4);The gate dielectric layer(9)Positioned at the gate electrode(3)It Under, the source electrode(1)With the drain electrode(2)Between, it is covered at the top of the AlGaN/GaN hetero-junctions and is received described in parcel Rice raceway groove(5)Two side walls.
2. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The substrate layer(6)For sapphire, SiC or GaN.
3. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The GaN cushions(7)Thickness is 0.5-2.5um.
4. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The AlGaN potential barrier(8)Thickness is 10-20nm, and wherein Al content is 15%-30%.
5. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The nano-channel(5)Number n be n >=1, length LchFor 0<Lch<Source electrode(1)And drain electrode(2)Spacing, width Wch For 10-200nm.
6. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The AlGaN potential barrier(8)On bottom portion of groove and the AlGaN/GaN hetero-junctions apart from Dch1For 0-15nm, the nanometer Raceway groove(5)Bottom is with the AlGaN/GaN hetero-junctions apart from Dch2For 0-150nm.
7. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The gate dielectric layer(9)For SiN, Al2O3、SiO2Or the stacked structure of medium layer, thickness is 1-15nm.
8. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The passivation layer(10)For SiN, Al2O3、SiO2Or a variety of passivation layers(10)Stacked structure, thickness is 50-150nm.
9. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The gate electrode(3)For straight grid or T-shaped grid, grid length Lg=LchOr Lg>LchOr Lg<Lch
10. the enhanced GaN transistor device of the notched gates according to claim 1 based on nano-channel, it is characterised in that: The source electrode(1)And drain electrode(2)For Ohmic contact, positioned at nano-channel(5)The raceway groove expansion area at two ends(4)On.
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CN107919397A (en) * 2017-11-20 2018-04-17 西安电子科技大学 A kind of High Linear FET device and preparation method thereof
CN108470768A (en) * 2018-03-02 2018-08-31 华南理工大学 A kind of preparation method of HEMT device nanometer gate
CN108666216A (en) * 2018-05-15 2018-10-16 西安电子科技大学 HEMT device and preparation method thereof based on overlayer passivation structure
US11349003B2 (en) * 2019-05-15 2022-05-31 Cambridge Electronics, Inc. Transistor structure with a stress layer
CN114843187A (en) * 2021-02-02 2022-08-02 北京大学 Preparation method of GaN-based multi-nano-channel high-electron-mobility transistor

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JP2009049288A (en) * 2007-08-22 2009-03-05 Nec Corp Semiconductor device
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Publication number Priority date Publication date Assignee Title
CN107919397A (en) * 2017-11-20 2018-04-17 西安电子科技大学 A kind of High Linear FET device and preparation method thereof
CN108470768A (en) * 2018-03-02 2018-08-31 华南理工大学 A kind of preparation method of HEMT device nanometer gate
CN108666216A (en) * 2018-05-15 2018-10-16 西安电子科技大学 HEMT device and preparation method thereof based on overlayer passivation structure
CN108666216B (en) * 2018-05-15 2021-05-07 西安电子科技大学 HEMT device based on laminated passivation structure and preparation method thereof
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CN114843187A (en) * 2021-02-02 2022-08-02 北京大学 Preparation method of GaN-based multi-nano-channel high-electron-mobility transistor
CN114843187B (en) * 2021-02-02 2024-05-17 北京大学 Preparation method of GaN-based nano-channel high electron mobility transistor

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