CN110148626A - Polarization doping InN base tunneling field-effect transistor and preparation method thereof - Google Patents
Polarization doping InN base tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- CN110148626A CN110148626A CN201910095373.4A CN201910095373A CN110148626A CN 110148626 A CN110148626 A CN 110148626A CN 201910095373 A CN201910095373 A CN 201910095373A CN 110148626 A CN110148626 A CN 110148626A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Abstract
The invention discloses a kind of polarization to adulterate InN base tunneling field-effect transistor, and mainly solving Random Dopant Fluctuation caused by conventional physical doping techniques causes device performance to decline, complex manufacturing technology, the low problem of reliability.It includes: substrate (1), buffer layer (2) He Tiqu (3) from bottom to top, the upper right quarter in body area is equipped with polarization inversion layer (4), dielectric layer (8) are deposited on the top in body area, the left side of polarization inversion layer and top, dielectric layer left side is etched with grid step (9), dielectric layer top right-to-left is successively deposited with modulation panel (10), grid (11) and tunnelling grid (12), body area two sides are etched with get out of a predicament or an embarrassing situation (5), and the left and right upper lateral part of the step is respectively equipped with source electrode (7) and drain electrode (6).The invention avoids the annealing process in conventional physical doping techniques, improves the output electric current of device and subthreshold swing and inhibit reverse leakage, improve device reliability, can be used for low consumption circuit system.
Description
Technical field
The invention belongs to technical field of semiconductor device, in particular to a kind of tunneling field-effect pipe can be used for low-power consumption electricity
Road system.
Technical background
With technique progress, the transistor feature size of the silicon area and diminution that constantly increase makes ultra-large integrated electricity
Road technique is developed rapidly, and the manufacturing cost of single transistor is thus promoted to gradually decrease the electrology characteristic with entire chip
It is lasting to improve.Currently, CMOS technology technology oneself enter the 14nm epoch, and also continue it is miniature, towards 7nm and its following
Technology node constantly promotes.Nowadays, billions of a devices can have been integrated on one single chip, however, as transistor size is miniature
Into nanometer scale, the problems such as short-channel effect, is got worse, and is especially increased sharply with number of devices on unit area and is caused function
Consumption increased dramatically, therefore power consumption becomes the important limitation and very important factor of IC design, referring to COLOMBO D
M, WIRTH G I, FAYOMI C.Design methodology using inversion coefficient for low-
voltage low-power CMOS voltage reference[C],Proceeding of the Conference on
Integrated Circuits and System Design.Sao Paulo,Brazil,2010:43-48.On the one hand, Gao Gong
Consumption will be such that chip interior temperature rises, so that the failure rate of increasing circuit system, increases 10 DEG C some researches show that operating temperature is every
It will lead to the high temperature that the crash rate of system is doubled, and more seriously generated to be possible to burn monolith chip, this pole
The earth affects the performances such as reliability and the stability of chip, referring to FENG W C.Making a case foe
Efficient supercomputing [M] .New York:ACM, 2003:54-64；On the other hand, the encapsulation and power consumption of chip
Closely related, high power consumption increases the cost of encapsulation and heat dissipation, and high power consumption also implies that chip will expend more electric energy,
Reduce the continuous working period and service life of various electronic equipments.Instantly, energy-saving and emission-reduction have become industry and know together, and low-power consumption
Technology will make associated electronic device have the features such as certain environmental protection, energy conservation, and more valuable is that will make to produce using Low-power Technology
Moral character can be promoted significantly, effectively enhanced its technical advantage and improved the market competitiveness, so, low energy-consumption electronic device, which becomes, works as
The Research Emphasis of modern integrated circuit fields, referring to Tao Guilong, progress [J] of the tunneling field-effect transistor such as Gao Bo is micro- perhaps
Nanoelectronic Technology .2018, Vol.55:707.
In the application of nano electron device, the pursuit to device low-power consumption is always to push field effect transistor Manifold technology wound
New catalyst, wherein tunneling field-effect transistor TFETs receives extensive pass as a kind of alternative device having boundless prospects
Note.Compared with conventional metals Oxide Semiconductor Field Effect Transistors MOSFET, the advantage of tunneling field-effect transistor is subthreshold
The value amplitude of oscillation is smaller than 60mV/decade, and off-state leakage current is lower, and short-channel effect can be effectively suppressed, referring to
K.K.Young,“Short-channel effect in fully depleted SOI MOSFETs,”IEEE
Trans.Electron Devices,vol.36,no.2,pp.399–402,Feb.1989。
Up to the present, a large amount of research work has been had been put into the development of TFETs, and has achieved good progress.
In recent years, since channel material electron effective mass is small, band gap is moderate, the tunnel based on III group nitride material such as InN, InGaN
It wears field effect transistor and receives extensive research and concern.Compared with traditional silicon substrate tunneling field-effect transistor, it is based on III
The performance of the tunneling field-effect transistor of group nitride material has significant raising.However, being imitated with traditional silicon substrate tunnelling field
Answer transistor similarly, the tunneling field-effect transistor for being mostly based on III group nitride material at present is still based on traditional object
Manage doping techniques.
Fig. 1 is a kind of tunneling field-effect transistor of traditional III nitride base based on physical doping, comprising: body area 1,
Source region 2, drain region 3, dielectric layer 4 are deposited with grid 5 on 4 top of dielectric layer, are deposited on drain region 3 drain electrode 6, form sediment in source region 2
Product source 7, in which: body area 1 uses the InN semiconductor material of [0001] crystal orientation；Source region 2 is located at 1 left side of body area, passes through p-type
Doping is formed, and doping concentration is 1 × 1018~1 × 1020cm-3, drain region 3 is located at 1 right side of body area, is formed, adulterated by n-type doping
Concentration is 1 × 1017~1 × 1019cm-3, dielectric layer 4 is located at 1 top of body area, and width and body area 1 are of same size, can be by SiO2
Or SiN or Al2O3Or HfO2Or TiO2Insulating dielectric materials are constituted, and thickness a is 1~20nm；The width and dielectric layer 4 of grid 5
It is identical.The device of this structure can encounter the silicon substrate tunnelling field with conventional physical doping due to using conventional physical doping techniques
The identical problem of effect transistor, expensive annealing technology subsidiary with its such as the intrinsic high cost of ion implantation technology, and
The problem of Random Dopant Fluctuation RDFs, the reduced performance of caused device, process complexity increase, and device reliability reduces.
Summary of the invention
It is an object of the invention to be directed to the deficiency of above-mentioned prior art, a kind of polarization doping InN Ji Suichuanchang effect is provided
Answer transistor and preparation method thereof, to avoid Random Dopant Fluctuation in conventional physical doping techniques to the decaying of device performance and
The annealing process of complex and expensive reduces the manufacture difficulty of device, is effectively improved the output electric current of device and subthreshold swing and presses down
The reverse leakage of device processed improves the reliability of device.
To achieve the above object, the technical scheme of the present invention is realized as follows:
One, device architecture
A kind of polarization doping InN base tunneling field-effect transistor, comprising: body area 3, drain electrode 6, source electrode 7, grid 11, feature
It is:
It is successively arranged buffer layer 2 and substrate 1 below the body area 3, which uses unintentional the mixing of [0001] crystal orientation
Miscellaneous GaN semiconductor material；
The upper right quarter in the body area 3 is deposited with polarization inversion layer 4, uses the unintentional doping of [0001] crystal orientation
InxGa1-xN semiconductor material, width f are 10~100nm, and the thickness h of polarization inversion layer (4) is approximate with In component x to meet relationship
Formula:
The two sides in the body area 3, which are etched with, gets out of a predicament or an embarrassing situation 5, and drain electrode 6 is located at the top of right side step 5, and thickness is greater than body area 3
With the sum of the thickness of polarization inversion layer 4；Source electrode 7 is located at the top of left side step 5, and thickness is greater than the thickness in body area 3；
The top in the body area 3 and the left side of polarization inversion layer 4 and top are deposited with dielectric layer 8；The left side of the dielectric layer 8
It is etched with grid step 9, top right-to-left is successively deposited with modulation panel 10 and tunnelling grid 12, and grid 11 is located at modulation panel 10 and tunnel
It wears between grid 12.
Preferably, the grid 11, width c is less than the width of modulation panel 10, and width b is 6~70nm.
Preferably, the drain electrode 6, uses the work function of metal will be lower than metal work function used by deposit grid 11
Number.
Preferably, the source electrode 7, uses the work function of metal to be higher than metal work function used by deposit grid 11
Number.
Preferably, the modulation panel 10, overlapping width is less than the width f of polarization inversion layer 4 with polarization inversion layer 4
It is higher than metal work function used by deposit grid 11 with the work function of the width b of modulation panel 10, and use metal.
Preferably, the dielectric layer 8, using SiO2Or SiN or Al2O3Or HfO2Or TiO2Insulating dielectric materials,
The thickness a on 3 top of body area, 4 left side of polarization inversion layer and polarization 4 these regions of top of inversion layer is equal, and is filled up completely body
Area 3, polarization inversion layer 4, grid 11, the region between modulation panel 10, thickness a are 1~20nm.
Preferably, the grid step 9, depth e is less than the thickness a of dielectric layer 8, and width d is less than modulation panel
The 10 width b and width c of grid 11.
Preferably, the tunnelling grid 12, width is identical as grid step 9, and lower part is located above grid step 9, and thickness
It is less than or equal to metal work function used by deposit grid 11 greater than the depth of grid step 9, and using the work function of metal, and
Tunnelling grid 12, modulation panel 10 and grid 11 are successively electrically connected.
Two, production method
The method that the present invention makes source ladder field plate vertical-type power transistor, comprises the following processes:
A. on substrate 1 the unintentional doping of extension [0001] crystal orientation GaN semiconductor material, formed with a thickness of 500~
The buffer layer 2 of 1000nm；
B. the InN semiconductor material of the unintentional doping of extension [0001] crystal orientation on the buffer layer 2, formed with a thickness of 10~
The body area 3 of 30nm；
C. polarization inversion layer 4 is made:
C1) in body area 3 the unintentional doping of extension [0001] crystal orientation InxGa1-xN semiconductor material, width f are
10~100nm, the thickness h of polarization inversion layer (4) is approximate with In component x to meet relational expression:
C2) in C1) In of extensionxGa1-xMask is made for the first time on N semiconductor material, using the mask in the left and right sides
Etching forms and gets out of a predicament or an embarrassing situation 5, and is etched to the stopping of 2 top of buffer layer；
C3) 2 top of buffer layer in the covering of the area Wei Beiti 3 and InxGa1-xSecond of production mask on N semiconductor material,
Utilize the In in mask etching removal left sidexGa1-xN semiconductor material forms polarization inversion layer 4,
D. two sides get out of a predicament or an embarrassing situation 5 and polarization inversion layer 4 top third time production mask, using the mask right side leave office
5 top of rank deposits metal, forms drain electrode 6；
E. 5 are got out of a predicament or an embarrassing situation in left side, polarization inversion layer 4 and drain 6 the production mask of top the 4th time, using the mask on a left side
Side get out of a predicament or an embarrassing situation 5 tops deposit metal, formed source electrode 7；
F. dielectric layer 8 is made:
F1 insulating dielectric materials, covering source electrode 7, body area 3, polarization inversion layer 4 and drain electrode) are deposited using conformal covering process
6；
F2) in F1) deposit insulating dielectric materials on the 5th production mask, utilize the mask etching removal left side and the right side
The insulating dielectric materials of side section, form dielectric layer 8, which covers body area 3 and the polarization inversion layer 4 of part, and its
Thickness a positioned at 3 top of body area, 4 left side of polarization inversion layer and top is equal, and thickness a is 1~20nm；
G. the 6th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, utilizes the exposure mask
Etching forms the thickness that etching depth is less than dielectric layer 8 on the left of dielectric layer 8, and width is less than the width of modulation panel 10 and grid 11
The grid step 9 of degree；
H. the 7th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, utilizes the exposure mask
Modulation panel 10 is formed in 8 right upper portion of dielectric layer deposit metal, 10 width b of the modulation panel is 6~70nm.The modulation panel 10 and pole
Change the overlapping width of inversion layer 4 and is less than the width of polarization inversion layer 4 and the width of modulation panel 10, and 10 left side of modulation panel and pole
The horizontal space for changing 4 left side of inversion layer is identical as the thickness of dielectric layer 8；
I. selection metal work function is greater than drain electrode 6 and is less than the metal of 10 metal work function of source electrode 7 and modulation panel, in source electrode
7, body area 3, dielectric layer 8, modulation panel 10, polarization inversion layer 4, drain electrode 6 on the 8th production exposure mask, using the exposure mask in modulation panel
8 top of dielectric layer between 9 right side of 10 left sides and grid step deposits the metal and forms grid 11；
J. selection metal work function is less than or equal to the metal of the metal work function of grid 11, in source electrode 7, body area 3, medium
Layer 8, grid 11, modulation panel 10, polarization inversion layer 4, drain electrode 6 on the 9th production exposure mask, formed sediment on grid step 9 using the exposure mask
The product metal forms the tunnelling grid 12 that thickness is greater than the depth of grid step 9, realizes tunnelling grid 12, modulation panel 10, grid 11 3
Electrical connection between person, the production of complete cost device.
Device of the present invention has compared with the tunneling field-effect transistor of traditional III nitride base based on physical doping
Following advantages:
1. avoiding the influence of Random Dopant Fluctuation using polarization doping.
Device of the present invention is according to polar theory, the In formed using polarization inversion layer 4 and body area 3xGa1-xN, InN hetero-junctions
Electron adulterated, the source region that InN, GaN hetero-junctions of combination area 3 and the formation of buffer layer 2 are realized of the drain region of realization
Hole doping, realize the polarization doping of device, avoid the tunnelling field of traditional III nitride base based on physical doping
Random Dopant Fluctuation present in effect transistor influences, and makes the tunnel of traditional III nitride base based on physical doping
Ion implanting needed for wearing during field effect transistor and high-temperature annealing process, significantly reduce device manufacture difficulty and at
This.
2. the present invention effectively reduces drain electrode and connects using the drain electrode 6 with a thickness of the sum of body area 3 and polarization 4 thickness of inversion layer
Electric shock resistance, increases the output electric current of device.
3. the present invention using on dielectric layer 8 right-to-left successively deposit metal work function modulation panel 10 from big to small,
The mode of grid 11, tunnelling grid 12 significantly improves grid 11 to the modulating action of device channel energy band and electric field, increases device
The output electric current of part, reduces the subthreshold swing of device, and effectively inhibits the reverse leakage of device, and that improves device can
By property.
Technology contents and effect of the invention are further illustrated below in conjunction with drawings and examples.
Detailed description of the invention
Fig. 1 is the structure chart of the tunneling field-effect transistor of traditional III nitride base based on physical doping；
Fig. 2 is the structure chart of present invention polarization doping InN base tunneling field-effect transistor；
Fig. 3 is the flow diagram of present invention production polarization doping InN base tunneling field-effect transistor；
Fig. 4 is the sub-process figure of production polarization inversion layer in the present invention；
Fig. 5 is the sub-process figure that dielectric layer is made in the present invention；
Fig. 6 is to the electron concentration and hole concentration distribution map obtained by device simulation of the present invention in the state of the equilibrium；
Fig. 7 is to dense along the polarization charge of device left side edge, hole in the state of the equilibrium obtained by device simulation of the present invention
Spend distribution map；
Fig. 8 is to the polarization charge along device right side edge, carrier in the state of the equilibrium obtained by device simulation of the present invention
Concentration profile；
Fig. 9 is that the tunneling field-effect transistor of III nitride base to tradition based on physical doping and device of the present invention are imitated
True gained transfer characteristic compares figure.
Specific embodiment
Referring to Fig. 2, InN base tunneling field-effect transistor is adulterated in polarization of the invention, from bottom to top includes: substrate 1, buffering
Floor 2, body area 3, in which: sapphire or silicon carbide or GaN material can be used in substrate 1；Buffer layer 2 uses the non-event of [0001] crystal orientation
The GaN semiconductor material of meaning doping, with a thickness of 500~1000nm；Body area 3 uses the unintentional doping of [0001] crystal orientation
InN semiconductor material, with a thickness of 10~30nm.
The upper right quarter in body area 3 is equipped with polarization inversion layer 4, which uses the unintentional doping of [0001] crystal orientation
InxGa1-xN semiconductor material, width f are 10~100nm, and the thickness h of polarization inversion layer (4) satisfaction approximate with In component x is closed
It is formula:
It is deposited with dielectric layer 8 on the top in body area 3, the left side of polarization inversion layer 4 and top, the dielectric layer 8 is by SiO2Or
SiN or Al2O3Or HfO2Or TiO2Insulating dielectric materials are constituted, and thickness a is 1~20nm, and are located at 3 top of body area, polarization instead
The thickness a in 4 left side of type layer and these regions of top is equal.Grid step 9 is etched on the left of dielectric layer 8, depth e is less than medium
The thickness a of layer 8,8 top right-to-left of dielectric layer are successively deposited with modulation panel 10, grid 11 and tunnelling grid 12, in which: modulation panel
10 width b is 15nm~50nm, and work function is higher than 11 metal work function of grid；The width c of metal gates 11 is less than modulation
The width b of plate 10；The width of tunnelling grid 12 is equal to the width d of grid step 9, and is less than the width b and grid 11 of modulation panel 10
Width c, the thickness of the tunnelling grid are greater than the depth of grid step 9, and are less than or equal to the metal of grid 11 using work function；Modulation
The width that plate 10 and polarization inversion layer 4 overlap is less than the width f of polarization inversion layer 4 and the width b of modulation panel 10；Tunnelling grid 12 with
Modulation panel 10 and grid 11 are successively electrically connected.Body area 3, polarization inversion layer 4, grid 11, the region between modulation panel 10 are situated between
Matter layer 8 is filled up completely.
3 two sides of body area, which are etched with, gets out of a predicament or an embarrassing situation 5, and the right upper portion of step 5 is equipped with drain electrode 6, and the thickness of the drain electrode 6 is greater than body area
3 with polarization inversion layer 4 the sum of thickness, use work function be lower than 11 work function of grid metal；The left upper portion of step 5 is set
Source 7, thickness are greater than the thickness in body area 3, and the metal of 11 metal work function of grid is higher than using work function.
Referring to Fig. 3, the method that the present invention makes polarization doping InN base tunneling field-effect transistor provides following three kinds of realities
Apply example.
Embodiment one: a kind of polarization doping InN base tunneling field-effect transistor that polarization inversion layer thickness is 24nm is made.
Step 1. makes drift layer 2 on substrate 1, such as Fig. 3 b.
Substrate 1 is done using sapphire, is using metal organic chemical vapor deposition technology epitaxial thickness on substrate 1
The unintentional doping GaN semiconductor material of [0001] crystal orientation of 1000nm forms drift layer 2, wherein the technique item that extension uses
Part are as follows: temperature is 950 DEG C, pressure 40Torr, hydrogen flowing quantity 4000sccm, ammonia flow 4000sccm, gallium source flux
For 100 μm of ol/min, the extension time is 2h.
Step 2. makes body area 3, such as Fig. 3 c.
On the buffer layer 2 using the InN semiconductor material of the unintentional doping of molecular beam epitaxy technique extension [0001] crystal orientation
Material forms the body area 3 with a thickness of 30nm, wherein the process conditions that extension uses are as follows: vacuum degree is less than or equal to 1.0 × 10- 10Mbar, radio-frequency power 400W, reactant use N2, high-purity indium source, the extension time be 30min.
Step 3. production polarization inversion layer 4, such as Fig. 3 d.
Referring to Fig. 4, this step is implemented as follows:
3.1) molecular beam epitaxy technique, the unintentional doping of extension [0001] crystal orientation in body area 3 are used
In0.95Ga0.05N semiconductor material forms the In that a layer thickness is 24nm0.95Ga0.05N layers, wherein the technique item that extension uses
Part are as follows: vacuum degree is less than or equal to 1.0 × 10-10Mbar, radio-frequency power 400W, reactant use N2, it is high-purity indium source, high-purity
Gallium source is spent, in 19:1, the extension time is 24min for In molecular flow and the control of Ga molecular flow ratio；
3.2) in the In of 3.1) extension0.95Ga0.05Mask is made for the first time on N semiconductor material, is existed using the mask
In0.95Ga0.05It etches to be formed using reactive ion etching technology at left and right sides of N semiconductor material and gets out of a predicament or an embarrassing situation 5, and be etched to buffering
2 top of layer stop, wherein etching the process conditions of use are as follows: Cl2Flow is 15sccm, pressure 10mT, power 100W；
3.3) 2 top of buffer layer in the covering of the area Wei Beiti 3 and In0.95Ga0.05Second of production is covered on N semiconductor material
Mould uses the In in reactive ion etching technology etching removal left side using the mask0.95Ga0.05N semiconductor material, formation width
For the polarization inversion layer 4 of 100nm, wherein etch the process conditions of use are as follows: Cl2Flow is 15sccm, pressure 10mT, function
Rate is 100W.
Step 4. production drain electrode 6, such as Fig. 3 e.
Two sides get out of a predicament or an embarrassing situation 5 and polarization inversion layer 4 top third time production mask, got out of a predicament or an embarrassing situation using the mask on right side
5 tops deposit metal Al using electron beam evaporation technique, form drain electrode 6, wherein the process conditions that deposit metal uses are as follows: high
Purity silicon source, vacuum degree is less than 1.8 × 10-3Pa, power 400W, evaporation rate are less than
Step 5. makes source electrode 7, such as Fig. 3 f.
Get out of a predicament or an embarrassing situation 5 in left side, polarization inversion layer 4 and drain 6 the production mask of top the 4th time, using the mask in left side
5 tops get out of a predicament or an embarrassing situation using electron beam evaporation technique deposit Pt metal, forms source electrode 7, wherein the process conditions that deposit metal uses
Are as follows: high purity platinum source, vacuum degree is less than 1.8 × 10-3Pa, power 400W, evaporation rate are less than
Step 6. makes dielectric layer 8, such as Fig. 3 g.
Referring to Fig. 5, this step is implemented as follows:
6.1) it is formed sediment on source electrode 7, body area 3, polarization inversion layer 4 and the top of drain electrode 6 using plasma enhanced chemical vapor
Product technology and conformal covering process deposit the SiN dielectric that a layer thickness is 20nm, wherein deposit the process conditions of passivation layer
It is: gas NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, and temperature is 300 DEG C, radio frequency
Power is 25W, pressure 950mTorr, deposition time 20min.
6.2) the 5th production mask on the 6.1) insulating dielectric materials of deposit, is carved using the mask using reactive ion
The SiN dielectric of erosion technology etching removal left and right side part, forms dielectric layer 8, which covers the body of part
Area 3 and polarization inversion layer 4, the thickness for being located at 3 top of body area, 4 left side of polarization inversion layer and top is 20nm, wherein is carved
Lose the process conditions used are as follows: CF4Flow is 45sccm, O2Flow is 5sccm, pressure 15mTorr, power 250W.
Step 7. makes grid step 9, such as Fig. 3 h.
The 6th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
It etching to form etching depth as 10nm using reactive ion etching technology on the left of dielectric layer 8, width is the grid step 9 of 10nm,
In, etch the process conditions of use are as follows: CF4Flow is 45sccm, O2Flow is 5sccm, pressure 15mTorr, and power is
250W。
Step 8. makes modulation panel 10, such as Fig. 3 i.
The 7th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
The modulation panel 10 that 8 right upper portion of dielectric layer is 70nm using electron beam evaporation technique deposit Pt metal formation width, the modulation panel
10 width overlapping with polarization inversion layer 4 are 50nm, and 10 left side of modulation panel and the horizontal space in 4 left side of polarization inversion layer are
20nm, wherein the process conditions that deposit metal uses are as follows: high purity platinum source, vacuum degree is less than 1.8 × 10-3Pa, power are
400W, evaporation rate are less than
Step 9. makes grid 11, such as Fig. 3 j.
The 8th production exposure mask in source electrode 7, body area 3, dielectric layer 8, modulation panel 10, polarization inversion layer 4, drain electrode 6, utilizes
Dielectric layer 8 top of the exposure mask between 9 right side of 10 left side of modulation panel and grid step deposits metal using electron beam evaporation technique
Ni formation width is the grid 11 of 30nm, wherein the process conditions that deposit metal uses are as follows: high-purity nickel source, vacuum degree are less than
1.8×10-3Pa, power 400W, evaporation rate are less than
Step 10. makes tunnelling grid 12, such as Fig. 3 k.
The 9th production is covered in source electrode 7, body area 3, dielectric layer 8, grid 11, modulation panel 10, polarization inversion layer 4, drain electrode 6
Film, the tunnelling grid 12 for the use of electron beam evaporation technique deposit W metal formation width being 10nm on grid step 9 using the exposure mask,
The thickness of the tunnelling grid 12 is greater than 10nm, the production of complete cost device, wherein the process conditions that deposit metal uses are as follows: high-purity
Nickel source is spent, vacuum degree is less than 1.8 × 10-3Pa, power 400W, evaporation rate are less than
Embodiment two: a kind of polarization doping InN base tunneling field-effect transistor that polarization inversion layer thickness is 10nm is made.
Step 1 makes drift layer 2 on substrate 1, such as Fig. 3 b.
Substrate 1 is done using silicon carbide, on substrate 1 using metal organic chemical vapor deposition technology temperature be 950
DEG C, pressure 40Torr, hydrogen flowing quantity 4000sccm, ammonia flow 4000sccm, gallium source flux is 100 μm of ol/min,
The unintentional doping GaN semiconductor material of [0001] crystal orientation that epitaxial thickness is 750nm under the process conditions that the extension time is 1.5h
Material forms drift layer 2.
Step 2 makes body area 3, such as Fig. 3 c.
It is less than or equal to 1.0 × 10 in vacuum degree using molecular beam epitaxy technique on the buffer layer 2-10Mbar, radio-frequency power are
400W, reactant use N2, high-purity indium source, the extension time is 20min, process conditions under extension [0001] crystal orientation non-therefore
The InN semiconductor material of meaning doping, forms the body area 3 with a thickness of 20nm.
Step 3 production polarization inversion layer 4, such as Fig. 3 d.
Referring to Fig. 4, this step is implemented as follows:
Molecular beam epitaxy technique 3a) is used in body area 3, is less than or equal to 1.0 × 10 in vacuum degree-10Mbar, radio-frequency power
For 400W, reactant uses N2, high-purity indium source, high purity gallium source, In molecular flow and Ga molecular flow ratio control in 17:3, outside
Between delay for 10min process conditions under, the In of the unintentional doping of extension [0001] crystal orientation0.85Ga0.15N semiconductor material, shape
The In for being 10nm at a layer thickness0.85Ga0.15N layers；
3b) in 3a) In of extension0.85Ga0.15Mask is made for the first time on N semiconductor material, is existed using the mask
In0.85Ga0.15Using reactive ion etching technology in Cl at left and right sides of N semiconductor material2Flow is 20sccm, pressure 10mT,
The stopping of 2 top of buffer layer is etched under the process conditions that power is 150W, formation gets out of a predicament or an embarrassing situation 5；
3c) 2 top of buffer layer in the covering of the area Wei Beiti 3 and In0.85Ga0.15Second of production is covered on N semiconductor material
Mould, using the mask using reactive ion etching technology in Cl2Flow is 15sccm, and pressure 10mT, power is the technique of 70W
Under the conditions of, the In in etching removal left side0.85Ga0.15N semiconductor material, formation width are the polarization inversion layer 4 of 40nm.
Step 4 production drain electrode 6, such as Fig. 3 e.
The specific implementation of this step is identical as the step 4 of embodiment one.
Step 5 makes source electrode 7, such as Fig. 3 f.
The specific implementation of this step is identical as the step 5 of embodiment one.
Step 6 makes dielectric layer 8, such as Fig. 3 g.
It is implemented as follows referring to such as Fig. 5, this step:
6a) plasma enhanced CVD skill is used on source electrode 7, body area 3, polarization inversion layer 4 and 6 tops of drain electrode
Art and conformal covering process are in NH3、N2And SiH4Gas, gas flow are respectively 2.5sccm, 950sccm and 250sccm, temperature
It is 300 DEG C, radio-frequency power 25W, pressure 950mTorr, deposition time is to deposit a layer thickness under the process conditions of 10min
For the dielectric SiN of 10nm；
6b) in 6a) deposit insulating dielectric materials on the 5th production mask, using the mask use reactive ion etching
Technology is in CF4Flow is 45sccm, O2Flow is 5sccm, and pressure 15mTorr, power is etching under the process conditions of 250W
The dielectric SiN of left and right side part is removed, dielectric layer 8 is formed, which covers body area 3 and the polarization of part
Inversion layer 4, the thickness for being located at 3 top of body area, 4 left side of polarization inversion layer and top is 10nm.
Step 7 makes grid step 9, such as Fig. 3 h.
The 6th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
Using reactive ion etching technology in CF on the left of dielectric layer 84Flow is 45sccm, O2Flow is 5sccm, pressure 15mTorr,
Power is under the process conditions of 250W, and it is 5nm that etching, which forms etching depth, and width is the grid step 9 of 5nm.
Step 8 makes modulation panel 10, such as Fig. 3 i.
The 7th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
8 right upper portion of dielectric layer is using electron beam evaporation technique in high purity platinum source, and vacuum degree is less than 1.8 × 10-3Pa, power are
200W, evaporation rate are less thanProcess conditions under, deposit Pt metal formation width be 30nm modulation panel 10, the modulation panel
10 width overlapping with polarization inversion layer 4 are 20nm, and 10 left side of modulation panel and the horizontal space in 4 left side of polarization inversion layer are
10nm。
Step 9 makes grid 11, such as Fig. 3 j.
The 8th production exposure mask in source electrode 7, body area 3, dielectric layer 8, modulation panel 10, polarization inversion layer 4, drain electrode 6, utilizes
Dielectric layer 8 top of the exposure mask between 9 right side of 10 left side of modulation panel and grid step is using electron beam evaporation technique in high-purity
Nickel source, vacuum degree is less than 1.8 × 10-3Pa, power 200W, evaporation rate are less thanProcess conditions under, deposit W metal
Formation width is the grid 11 of 10nm.
Step 10 makes tunnelling grid 12, such as Fig. 3 k.
The 9th production is covered in source electrode 7, body area 3, dielectric layer 8, grid 11, modulation panel 10, polarization inversion layer 4, drain electrode 6
Film uses electron beam evaporation technique in high-purity nickel source using the exposure mask on grid step 9, and vacuum degree is less than 1.8 × 10-3Pa,
Power is 200W, and evaporation rate is less thanProcess conditions under, deposit W metal formation width be 5nm tunnelling grid 12, should
The thickness of tunnelling grid 12 is greater than 5nm, the production of complete cost device..
Embodiment three: a kind of polarization doping InN base tunneling field-effect crystal that polarization inversion layer thickness is 1.2nm is made
Pipe.
Step A. makes drift layer 2 on substrate 1, such as Fig. 3 b.
Substrate 1 is done using GaN material, is using metal organic chemical vapor deposition technology epitaxial thickness on substrate 1
The GaN semiconductor material of the unintentional doping of [0001] crystal orientation of 500nm forms drift layer 2, wherein the technique that extension uses
Condition are as follows: temperature is 950 DEG C, pressure 40Torr, hydrogen flowing quantity 4000sccm, ammonia flow 4000sccm, gallium source stream
Amount is 100 μm of ol/min, and the extension time is 1h.
Step B. makes body area 3, such as Fig. 3 c.
On the buffer layer 2 using the InN semiconductor material of the unintentional doping of molecular beam epitaxy technique extension [0001] crystal orientation
Material forms the body area 3 with a thickness of 10nm, wherein the process conditions that extension uses are as follows: vacuum degree is less than or equal to 1.0 × 10- 10Mbar, radio-frequency power 400W, reactant use N2, high-purity indium source, the extension time be 10min.
Step C. production polarization inversion layer 4, such as Fig. 3 d.
Referring to Fig. 4, this step is implemented as follows:
C1 molecular beam epitaxy technique, the In of the unintentional doping of extension [0001] crystal orientation in body area 3) are used0.1Ga0.9N
Semiconductor material forms the In that a layer thickness is 1.2nm0.1Ga0.9N layers, wherein the process conditions that extension uses are as follows: vacuum degree
Less than or equal to 1.0 × 10-10Mbar, radio-frequency power 400W, reactant use N2, high-purity indium source, high purity gallium source, In point
In 1:9, the extension time is 72s for subflow and the control of Ga molecular flow ratio；
C2) in C1) In of extension0.1Ga0.9Mask is made for the first time on N semiconductor material, is existed using the mask
In0.1Ga0.9It etches to be formed using reactive ion etching technology at left and right sides of N semiconductor material and gets out of a predicament or an embarrassing situation 5, and be etched to buffer layer
2 tops stop, wherein the process conditions for etching use are identical as the step 3.2) of embodiment one.
C3) 2 top of buffer layer in the covering of the area Wei Beiti 3 and In0.1Ga0.9Second of production mask on N semiconductor material,
The In in reactive ion etching technology etching removal left side is used using the mask0.1Ga0.9N semiconductor material, formation width are
The polarization inversion layer 4 of 10nm, wherein the process conditions for etching use are identical as one step 3.3) of embodiment.
Step D. production drain electrode 6, such as Fig. 3 e.
The specific implementation of this step is identical as the step 4 of embodiment one.
Step E. makes source electrode 7, such as Fig. 3 f.
The specific implementation of this step is identical as the step 5 of embodiment one.
Step F. makes dielectric layer 8, such as Fig. 3 g.
Referring to Fig. 5, this step is implemented as follows:
F1) plasma enhanced CVD skill is used on source electrode 7, body area 3, polarization inversion layer 4 and 6 tops of drain electrode
Art and conformal covering process deposit the dielectric SiN that a layer thickness is 1nm, wherein the process conditions for depositing passivation layer are:
NH3、N2And SiH4Gas, gas flow are respectively 2.5sccm, 950sccm and 250sccm, and temperature is 300 DEG C, and radio-frequency power is
25W, pressure 950mTorr, deposition time 1min；
F2) in F1) deposit insulating dielectric materials on the 5th production mask, using the mask use reactive ion etching
The dielectric SiN of technology etching removal left and right side part, forms dielectric layer 8, which covers the body area of part
3 and polarization inversion layer 4, the thickness for being located at 3 top of body area, polarization inversion layer 4 left side and top is 1nm, wherein etching is adopted
Process conditions are identical as one step 6.2) of embodiment.
Step G. makes grid step 9, such as Fig. 3 h.
The 6th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
It etching to form etching depth as 0.5nm using reactive ion etching technology on the left of dielectric layer 8, width is the grid step 9 of 1nm,
In, etch the process conditions of use are as follows: CF4Flow is 45sccm, O2Flow is 5sccm, pressure 15mTorr, and power is
250W。
Step H. makes modulation panel 10, such as Fig. 3 i.
The 7th production exposure mask in source electrode 7, body area 3, dielectric layer 8, polarization inversion layer 4, drain electrode 6, is existed using the exposure mask
The modulation panel 10 that 8 right upper portion of dielectric layer is 6nm using electron beam evaporation technique deposit Pt metal formation width, the modulation panel 10
Overlapping width is 5nm with polarization inversion layer 4, and 10 left side of modulation panel and the horizontal space in 4 left side of polarization inversion layer are
1nm, wherein the process conditions for depositing metal are identical as the step 8 of embodiment one.
Step I makes grid 11, such as Fig. 3 j.
The 8th production exposure mask in source electrode 7, body area 3, dielectric layer 8, modulation panel 10, polarization inversion layer 4, drain electrode 6, utilizes
Dielectric layer 8 top of the exposure mask between 9 right side of 10 left side of modulation panel and grid step deposits metal using electron beam evaporation technique
Ni formation width is the grid 11 of 3nm, wherein the process conditions for depositing metal are identical as the step 9 of embodiment one.
Step J. makes tunnelling grid 12, such as Fig. 3 k.
The 9th production is covered in source electrode 7, body area 3, dielectric layer 8, grid 11, modulation panel 10, polarization inversion layer 4, drain electrode 6
Film uses electron beam evaporation technique in high-purity nickel source using the exposure mask on grid step 9, and vacuum degree is less than 1.8 × 10-3Pa,
Power is 400W, and evaporation rate is less thanProcess conditions under deposit W metal, formation width is the tunnelling grid 12 of 1nm, should
The thickness of tunnelling grid 12 is greater than 0.5nm, is electrically connected tunnelling grid 12 successively with modulation panel 10 and grid 11, complete cost device
Production.
Effect of the invention can be further illustrated by following emulation.
Emulation 1 emulates device of the invention electron concentration in the state of the equilibrium and hole concentration distribution, as a result
Such as Fig. 6, wherein Fig. 6 (a) is distribution of electron's density, and Fig. 6 (b) is hole concentration distribution.As seen from Figure 6, devices use of the present invention
Polarization doping effect can form high hole concentration in source region, and moderate electron concentration can be formed in drain region.
Emulation 2 is distributed device of the invention along the polarization charge of device left side edge, hole concentration in the state of the equilibrium
It is emulated, as a result such as Fig. 7.As seen from Figure 7, in the body area of device and buffering bed boundary there are the polarization negative electrical charge of high concentration,
Polarization negative electrical charge can generate high concentration hole in body area 3.This shows that device source region institute can be formed using polarity effect
The hole concentration needed.
Emulation 3, to device of the invention in the state of the equilibrium along the polarization charge of device right side edge, carrier concentration point
Cloth is emulated, as a result such as Fig. 8.As seen from Figure 8, in the polarization inversion layer of device of the present invention, there are high concentrations with body regional boundary face
Polarize positive charge, and there are the polarization negative electrical charges of high concentration for the interface of the area Er Ti 3 and buffer layer 2, and polarizing positive charge can be in body
Electronics is generated in area 3, and the negative electrical charge that polarizes can generate hole in body area 3, due at polarization inversion layer 4 and 3 interface of body area
Electron concentration of nearby inducting is greater than hole concentration of inducting, therefore shows in polarize inversion layer 4 and the body area 3 near 3 interface of body area
For electron concentration.This shows electron concentration needed for can forming device drain region using polarity effect.
Emulation 4, the tunneling field-effect transistor and device of the invention of III nitride base to tradition based on physical doping
The transfer characteristic of part is emulated, as a result such as Fig. 9.Fig. 9 as it can be seen that in the off case the electric leakage of device of the present invention be significantly less than biography
The electric leakage of system device shows that the OFF state characteristic of device of the present invention is better than the tunnelling of traditional III nitride base based on physical doping
Field effect transistor；And the forward current of device of the present invention-voltage response slope is significantly greater than tradition in the on-state
The forward current of the tunneling field-effect transistor of III nitride base based on physical doping-voltage response slope, shows
The subthreshold swing of device of the present invention is better than the tunneling field-effect transistor of traditional III nitride base based on physical doping
Subthreshold swing.
Above description is only three specific embodiments of the invention, is not construed as limiting the invention, it is clear that for this
It, can be without departing substantially from the principle and scope of the present invention after having understood the content of present invention and principle for the professional in field
In the case where, various modifications and variations in form and details are carried out according to the method for the present invention, but these are based on the present invention
Modifications and variations still within the scope of the claims of the present invention.
Claims (10)
1. InN base tunneling field-effect transistor is adulterated in a kind of polarization, comprising: body area (3), drain electrode (6), source electrode (7), grid
(11), it is characterized in that:
It is successively arranged buffer layer (2) and substrate (1) below the body area (3), which uses the non-event of [0001] crystal orientation
The GaN semiconductor material of meaning doping；
The upper right quarter of the body area (3) is deposited with polarization inversion layer (4), uses the unintentional doping of [0001] crystal orientation
InxGa1-xN semiconductor material, width f is 10~100nm, and the thickness h satisfaction approximate with In component x of polarization inversion layer (4) is closed
It is formula:
The two sides of the body area (3) are etched with get out of a predicament or an embarrassing situation (5), and drain electrode (6) is located at the top of right side step (5), and thickness is greater than
The sum of the thickness in body area (3) and polarization inversion layer (4)；Source electrode (7) is located at the top of left side step (5), and thickness is greater than body area
(3) thickness；
The top of the body area (3) and the left side of polarization inversion layer (4) and top are deposited with dielectric layer (8)；The dielectric layer (8)
Left side is etched with grid step (9), and top right-to-left is successively deposited with modulation panel (10) and tunnelling grid (12), and grid (11) is located at
Between modulation panel (10) and tunnelling grid (12).
2. tunneling field-effect transistor according to claim 1, which is characterized in that the grid (11), width c are less than
The width b of modulation panel (10), width b are 6~70nm.
3. tunneling field-effect transistor according to claim 1, which is characterized in that the drain electrode (6) uses metal
Work function will be lower than metal work function used by deposit grid (11).
4. tunneling field-effect transistor according to claim 1, which is characterized in that the source electrode (7) uses metal
Work function is higher than metal work function used by deposit grid (11).
5. tunneling field-effect transistor according to claim 1, which is characterized in that the modulation panel (10), with polarization
The overlapping width of inversion layer (4) is less than the width f of polarization inversion layer (4) and the width b of modulation panel (10), and using the function of metal
Function is higher than metal work function used by deposit grid (11).
6. tunneling field-effect transistor according to claim 1, which is characterized in that the dielectric layer (8), using SiO2Or
SiN or Al2O3Or HfO2Or TiO2Insulating dielectric materials, in body area (3) top, polarization inversion layer (4) left side and polarization transoid
The thickness a in layer (4) these regions of top is equal, and is filled up completely body area (3), polarization inversion layer (4), grid (11), modulation
Region between plate (10), thickness a are 1~20nm.
7. tunneling field-effect transistor according to claim 1, it is characterised in that the grid step (9), depth e are less than
The thickness a of dielectric layer (8), width d are less than the width b of modulation panel (10) and the width c of grid (11).
8. tunneling field-effect transistor according to claim 1, which is characterized in that the tunnelling grid (12), width with
Grid step (9) is identical, and lower part is located at grid step (9) above, and thickness is greater than the depth of grid step (9), and using the function of metal
Function is less than or equal to metal work function used by deposit grid (11), and tunnelling grid (12), modulation panel (10) and grid
(11) it is successively electrically connected.
9. tunneling field-effect transistor according to claim 1, it is characterised in that:
The substrate (1), using sapphire, silicon carbide, GaN material；
The body area (3), using the InN semiconductor material of the unintentional doping of [0001] crystal orientation.
10. a kind of method for making polarization doping InN base tunneling field-effect transistor, which comprises the steps of:
A. on substrate (1) the unintentional doping of extension [0001] crystal orientation GaN semiconductor material, formed with a thickness of 500~
The buffer layer (2) of 1000nm；
B. on buffer layer (2) the unintentional doping of extension [0001] crystal orientation InN semiconductor material, formed with a thickness of 10~
The body area (3) of 30nm；
C. production polarization inversion layer (4):
C1) on body area (3) the unintentional doping of extension [0001] crystal orientation InxGa1-xN semiconductor material, the InxGa1-xN half
The width f of conductor material is 10~100nm, and the thickness h of polarization inversion layer (4) is approximate with In component x to meet relational expression:
C2) in C1) In of extensionxGa1-xMask is made for the first time on N semiconductor material, is etched using the mask in the left and right sides
Formation is got out of a predicament or an embarrassing situation (5), and is etched to the stopping of buffer layer (2) top；
C3) buffer layer (2) top in the area Wei Beiti (3) covering and InxGa1-xSecond of production mask, benefit on N semiconductor material
With the In in mask etching removal left sidexGa1-xN semiconductor material forms polarization inversion layer (4)；
D. two sides get out of a predicament or an embarrassing situation (5) and polarize inversion layer (4) top third time production mask, using the mask right side leave office
Rank (5) top deposits metal, forms drain electrode (6)；
E. get out of a predicament or an embarrassing situation (5) in left side, polarize inversion layer (4) and the production mask of top the 4th time of (6) of draining, existed using the mask
Left side get out of a predicament or an embarrassing situation (5) top deposit metal, formed source electrode (7)；
F. dielectric layer (8) are made:
F1 insulating dielectric materials, covering source electrode (7), body area (3), polarization inversion layer (4) and leakage) are deposited using conformal covering process
Pole (6)；
F2) in F1) deposit insulating dielectric materials on the 5th production mask, utilize the mask etching removal left and right side portion
The insulating dielectric materials divided are formed dielectric layer (8), which covers body area (3) and polarization inversion layer (4) of part,
And it is located at body area (3) top, is equal with each region thickness a on top on the left of polarization inversion layer (4), thickness a is 1~
20nm；
G. the 6th production exposure mask in source electrode (7), body area (3), dielectric layer (8), polarization inversion layer (4), drain electrode (6), utilizes
Exposure mask etching on the left of the dielectric layer (8) forms etching depth less than dielectric layer (8) thickness, and width be less than modulation panel (10) and
The grid step (9) of the width of grid (11)；
H. the 7th production exposure mask in source electrode (7), body area (3), dielectric layer (8), polarization inversion layer (4), drain electrode (6), utilizes
The exposure mask forms modulation panel (10) in dielectric layer (8) right upper portion deposit metal, which is 6~70nm.It should
The width that modulation panel (10) and polarization inversion layer (4) overlap is less than the width of polarization inversion layer (4) and the width of modulation panel (10),
And the horizontal space on the left of the modulation panel (10) and on the left of polarization inversion layer (4) is identical as the thickness of dielectric layer (8)；
I. selection metal work function is greater than drain electrode (6) and is less than the metal of source electrode (7) and modulation panel (10) metal work function；In source
Pole (7), dielectric layer (8), modulation panel (10), is polarized inversion layer (4), the 8th production exposure mask in drain electrode (6) at body area (3), is utilized
Dielectric layer (8) top depositing selected metal of the exposure mask on the left of modulation panel (10) between grid step (9) right side forms grid
(11)；
J. selection metal work function is less than or equal to the metal of the metal work function of grid (11), in source electrode (7), body area (3), is situated between
Matter layer (8), modulation panel (10), polarizes inversion layer (4), the 9th production exposure mask in drain electrode (6) at grid (11), utilizes the exposure mask
The depositing selected metal on grid step (9) forms the tunnelling grid (12) that thickness is greater than grid step (9) depth, realizes tunnelling grid
(12), the electrical connection between modulation panel (10), grid (11) three, completes the production of device.
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| CN111063735A (en) * | 2019-12-03 | 2020-04-24 | 西安电子科技大学 | Multi-stage coupling gate tunneling field effect transistor and manufacturing method thereof |
| CN111063738A (en) * | 2019-12-03 | 2020-04-24 | 西安电子科技大学 | Tunneling field effect device based on overlapped coupling plate and manufacturing method |
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