CN110993692A - Tunneling field effect transistor and manufacturing method thereof - Google Patents

Tunneling field effect transistor and manufacturing method thereof Download PDF

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CN110993692A
CN110993692A CN201911217921.2A CN201911217921A CN110993692A CN 110993692 A CN110993692 A CN 110993692A CN 201911217921 A CN201911217921 A CN 201911217921A CN 110993692 A CN110993692 A CN 110993692A
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grid
plate
electrode
dielectric layer
gate
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CN110993692B (en
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毛维
何元浩
刘晓雨
马佩军
杜鸣
张进成
郝跃
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Xidian University
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Abstract

The invention discloses a tunneling field effect transistor, which mainly solves the problems of random impurity fluctuation and bipolar off-state electric leakage of the traditional tunneling field effect transistor, and is provided with a substrate (1), a body region (2) and a gate dielectric layer (3) from bottom to top, wherein lower steps (4) are etched on two sides of the body region and the gate dielectric layer, a source electrode (6) and a drain electrode (5) are respectively deposited above the lower steps on the left side and the right side, a source electrode modulation plate (7), a grid electrode (8) and a grid electrode coupling modulation plate (9) and a drain electrode coupling modulation plate (10) which are distributed at intervals are sequentially arranged above the gate dielectric layer from left to right, and passivation layers (11) are arranged on the peripheries of the gate dielectric layer, the drain electrode, the source electrode modulation plate, the grid electrode coupling modulation plate and the drain electrode coupling modulation plate, the power consumption of the device is reduced, the switching speed and the reliability of the device are improved, and the device can be used for a low-power electronic system.

Description

Tunneling field effect transistor and manufacturing method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a tunneling field effect transistor which can be used for a low-power-consumption circuit system.
Technical Field
The rapid development of semiconductor technology has promoted the integration level of integrated circuit chips to be continuously improved at a rate of doubling every 2-3 years, and has brought a great leap in chip performance. However, as the device size is further reduced, the problems of static power consumption and switching power consumption of the conventional MOSFET device become more and more significant, and the requirements of future low-power-consumption applications and energy conservation and environmental protection cannot be fully met. As a novel low-power-consumption semiconductor device expected to replace the traditional MOSFET device, the tunneling field effect transistors TFETs can realize steeper sub-threshold slope based on a quantum band-band tunneling mechanism, have the advantages of high switching speed and good effect of inhibiting short channel effect, and are beneficial to realizing high-performance and ultra-low-power-consumption integrated circuit chips. The method has important practical significance for realizing energy conservation, emission reduction, environmental protection and sustainable development. See RF Performance and Avalanche Breakdown analysis of InN Tunnel FETs, IEEE TRANSACTIONS ELECTRON DEVICES, Vol.61, No.10, pp.3405-3410,2014.
Fig. 1 is a conventional tunneling field effect transistor, which includes: the transistor comprises a substrate, a body region, a source region, a drain region and a gate dielectric layer, wherein a grid electrode is deposited on the upper portion of the gate dielectric layer, a drain electrode is deposited on the upper right portion of the drain region, a source electrode is deposited on the upper left portion of the source region, and passivation layers are deposited on the peripheries of the source region, the drain region, the grid electrode, the drain electrode and the source electrode, wherein: the body region is arranged on the substrate and is formed by intrinsic doping or N-type doping with doping concentration of 5 × 109～1×1017cm-3(ii) a The source region is located on the left side of the body region,formed by P-type doping with a doping concentration of 1 × 1018～1×1020cm-3(ii) a The drain region is located at the right side of the body region and is formed by N-type doping with a doping concentration of 1 × 1017～1×1020cm-3(ii) a The gate dielectric layer is arranged on the upper part of the body region, has the same width as the body region, and can be made of SiO2Or SiN or Al2O3Or HfO2Or TiO2Or other insulating dielectric materials, and the thickness of the insulating dielectric material is 1-20 nm; the width of the grid electrode is the same as that of the grid dielectric layer; the passivation layer may be SiO2Or SiN or Al2O3Or Sc2O3Or HfO2Or TiO2An insulating dielectric material. The device with the structure has the following defects:
1. due to the inherent defects of the structure of the device, when the device works under negative pressure, the edge of the grid close to one side of the drain has a strong electric field peak value, so that the serious bipolar off-state leakage problem is caused. 2. The device usually adopts the traditional ion implantation physical doping technology to realize the doping of the source region and the drain region of the device, and the problem of random impurity fluctuation in the device can be caused. These problems lead to degraded device performance, reduced reliability, and increased power consumption.
Disclosure of Invention
The present invention aims to overcome the defects of the prior art, and provide a tunneling field effect transistor and a manufacturing method thereof, so as to effectively suppress the bipolar off-state leakage of a device, increase the switching speed of the device, reduce the power consumption of the device, and significantly improve the reliability of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
1. A tunneling field effect transistor comprising: substrate 1, drain electrode 5, source electrode 6, grid 8, passivation layer 11, substrate 1 top is equipped with body region 2 and gate dielectric layer 3 from bottom to top in proper order, its characterized in that:
lower steps 4 are etched on two sides of the body region 2 and the gate dielectric layer 3, and a drain electrode 5 is positioned on the upper portion of the right lower step 4; the source electrode 6 is positioned at the upper part of the left lower step 4;
a source electrode modulation plate 7 is arranged above the left side of the gate dielectric layer 3, a grid electrode coupling modulation plate 9 and a drain electrode coupling modulation plate 10 which are distributed at intervals are arranged on the gate dielectric layer on the right side of the source electrode modulation plate from left to right, and a grid electrode 8 is positioned between the source electrode modulation plate 7 and the grid electrode coupling modulation plate 9;
the passivation layer 11 is positioned on the periphery of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8, the gate electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 10;
the grid coupling modulation plate 9 is composed of m grid induction polar plates with the same size, m is larger than or equal to 1, the distance S between the leftmost grid induction polar plate and the grid 8 is 0.5-20 nm, the distances between two adjacent grid induction polar plates are sequentially increased from left to right, and the distances between two adjacent grid induction polar plates are larger than S;
the drain coupling modulation plate 10 is composed of n drain induction polar plates with the same size, n is larger than or equal to 1, the distance R between the rightmost drain induction polar plate and the drain 5 is 0-20 nm, the distance between two adjacent drain induction polar plates is sequentially increased from right to left, the distance between the two adjacent drain induction polar plates is larger than R, and the distance Q between the leftmost drain induction polar plate and the rightmost gate induction polar plate is larger than or equal to the distance between each two adjacent drain induction polar plates and the distance between each two adjacent gate induction polar plates.
Further, the width L of the source modulation plate 7120-100 nm, and a distance L between the gate and the gate 820.5-20 nm, and the same metal as the source electrode 6.
Furthermore, each grid induction polar plate is in an independent floating state, namely is not in contact with any electrode or metal, the work function of the metal adopted by each grid induction polar plate is less than or equal to that of the metal adopted by the grid 8, and the work functions of the two adjacent grid induction polar plates are arranged in a manner that the work function of the left grid induction polar plate is not less than that of the right grid induction polar plate; width L of each gate induction plate4All 1-10 nm, and the thickness T3All of which are 10 to 60nm and T3Not greater than the thickness of the gate 8.
Further, the leakage induction polar plates are mutually arrangedThe leakage induction plates are in an independent floating state, namely, the leakage induction plates are not in contact with any electrode or metal, the work function of the metal adopted by each leakage induction plate is greater than or equal to that of the metal adopted by the drain electrode 5, and the work functions of the two adjacent leakage induction plates are arranged in a mode that the work function of the left leakage induction plate is not less than that of the right leakage induction plate; width L of each leakage induction plate5Are all 1-10 nm and have the thickness T equal to that of the grid coupling modulation plate 93The same is true.
Furthermore, the work function of the metal adopted by the drain electrode 5 is lower than that of the metal adopted by the deposition grid electrode 8, and the upper surface of the drain electrode 5 is not lower than that of each drain induction polar plate;
further, the source electrode 6 is made of a metal having a work function higher than that of the metal used for depositing the gate electrode 8, and is electrically connected to the source electrode modulation plate 7.
Further, the passivation layer 11 is made of SiO2Or SiN or Al2O3Or Sc2O3Or HfO2Or TiO2And the thickness of the insulating medium material is larger than that of the gate coupling modulation plate 9, and the insulating medium material completely fills the areas between the source modulation plate 7 and the gate 8, between the gate 8 and the gate coupling modulation plate 9, between the gate induction plates, between the gate coupling modulation plate 9 and the drain coupling modulation plate 10, between the drain induction plates and between the drain coupling modulation plate 10 and the drain 5.
Second, the manufacturing method
The method for manufacturing the tunneling field effect transistor comprises the following steps of:
A. selecting a substrate;
B. epitaxial growth of a homogeneous semiconductor material on a substrate 1 to a thickness T1A 5-50 nm body region 2;
C. depositing an insulating dielectric material on the body region 2 to a thickness T2A gate dielectric layer 3 of 0.5-40 nm;
D. manufacturing a mask on the gate dielectric layer 3, and etching two sides of the gate dielectric layer 3 by using the mask until reaching the upper surface of the substrate 1 to form a lower step 4;
E. manufacturing a mask on the gate dielectric layer 3 and the lower step 4, and depositing metal on the upper part of the lower step 4 on the right side by using the mask to form a drain electrode 5;
F. manufacturing masks on the gate dielectric layer 3, the left lower step 4 and the drain 5, and depositing metal on the upper part of the left lower step 4 and the upper left part of the gate dielectric layer 3 by using the masks to form a source electrode 6 and a source electrode modulation plate 7;
G. manufacturing masks on the gate dielectric layer 3, the drain electrode 5, the source electrode 6 and the source electrode modulation plate 7, and depositing metal on the upper part of the gate dielectric layer 3 on the right side of the source electrode modulation plate 7 by using the masks to form a gate electrode 8;
H. manufacturing a grid coupling modulation board 9
H1) A mask is manufactured on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7 and the grid electrode 8, metal with work function less than or equal to that of the grid electrode 8 is deposited on the upper part of the gate dielectric layer 3 on the right side of the grid electrode 8 by utilizing the mask, and the width L is formed41 to 10nm, and a thickness T3The first grid induction polar plate is 10-60 nm and in a floating state, and the distance S between the grid induction polar plate and the grid 8 is 0.5-20 nm;
H2) making masks on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8 and the first gate induction polar plate, and depositing metal with work function less than or equal to that of the first gate induction polar plate on the upper part of the gate dielectric layer 3 on the right side of the first gate induction polar plate by using the masks to form the width L 41 to 10nm, and a thickness T3The second grid induction polar plate is 10-60 nm and in a floating state, and the distance between the two grid induction polar plates is larger than S;
H3) and analogizing in sequence, manufacturing a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8 and the m-1 gate induction polar plate, and depositing metal with the work function smaller than or equal to that of the m-1 gate induction polar plate on the upper part of the gate dielectric layer 3 on the right side of the m-1 gate induction polar plate by using the mask until the width L is formed41 to 10nm, and a thickness T3The m gate induction polar plates are 10-60 nm and in a floating state, the m gate induction polar plates jointly form a gate coupling modulation plate 9, and the distance between every two adjacent gate induction polar plates is gradually increased from left to right to complete gate coupling modulationAnd (3) manufacturing a plate 9, wherein m is more than or equal to 1.
I. Manufacturing a drain-coupled modulation panel 10
I1) Making a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8 and the gate electrode coupling modulation plate 9, depositing metal with work function larger than or equal to that of the drain electrode 5 on the upper part of the gate dielectric layer 3 on the left side of the drain electrode 5 by using the mask to form a width L 51 to 10nm, and a thickness T3The first leakage induction polar plate is 10-60 nm and in a floating state, and the distance R between the leakage induction polar plate and the drain 5 is 0-20 nm;
I2) making masks on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8, the grid electrode coupling modulation plate 9 and the first drain induction polar plate, and depositing metal with the work function larger than or equal to that of the first drain induction polar plate on the upper part of the gate dielectric layer 3 on the left side of the first drain induction polar plate by using the masks to form the width L 51 to 10nm, and a thickness T3A second leakage induction polar plate which is 10-60 nm and is in a floating state, wherein the distance between the two leakage induction polar plates is larger than R;
I3) and analogizing in sequence, manufacturing masks on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8, the grid electrode coupling modulation plate 9 and the n-1 leakage induction polar plates, and depositing metal with the work function larger than or equal to that of the n-1 leakage induction polar plate on the upper part of the gate dielectric layer 3 on the left side of the n-1 leakage induction polar plate by using the masks until the width L is formed51 to 10nm, and a thickness T3The n leakage induction polar plates are 10-60 nm and in a floating state, n is more than or equal to 1, the n leakage induction polar plates jointly form a drain coupling modulation plate 10, and the distance between every two adjacent leakage induction polar plates is increased progressively from right to left in sequence to complete the manufacture of the drain coupling modulation plate 10;
J. and depositing a passivation layer 11 with the thickness larger than that of the gate coupling modulation plate 9 in the peripheral areas of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8, the gate coupling modulation plate 9 and the drain electrode coupling modulation plate 10, and completely filling the areas between the source electrode modulation plate 7 and the gate electrode 8, between the gate electrode 8 and the gate coupling modulation plate 9, between the gate induction plates, between the gate coupling modulation plate 9 and the drain electrode coupling modulation plate 10, between the drain induction plates and between the drain electrode coupling modulation plate 10 and the drain electrode 5 to finish the manufacture of the device.
Compared with the traditional tunneling field effect transistor, the device of the invention has the following advantages:
1. random impurity fluctuation is avoided.
The device adopts a source electrode modulation plate, a grid electrode coupling modulation plate and a drain electrode coupling modulation plate for induction doping instead of the traditional ion injection physical doping, and realizes P-type doping by setting the source electrode modulation plate to induce high-concentration holes; meanwhile, the grid coupling modulation plate and the drain coupling modulation plate can induce high-concentration electrons to realize N-type doping, so that the problem of random impurity fluctuation caused by the traditional ion implantation physical doping technology is solved.
2. The bipolar off-state leakage is small and the reliability is high.
The device of the invention adopts a grid coupling modulation plate structure, so that the potential distribution in the body region below the grid medium can be effectively modulated during negative grid voltage, and the direction of the body region from the source region to the drain region is gradually changed. And by modulating the work functions of the grid induction polar plates and the drain induction polar plates by using metal and the distance between two adjacent drain induction polar plates and two adjacent grid induction polar plates, the slow change of the electron concentration near the tunneling position in the body area between the grids and the drains can be realized, the slow change of the energy band in the body area between the grids and the drains can be realized, and the off-state tunneling of the device is effectively inhibited, so that the bipolar off-state leakage is reduced, the switching speed of the device is increased, the power consumption of the device is reduced, and the reliability of the device is obviously improved.
Drawings
Fig. 1 is a structural view of a conventional tunnel field effect transistor;
FIG. 2 is a block diagram of a tunneling field effect transistor of the present invention;
FIG. 3 is a schematic overall flow chart of the present invention for fabricating a tunneling field effect transistor;
FIG. 4 is a sub-flow diagram illustrating the steps of fabricating the 1 st to the mth gate sensing plates according to the present invention;
FIG. 5 is a sub-flow diagram illustrating the steps of fabricating the 1 st to nth drain sensing plates according to the present invention;
fig. 6 is a graph comparing simulation results of transfer characteristics of a conventional tunneling field effect transistor and the device of the present invention.
Detailed Description
Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, the present example provides a tunneling field effect transistor, which includes: the field effect transistor comprises a substrate 1, a body region 2, a gate dielectric layer 3, a lower step 4, a drain electrode 5, a source electrode 6, a source electrode modulation plate 7, a gate electrode 8, a gate electrode coupling modulation plate 9, a drain electrode coupling modulation plate 10 and a passivation layer 11, wherein:
the substrate 1 is made of InN or InGaN or Si or Ge or SiGe or InN material;
the body region 2 is located in the upper part of the substrate 1 and has a thickness T15-50 nm InN or InGaN or Si or Ge or SiGe or InN material;
a gate dielectric layer 3 is arranged above the body region 2 and made of SiO2Or SiN or Al2O3Or HfO2Or TiO2Insulating dielectric material of thickness T20.5 to 40 nm;
lower steps 4 are formed on two sides of the body region 2 and the gate dielectric layer 3 in an etching mode, a drain electrode 5 of the lower steps 4 is located on the right side, the work function of metal adopted by the drain electrode 5 is lower than that of metal adopted by a deposited gate electrode 8, and the upper surface of the drain electrode 5 is not lower than that of each leakage induction polar plate; the source electrode 6 is positioned on the left lower step 4, the work function of the metal adopted by the source electrode 6 is higher than that of the metal adopted by the deposition grid electrode 8, and the source electrode 6 is electrically connected with the source electrode modulation plate 7;
the upper part of the gate dielectric layer 3 on the right side of the source electrode 6 is provided with a width L1A source modulation plate 7 of 20-100 nm and made of the same metal as the source 6; the gate dielectric layer 3 on the right side of the source electrode modulation plate 7 is provided with a width L3A gate electrode 8 of 20-100 nm, a distance L between the gate electrode 8 and the source electrode modulation plate 720.5 to 20 nm;
the grid medium layer 3 on the right side of the grid is provided with m grid induction polar plates with the same size and grid coupling modulation plates 9 distributed at intervals, wherein m is more than or equal to 1The distance S between the leftmost gate induction polar plate and the grid 8 is 0.5-20 nm, the distance between two adjacent gate induction polar plates is sequentially increased from left to right, and the distance between two adjacent gate induction polar plates on the leftmost side is larger than S; each grid induction polar plate is in an independent floating state, namely is not contacted with any electrode or metal, the work function of the metal adopted by each grid induction polar plate is less than or equal to that of the metal adopted by the grid 8, and the work functions of the two adjacent grid induction polar plates are arranged in a mode that the work function of the left grid induction polar plate is not less than that of the right grid induction polar plate; width L of each gate induction plate4All 1-10 nm, and the thickness T3All of which are 10 to 60nm and T3Not greater than the thickness of the gate 8.
The grid medium layer 3 on the right side of the grid coupling modulation plate 9 is provided with n leakage induction polar plates with the same size and drain coupling modulation plates 10 which are distributed at intervals, wherein n is more than or equal to 1, the distance R between the rightmost leakage induction polar plate and the drain 5 is 0-20 nm, the distance between two adjacent leakage induction polar plates is sequentially increased from right to left, the distance between two adjacent leakage induction polar plates on the rightmost side is larger than R, and the distance Q between the leftmost leakage induction polar plate and the rightmost grid induction polar plate is larger than or equal to the distance between each adjacent leakage induction polar plate and the distance between each adjacent grid induction polar plate; each leakage induction polar plate is in an independent floating state, namely is not contacted with any electrode or metal, the work function of the metal adopted by each leakage induction polar plate is larger than or equal to that of the metal adopted by the drain 5, and the work functions of the two adjacent leakage induction polar plates are arranged in a mode that the work function of the left leakage induction polar plate is not smaller than that of the right leakage induction polar plate; width L of each leakage induction plate5Are all 1-10 nm and have the thickness T equal to that of the grid coupling modulation plate 93The same is true.
The passivation layer 11 is arranged on the periphery of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8, the grid electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 10, and SiO with the thickness larger than that of the multistage coupling grid 8 is adopted2Or SiN or Al2O3Or Sc2O3Or HfO2Or TiO2Insulating dielectric materialFeeding; the regions between the source modulation plate 7 and the gate 8, between the gate 8 and the gate coupling modulation plate 9, between the gate sensing plates, between the gate coupling modulation plate 9 and the drain coupling modulation plate 10, between the drain sensing plates, and between the drain coupling modulation plate 10 and the drain 5 are completely filled with the passivation layer 11.
Referring to fig. 3, the method for fabricating a tunneling field effect transistor according to the present invention provides the following three embodiments.
The first embodiment is as follows: and manufacturing the tunneling field effect transistor with 1 grid induction polar plate and 1 drain induction polar plate.
Step 1. silicon semiconductor material is selected as substrate 1, as shown in fig. 3 a.
Step 2. make body region 2 on silicon substrate 1, as shown in fig. 3 b.
A molecular beam epitaxy technology is used for epitaxial growth of a silicon semiconductor material with the thickness of 5nm on a silicon substrate 1 to form a body region 2, wherein the epitaxial growth adopts the following process conditions: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 150W, and high-purity silicon source as reactant.
And step 3, manufacturing a gate dielectric layer 3, as shown in fig. 3 c.
And depositing a layer of SiN insulating dielectric material with the thickness of 0.5nm on the upper part of the body region 2 by using a plasma enhanced chemical vapor deposition technology, wherein the process conditions for depositing the insulating dielectric material are as follows: the gas being NH3、N2And SiH4The gas flow rate is 2.5sccm, 950sccm and 250sccm respectively, the temperature is 300 ℃, the radio frequency power is 25W, and the pressure is 950 mTorr.
And 4, manufacturing a lower step 4 as shown in fig. 3 d.
Manufacturing a mask on the gate dielectric layer 3 for the first time, etching and removing materials on the left side and the right side on the two sides of the body region 2 and the gate dielectric layer 3 by using a reactive ion etching technology by using the mask, and etching until the upper surface of the substrate 1 stops to form a lower step 4, wherein the etching adopts the following process conditions: cl2The flow rate is 15sccm, the pressure is 10mT, and the radio frequency power is 100W.
Step 5, manufacturing the drain 5, as shown in fig. 3 e.
The second manufacturing is carried out on the gate dielectric layer 3 and the lower step 4And a mask, wherein the metal Al is deposited on the upper part of the right lower step 4 by using an electron beam evaporation technology through the mask to form the drain electrode 5, and the process conditions adopted by the deposited metal are as follows: high purity aluminum source with vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000071
And 6, manufacturing a source electrode 6 and a source electrode modulation plate 7, as shown in the figure 3 f.
And (3) making masks on the gate dielectric layer 3, the left lower step 4 and the drain 5 for the third time, and depositing metal Pt on the upper part of the left lower step 4 and the right upper part of the gate dielectric layer 3 by using an electron beam evaporation technology by using the masks to form a source electrode 6 and a source electrode modulation plate 7 with the width of 20nm, wherein the technological conditions adopted by the deposited metal are as follows: high purity platinum source, vacuum degree less than 1.8 × 10- 3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000072
And 7, manufacturing a grid 8 as shown in fig. 3 g.
Manufacturing a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6 and the source electrode modulation plate 7 for the fourth time, depositing metal Ni on the upper part of the gate dielectric layer 3 on the right side of the source electrode modulation plate 7 by using an electron beam evaporation technology by using the mask to form a grid electrode 8 with the thickness of 15nm and the width of 20nm, wherein the distance between the grid electrode 8 and the source electrode modulation plate 7 is 0.5nm, and the process conditions adopted by metal deposition are as follows: high purity nickel source with vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000081
And 8, manufacturing a grid coupling modulation plate 9, as shown in fig. 3 h.
Making a mask on the upper parts of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7 and the grid electrode 8 for the fifth time, depositing metal Mo on the upper part of the gate dielectric layer 3 on the right side of the grid electrode 8 by using the mask through an electron beam evaporation technology to form 1 metal Mo with the thickness of 10nm and the width of 1nmThe grid induction polar plate forms a grid coupling modulation plate 9, the distance between the grid induction polar plate and the grid is 0.5nm, wherein, the process conditions adopted by the deposited metal are as follows: high purity molybdenum source with vacuum degree less than 1.8 × 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000082
And 9, manufacturing the drain-coupled modulation board 10, as shown in fig. 3 i.
Making masks on the upper parts of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8 and the gate electrode coupling modulation plate 9 for the sixth time, depositing metal Al on the upper part of the gate dielectric layer 3 on the left side of the drain electrode 5 by using an electron beam evaporation technology by using the masks to form 1 leakage induction polar plate with the thickness of 10nm and the width of 1nm, wherein the leakage induction polar plate is electrically connected with the drain electrode 5, the distance between the drain induction polar plate and the gate induction polar plate is 5nm, and the process conditions adopted by deposited metal are as follows: high purity aluminum source with vacuum degree less than 1.8X 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000083
Step 10, a passivation layer 11 is manufactured, as shown in fig. 3 j.
A passivation layer 11 with the thickness of 50nm is deposited in the peripheral areas of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8, the gate electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 10 by using a plasma enhanced chemical vapor deposition technology, and the areas between the source electrode modulation plate 7 and the gate electrode 8, between the gate electrode 8 and the gate electrode coupling modulation plate 9, between each gate induction plate, between the gate electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 10, between each drain induction plate and between the drain electrode coupling modulation plate 10 and the drain electrode 5 are completely filled with the passivation layer 11, wherein the process conditions for depositing the passivation layer are as follows: the gas being NH3、N2And SiH4The gas flow is respectively 2.5sccm, 950sccm and 250sccm, the temperature is 300 ℃, the radio frequency power is 25W, and the pressure is 950mTorr, thus completing the manufacture of the device.
Example two: manufacturing tunneling field effect transistor with 2 gate induction pole plates and 2 drain induction pole plates
Step one, an InN semiconductor material is selected as the substrate 1, as shown in fig. 3 a.
Step two, a body region 2 is manufactured on the InN substrate 1, as shown in fig. 3 b.
Using molecular beam epitaxy technique on InN substrate 1 under vacuum degree of 1.0 × 10-10mbar, radio frequency power of 150W, high-purity In source and N as reactant2The body region 2 is formed by epitaxy of an InN semiconductor material with a thickness of 25nm under the process conditions of (1).
And step three, manufacturing a gate dielectric layer 3, as shown in fig. 3 c.
Using plasma enhanced chemical vapor deposition in the upper part of the body region 2 to form NH gas3、N2And SiH4The SiN insulating dielectric material with the thickness of 20nm is deposited under the process conditions that the gas flow is 2.5sccm, 950sccm and 250sccm respectively, the temperature is 300 ℃, the radio frequency power is 25W and the pressure is 950 mTorr.
And fourthly, manufacturing a lower step 4 as shown in figure 3 d.
Making a mask on the gate dielectric layer 3 for the first time, and using the mask to etch Cl on the two sides of the body region 2 and the gate dielectric layer 3 by using a reactive ion etching technology2And etching to remove the materials on the left side and the right side under the process conditions of 15sccm flow, 10mT pressure and 100W radio frequency power until the etching is stopped until the upper surface of the substrate 1, and forming a lower step 4.
Step five, manufacturing the drain electrode 5, as shown in fig. 3 e.
Making a mask on the gate dielectric layer 3 and the lower step 4 for the second time, and using the mask to evaporate the high-purity silver source on the upper part of the lower step 4 at the right side by using an electron beam evaporation technology, wherein the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000094
Under the process conditions of (3), depositing metal Ag to form the drain electrode 5.
And step six, manufacturing a source electrode 6 and a source electrode modulation plate 7, as shown in figure 3 f.
At the gate dielectric layer 3 and the left lower stageMaking a mask on the step 4 and the drain 5 for the third time, and using the mask to evaporate the upper part of the left lower step 4 and the right upper part of the gate dielectric layer 3 by using an electron beam to form a high-purity platinum source with the vacuum degree of less than 1.8 multiplied by 10- 3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000091
Under the process conditions of (1), metal Pt is deposited to form a source electrode 6 and a source electrode modulation plate 7 with the width of 50 nm.
Step seven, manufacturing the grid 8, as shown in figure 3 g.
Making a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6 and the source electrode modulation plate 7 for the fourth time, and using the mask to evaporate the high-purity nickel source on the upper part of the gate dielectric layer 3 on the right side of the source electrode modulation plate 7 by using an electron beam evaporation technology, wherein the vacuum degree is less than 1.8 multiplied by 10- 3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000092
Under the process conditions of (1), depositing metal Ni to form a grid 8 with the thickness of 40nm and the width of 60nm, wherein the distance between the grid 8 and the source modulation plate 7 is 10 nm.
And step eight, manufacturing the grid coupling modulation plate 9, as shown in fig. 3 h.
Referring to fig. 4, the specific implementation of this step is as follows:
8.1) making a mask on the upper parts of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7 and the grid electrode 8 for the fifth time, using the mask to perform electron beam evaporation technology on the upper part of the gate dielectric layer 3 on the right side of the grid electrode 8 to form a high-purity tin source, wherein the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000093
Under the process conditions of (1), depositing metal Sn to form a 1 st grid induction polar plate with the thickness of 35nm and the width of 5nm, wherein the distance between the grid induction polar plate and a grid is 3 nm;
8.2) making a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8 and the upper part of the 1 st grid induction polar plate for the sixth time, and utilizing the maskThe upper part of a grid dielectric layer 3 on the right side of the 1 st grid induction polar plate is coated with a high-purity molybdenum source by using an electron beam evaporation technology, and the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000101
Under the process conditions of (1), depositing metal Mo with a metal work function smaller than that of Sn to form a 2 nd gate induction polar plate with the thickness of 35nm and the width of 5nm, wherein the distance between the 2 nd gate induction polar plate and the 1 st gate induction polar plate is 5 nm; the 2 grid induction polar plates jointly form a grid coupling modulation plate 9, and the manufacture of the grid coupling modulation plate 9 is completed.
Step nine, manufacturing the drain-coupled modulation board 10, as shown in fig. 3 i.
Referring to fig. 5, the specific implementation of this step is as follows:
9.1) manufacturing a mask on the upper parts of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8 and the gate coupling modulation plate 9 for the seventh time, and using the mask to perform electron beam evaporation on the upper part of the gate dielectric layer 3 on the left side of the drain electrode 5 to form a high-purity aluminum source with a vacuum degree of less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000102
Under the process conditions of (1), depositing metal Al to form a 1 st leakage induction plate with the thickness of 35nm and the width of 5nm, wherein the distance between the leakage induction plate and the drain electrode is 5 nm.
9.2) making a mask for the eighth time on the upper parts of the grid dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8, the grid electrode coupling modulation plate 9 and the 1 st leakage induction polar plate, using the mask to perform electron beam evaporation technology on the upper part of the grid dielectric layer 3 on the left side of the 1 st leakage induction polar plate to form a high-purity titanium source, wherein the vacuum degree is less than 1.8 multiplied by 10-3Pa, power of 400W, evaporation rate of less than
Figure BDA0002300004550000103
Under the process conditions of (1), depositing metal Ti with the metal work function larger than that of Al to form a 2 nd leakage induction polar plate with the thickness of 35nm and the width of 5nm, wherein the 2 nd leakage induction polar plate and the second leakage induction polar plateThe distance between 1 leakage induction polar plate is 7nm, the distance between the 2 nd leakage induction polar plate and the 2 nd grid induction polar plate is 15nm, the two leakage induction polar plates jointly form a drain coupling modulation plate 10, and the manufacture of the drain coupling modulation plate 10 is completed
Step ten, manufacturing a passivation layer 11, as shown in fig. 3 j.
Using plasma enhanced chemical vapor deposition technology to form NH gas in the peripheral area of the grid dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the grid electrode 8, the grid electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 103、N2And SiH4The passivation layer 11 with a thickness of 75nm is deposited under the process conditions of gas flow of 2.5sccm, 950sccm and 250sccm, temperature of 300 ℃, radio frequency power of 25W and pressure of 950mTorr, and the regions between the source modulation plate 7 and the gate 8, between the gate 8 and the gate coupling modulation plate 9, between the gate sensing electrode plates, between the gate coupling modulation plate 9 and the drain coupling modulation plate 10, between the drain sensing electrode plates and between the drain coupling modulation plate 10 and the drain 5 are completely filled with the passivation layer 11, thereby completing the fabrication of the device.
Example three: and manufacturing the tunneling field effect transistor with 3 grid induction polar plates and 3 drain induction polar plates.
Step a. Ge semiconductor material is selected as substrate 1, fig. 3 a.
Step b. the body region 2 is fabricated on the Ge substrate 1, as in fig. 3 b.
A germanium semiconductor material with the thickness of 50nm is epitaxially grown on a Ge substrate 1 by using a molecular beam epitaxy technology to form a body region 2, wherein the epitaxial process conditions are as follows:
vacuum degree of 1.0X 10 or less-10mbar，
The radio frequency power is 150W and,
the reactant is a high-purity germanium source.
And step C, manufacturing a gate dielectric layer 3, as shown in FIG. 3 c.
And depositing a layer of SiN insulating medium material with the thickness of 40nm on the upper part of the body region 2 by using a plasma enhanced chemical vapor deposition technology, wherein the process conditions for depositing the insulating medium material are as follows:
the temperature of the reaction chamber is 300 ℃, the radio frequency power is 250W, the pressure is 950mTorr,
SiH gas simultaneously introduced into the reaction cavity4、N2、NH3，
SiH4The flow rate was 2.5sccm, N2Flow rate 950sccm, NH3The flow rate was 250 sccm.
And D, manufacturing a lower step 4 as shown in fig. 3 d.
Manufacturing a mask on the gate dielectric layer 3 for the first time, etching and removing materials on the left side and the right side on the two sides of the body region 2 and the gate dielectric layer 3 by using a reactive ion etching technology by using the mask, and etching until the upper surface of the substrate 1 is stopped to form a lower step 4, wherein the etching adopts the following process conditions:
Cl2the flow rate was 15sccm and,
the pressure is 10mT, and the pressure is lower than the normal pressure,
the RF power is 100W.
Step e. drain 5 is fabricated as shown in fig. 3 e.
Manufacturing a mask on the gate dielectric layer 3 and the lower step 4 for the second time, and depositing metal Al on the upper part of the lower step 4 on the right side by using an electron beam evaporation technology by using the mask to form the drain electrode 5, wherein the process conditions adopted by the deposited metal are as follows:
a high-purity aluminum source,
vacuum degree less than 1.8X 10-3Pa，
The power is 400W, and the power is,
evaporation rate less than
Figure BDA0002300004550000111
Step f. make source 6 and source modulation plate 7, as in fig. 3 f.
And manufacturing masks on the gate dielectric layer 3, the left lower step 4 and the drain 5 for the third time, and depositing metal Pt on the upper part of the left lower step 4 and the right upper part of the gate dielectric layer 3 by using an electron beam evaporation technology by using the masks to form a source electrode 6 and a source electrode modulation plate 7 with the width of 100nm, wherein the process conditions adopted by the deposited metal are as follows:
a source of high-purity platinum in a solvent,
vacuum degree less than 1.8X 10-3Pa，
The power is 400W, and the power is,
evaporation rate less than
Figure BDA0002300004550000121
And G, manufacturing the grid 8, as shown in figure 3 g.
Manufacturing a mask on the gate dielectric layer 3, the drain electrode 5, the source electrode 6 and the source electrode modulation plate 7 for the fourth time, depositing metal Ni on the upper part of the gate dielectric layer 3 on the right side of the source electrode modulation plate 7 by using an electron beam evaporation technology by using the mask to form a grid electrode 8 with the thickness of 80nm and the width of 100nm, wherein the distance between the grid electrode 8 and the source electrode modulation plate 7 is 20nm, and the process conditions adopted by metal deposition are as follows:
a source of high-purity nickel,
vacuum degree less than 1.8X 10-3Pa，
The power is 400W, and the power is,
evaporation rate less than
Figure BDA0002300004550000122
And H, manufacturing a grid coupling modulation plate 9, as shown in fig. 3 h.
Making masks on the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7 and the upper part of the gate electrode 8 for the fifth time, depositing metal Mo on the upper part of the gate dielectric layer 3 on the right side of the gate electrode 8 by utilizing the masks by using an electron beam evaporation technology to form 3 gate induction polar plates with the thickness of 60nm, the width of 10nm and the same metal work function, wherein the distance between the 1 st gate induction polar plate on the left side and the gate electrode is 20nm, the distance between the 1 st gate induction polar plate and the 2 nd gate induction polar plate is 25nm, and the distance between the 2 nd gate induction polar plate and the 3 rd gate induction polar plate is 30 nm; the three gate induction polar plates jointly form a gate coupling modulation plate 9, and the manufacturing of the gate coupling modulation plate 9 is completed, wherein the process conditions adopted by the deposited metal are as follows:
a source of high-purity molybdenum in a high purity,
vacuum degree less than 1.8X 10-3Pa，
The power is 400W, and the power is,
evaporation rate less than
Figure BDA0002300004550000123
Step i. fabricate the drain-coupled modulation panel 10, as shown in fig. 3 i.
Making masks on the upper parts of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8 and the gate electrode coupling modulation plate 9 for the sixth time, depositing metal Ti on the upper part of the gate dielectric layer 3 on the left side of the drain electrode 5 by using an electron beam evaporation technology by using the masks to form 3 leakage induction polar plates with the thickness of 60nm, the width of 10nm and the same metal work function, wherein the distance between the 1 st leakage induction polar plate on the right side and the drain electrode 5 is 20nm, the distance between the 1 st leakage induction polar plate and the 2 nd leakage induction polar plate is 30nm, the distance between the 2 nd leakage induction polar plate and the 3 rd leakage induction polar plate is 40nm, and the distance between the 3 rd leakage induction polar plate and the 3 rd gate induction polar plate is 50 nm; the three drain-induced plates jointly form a drain-coupled modulation board 10, and the manufacturing of the drain-coupled modulation board 10 is completed, wherein the process conditions adopted by the deposited metal are as follows:
a source of high-purity titanium having a high purity,
vacuum degree less than 1.8X 10-3Pa，
The power is 400W, and the power is,
evaporation rate less than
Figure BDA0002300004550000131
Step j. fabricate the passivation layer 11, as shown in fig. 3 j.
And depositing a passivation layer 11 with the thickness of 100nm in the peripheral areas of the gate dielectric layer 3, the drain electrode 5, the source electrode 6, the source electrode modulation plate 7, the gate electrode 8, the gate electrode coupling modulation plate 9 and the drain electrode coupling modulation plate 10 by using a plasma enhanced chemical vapor deposition technology, wherein the process conditions for depositing the passivation layer are as follows:
the temperature of the reaction chamber is 300 ℃, the radio frequency power is 250W, the pressure is 950mTorr,
SiH gas simultaneously introduced into the reaction cavity4、N2、NH3，
SiH4The flow rate was 2.5sccm, N2Flow rate 950sccm, NH3The flow rate was 250 sccm.
The passivation layer 11 is completely filled in the areas between the source modulation plate 7 and the gate 8, between the gate 8 and the gate coupling modulation plate 9, between the gate induction plates, between the gate coupling modulation plate 9 and the drain coupling modulation plate 10, between the drain induction plates, and between the drain coupling modulation plate 10 and the drain 5, thereby completing the manufacture of the device.
The effects of the present invention can be further illustrated by the following simulations.
The transfer characteristics of the conventional tunneling field effect transistor and the device of the present invention were simulated, and the results are shown in fig. 6.
As can be seen from fig. 6, in the off state, that is, when the overdrive voltage is less than 0V, the bipolar off-state leakage of the device of the present invention is significantly less than that of the conventional device, indicating that the off-state characteristics of the device of the present invention are better than that of the conventional tunneling field effect transistor.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.

Claims (10)

1. A tunneling field effect transistor comprising: substrate (1), drain electrode (5), source electrode (6), grid (8), passivation layer (11), substrate (1) top is equipped with body region (2) and grid dielectric layer (3) from bottom to top in proper order, its characterized in that:
lower steps (4) are etched on two sides of the body region (2) and the gate dielectric layer (3), and the drain electrode (5) is positioned on the upper portion of the right lower step (4); the source electrode (6) is positioned at the upper part of the left lower step (4);
a source electrode modulation plate (7) is arranged above the left side of the grid dielectric layer (3), grid electrode coupling modulation plates (9) and drain electrode coupling modulation plates (10) which are distributed at intervals are arranged on the grid dielectric layer on the right side of the source electrode modulation plate from left to right, and a grid electrode (8) is positioned between the source electrode modulation plate (7) and the grid electrode coupling modulation plates (9);
the passivation layer (11) is positioned at the periphery of the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8), the grid electrode coupling modulation plate (9) and the drain electrode coupling modulation plate (10);
the grid coupling modulation plate (9) consists of m grid induction polar plates with the same size, wherein m is larger than or equal to 1, the distance S between the leftmost grid induction polar plate and the grid (8) is 0.5-20 nm, the distances between two adjacent grid induction polar plates are sequentially increased from left to right, and the distances between two adjacent grid induction polar plates are larger than S;
the drain coupling modulation plate (10) is composed of n leakage induction polar plates with the same size, n is larger than or equal to 1, the distance R between the rightmost leakage induction polar plate and the drain (5) is 0-20 nm, the distances between every two adjacent leakage induction polar plates are sequentially increased from right to left, the distances between every two adjacent leakage induction polar plates are larger than R, and the distance Q between the leftmost leakage induction polar plate and the rightmost grid induction polar plate is larger than or equal to the distance between every two adjacent leakage induction polar plates and the distance between every two adjacent grid induction polar plates.
2. Device according to claim 1, characterized in that the width L of the source modulation plate (7)120 to 100nm, and a distance L between the gate electrode (8) and the gate electrode20.5-20 nm, and the same metal as the source electrode (6).
3. The device of claim 1, wherein each gate induction polar plate is in an independent floating state, namely is not in contact with any electrode or metal, the work function of the metal adopted by each gate induction polar plate is less than or equal to that of the metal adopted by the gate (8), and the work functions of the two adjacent gate induction polar plates are arranged in a manner that the work function of the left gate induction polar plate is not less than that of the right gate induction polar plate; width L of each gate induction plate4All 1-10 nm, and the thickness T3All of which are 10 to 60nm and T3Not greater than the thickness of the gate (8)。
4. The device of claim 1, wherein each leakage induction plate is in a mutually independent floating state, i.e. not in contact with any electrode or metal, the work function of the metal adopted by each leakage induction plate is greater than or equal to that of the metal adopted by the drain electrode (5), and the work functions of the two adjacent leakage induction plates are set in a manner that the work function of the left leakage induction plate is not less than that of the right leakage induction plate; width L of each leakage induction plate5Are all 1-10 nm and the thickness is equal to the thickness T of the grid coupling modulation plate (9)3The same is true.
5. Device according to claim 1, characterized in that the substrate (1) is of InN or InGaN or Si or Ge or SiGe or other semiconductor material.
6. Device according to claim 1, characterized in that said body region (2) adopts a thickness T15-50 nm InN or InGaN or Si or Ge or SiGe or other semiconductor material.
7. The device of claim 1, wherein:
the work function of the adopted metal of the drain electrode (5) is lower than that of the metal adopted for depositing the grid electrode (8), and the upper surface of the drain electrode (5) is not lower than that of each drain induction polar plate;
the source electrode (6) is made of metal with a work function higher than that of the metal used for depositing the grid electrode (8) and is electrically connected with the source electrode modulation plate (7).
8. The device according to claim 1, wherein the gate dielectric layer (3) is made of SiO2Or SiN or Al2O3Or HfO2Or TiO2Or other insulating dielectric material, of thickness T2Is 0.5 to 40 nm.
9. The device of claim 1,the passivation layer (11) adopts SiO2Or SiN or Al2O3Or Sc2O3Or HfO2Or TiO2And the thickness of the insulating medium material is greater than that of the grid coupling modulation plate (9), and the insulating medium material completely fills the areas between the source modulation plate (7) and the grid (8), between the grid (8) and the grid coupling modulation plate (9), between the grid induction plates, between the grid coupling modulation plate (9) and the drain coupling modulation plate (10), between the drain induction plates and between the drain coupling modulation plate (10) and the drain (5).
10. A method of fabricating a tunneling field effect transistor, comprising the steps of:
A. selecting a substrate;
B. epitaxially growing a homogeneous semiconductor material on a substrate (1) to a thickness T1A body region (2) of 5 to 50 nm;
C. depositing an insulating dielectric material over the body region (2) to a thickness T2A gate dielectric layer (3) of 0.5-40 nm;
D. manufacturing a mask on the gate dielectric layer (3), and etching the two sides of the gate dielectric layer (3) by using the mask until reaching the upper surface of the substrate (1) to form a lower step (4);
E. manufacturing a mask on the gate dielectric layer (3) and the lower step (4), and depositing metal on the upper part of the lower step (4) on the right side by using the mask to form a drain electrode (5);
F. manufacturing masks on the gate dielectric layer (3), the left lower step (4) and the drain electrode (5), and depositing metal on the upper part of the left lower step (4) and the upper left part of the gate dielectric layer (3) by using the masks to form a source electrode (6) and a source electrode modulation plate (7);
G. manufacturing masks on the gate dielectric layer (3), the drain electrode (5), the source electrode (6) and the source electrode modulation plate (7), and depositing metal on the upper part of the gate dielectric layer (3) on the right side of the source electrode modulation plate (7) by using the masks to form a gate electrode (8);
H. manufacturing grid coupling modulation board (9)
H1) Manufacturing masks on the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7) and the grid electrode (8), and depositing a work function smaller than or equal to that of the mask on the upper part of the gate dielectric layer (3) on the right side of the grid electrode (8)Forming a width L in the metal of the work function of the gate (8)41 to 10nm, and a thickness T3The first grid induction polar plate is 10-60 nm and in a floating state, and the distance S between the grid induction polar plate and the grid (8) is 0.5-20 nm;
H2) manufacturing masks on the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8) and the first gate induction polar plate, and depositing metal with the work function smaller than or equal to that of the first gate induction polar plate on the upper part of the gate dielectric layer (3) on the right side of the first gate induction polar plate by using the masks to form the width L41 to 10nm, and a thickness T3The second grid induction polar plate is 10-60 nm and in a floating state, and the distance between the two grid induction polar plates is larger than S;
H3) and analogizing in sequence, manufacturing masks on the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8) and the m-1 gate induction polar plates, and depositing metal with the work function smaller than or equal to that of the m-1 gate induction polar plate on the upper part of the gate dielectric layer (3) on the right side of the m-1 gate induction polar plate by using the masks until the width L is formed41 to 10nm, and a thickness T3The m grid induction polar plates are 10-60 nm and in a floating state, the m grid induction polar plates jointly form a grid coupling modulation plate (9), the distance between every two adjacent grid induction polar plates is gradually increased from left to right, the manufacturing of the grid coupling modulation plate (9) is completed, and m is larger than or equal to 1.
I. Manufacturing a drain electrode coupling modulation board (10)
I1) Manufacturing a mask on the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8) and the grid electrode coupling modulation plate (9), depositing metal with work function larger than or equal to that of the drain electrode (5) on the upper part of the gate dielectric layer (3) on the left side of the drain electrode (5) by using the mask to form a width L51 to 10nm, and a thickness T3The first leakage induction polar plate is 10-60 nm and in a floating state, and the distance R between the leakage induction polar plate and the drain electrode (5) is 0-20 nm;
I2) masks are manufactured on the grid dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8), the grid electrode coupling modulation plate (9) and the first drain induction polar plate, and the use is made ofThe mask deposits metal with work function larger than or equal to that of the first leakage induction polar plate on the upper part of the gate dielectric layer (3) on the left side of the first leakage induction polar plate to form a width L51 to 10nm, and a thickness T3A second leakage induction polar plate which is 10-60 nm and is in a floating state, wherein the distance between the two leakage induction polar plates is larger than R;
I3) and analogizing in sequence, manufacturing masks on the gate dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8), the grid electrode coupling modulation plate (9) and the n-1 leakage induction polar plates, and depositing metal with the work function larger than or equal to that of the n-1 leakage induction polar plate on the upper part of the gate dielectric layer (3) on the left side of the n-1 leakage induction polar plate by using the masks until the width L is formed51 to 10nm, and a thickness T3The n leakage induction polar plates are 10-60 nm and in a floating state, n is more than or equal to 1, the n leakage induction polar plates jointly form a drain coupling modulation plate (10), and the distance between every two adjacent leakage induction polar plates is sequentially increased from right to left to complete the manufacture of the drain coupling modulation plate (10);
J. and depositing a passivation layer (11) with the thickness larger than that of the grid coupling modulation plate (9) on the peripheral areas of the grid dielectric layer (3), the drain electrode (5), the source electrode (6), the source electrode modulation plate (7), the grid electrode (8), the grid coupling modulation plate (9) and the drain electrode coupling modulation plate (10), and completely filling the areas between the source electrode modulation plate (7) and the grid electrode (8), between the grid electrode (8) and the grid coupling modulation plate (9), between all grid induction polar plates, between the grid coupling modulation plate (9) and the drain electrode coupling modulation plate (10), between all drain induction polar plates and between the drain electrode coupling modulation plate (10) and the drain electrode (5) to finish the manufacture of the device.
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