CN109545855B - Preparation method of active region of silicon carbide double-groove MOSFET device - Google Patents

Preparation method of active region of silicon carbide double-groove MOSFET device Download PDF

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CN109545855B
CN109545855B CN201811381503.2A CN201811381503A CN109545855B CN 109545855 B CN109545855 B CN 109545855B CN 201811381503 A CN201811381503 A CN 201811381503A CN 109545855 B CN109545855 B CN 109545855B
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implantation
window
etching
mask
ion implantation
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CN109545855A (en
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杨成樾
白云
汤益丹
陈宏�
田晓丽
王臻星
刘新宇
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention discloses a preparation method of an active region of a silicon carbide double-groove MOSFET device. The method can realize two times of etching of the gate trench and the source trench and three times of ion implantation of the P-, P + and N + active regions only by two times of photoetching. Wherein, the etching of the grid groove and the injection of P-and N + are realized by one-time photoetching and two-time self-alignment process; the source trench and the P + implant are implemented by one photolithography and one self-aligned process. The method has the characteristics of high manufacturing precision and low process cost.

Description

Preparation method of active region of silicon carbide double-groove MOSFET device
Technical Field
The invention belongs to the technical field of semiconductors, relates to a processing and preparation method of a semiconductor device, and particularly relates to a preparation method of an active region of a silicon carbide double-groove MOSFET device.
Background
As a representative example of the third generation wide bandgap semiconductor materials, silicon carbide (SiC) is one of important materials for manufacturing high-temperature, high-frequency, and high-power semiconductor devices due to its excellent physicochemical and electrical properties. Meanwhile, SiC is a semiconductor material having hardness second to that of diamond in nature, and hardly reacts with all substances at normal temperature. From the process of material preparation, the manufacturing process of SiC is highly compatible with the traditional and mature silicon (Si) semiconductor process and can directly form silicon oxide (SiO) through a high-temperature oxidation process2) A passivation layer, which is not comparable to other compound semiconductor materials.
The silicon carbide metal oxide field effect transistor (SiC MOSFET) is a voltage control device, a gate drive circuit is simple to control a channel region, the SiC MOSFET is a multi-sub conductive device, the switching time is short, the power density is high, the SiC MOSFET is a typical power semiconductor device, and the SiC MOSFET is widely applied to various power electronic systems. Compared with the traditional vertical structure metal oxide field effect transistor (VDMOSFET), the metal oxide field effect transistor (DT-MOSFET) with the double-groove structure is formed by grooving the source region and the grid region, and has the advantages of smaller cell size, smaller power loss and larger channel density. Meanwhile, the parasitic JFET effect can be avoided, so that the method becomes a research hotspot and development direction at present.
Due to the difference of the structure of the conventional SiC VDMOSFET device, the etching process of a gate trench and a source trench is additionally added in the preparation process of an active region of the DT-MOSFET device. And when the design depths of the gate trench and the source trench are different, the etching needs to be finished by two times. And the three-time ion implantation process of the P-, N + and P + active regions is adopted, so that the preparation process of the whole active region is realized by at least 5 times of photoetching, and the process is relatively complicated. In addition, when the photoetching process is carried out on the patterned substrate with the groove structure, the uniformity of the whirl coating morphology is more difficult to control in the gluing process compared with the substrate with a plane structure, and the difficulty in controlling the characteristic dimension of a fine line is higher.
Aiming at the preparation process method of the active area of the conventional silicon carbide double-groove metal oxide field effect transistor, the invention provides a preparation process implementation method on the premise of ensuring the process precision, which can greatly simplify the process flow and reduce the processing cost.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects in the manufacturing process of the active area of the SiC DT-MOSFET device, the invention provides a preparation method of the active area of the SiC DT-MOSFET device.
(II) technical scheme
In order to solve the problems, the invention adopts the following technical scheme:
a preparation method of an active region of a silicon carbide double-groove MOSFET device comprises the following steps:
depositing a first injection mask medium on the SiC substrate, forming a first ion injection window, and performing first ion injection;
growing a second implantation mask medium on the first implantation mask medium, forming a second implantation mask medium side wall on the side wall of the first implantation mask medium through etching, and performing second ion implantation;
oxidizing the second injection mask medium side wall completely to form a gate groove etching window through high-temperature oxidation;
etching the SiC substrate at the gate groove etching window to form a gate groove, and removing all mask media;
growing a third injection mask medium and forming a source groove window, and etching the SiC substrate at the source groove window to form a source groove;
etching the third implantation mask medium to widen the source groove window to form a third ion implantation window, and performing third ion implantation;
and removing the third injection mask medium to finish the preparation of the active region.
In some embodiments, the first ion implantation is a P-implantation, the second ion implantation is an N + implantation, and the third ion implantation is a P + implantation.
In some embodiments, the material of the first implantation mask dielectric is silicon oxide, the material of the second implantation mask dielectric is polysilicon, and the material of the third implantation mask dielectric is silicon oxide.
In some embodiments, the width of the second implantation mask dielectric sidewall formed on the sidewall of the first implantation mask dielectric is adjusted by growing the thickness of the second implantation mask dielectric, thereby adjusting the width between the P-implantation region and the N + implantation region.
In some embodiments, the size of the gate trench window is adjusted by the time of the second implantation mask dielectric oxidation, and the longer the oxidation time, the smaller the gate trench window.
In some embodiments, the window of the third implant mask is controlled by adjusting the etch time of the third implant mask dielectric.
In some embodiments, the depth of the second ion implantation is less than the depth of the first ion implantation.
In some embodiments, the depth of the gate trench is greater than the depth of the first ion implantation.
In some embodiments, the third ion implantation region is located on the sidewall, the top and the bottom of the source trench, and the third ion implantation region partially overlaps with the first ion implantation region.
In some embodiments, the first ion implantation window and the source trench window are formed by photolithography and etching, the second implantation mask dielectric sidewall, the gate trench, and the source trench are formed by dry etching, and the source trench window is widened by wet etching.
(III) advantageous effects
In combination with the above description of the technical solution of the present invention, it can be seen that the following beneficial improvements can be brought about by using the process implementation method of the present invention:
the process implementation method adopted by the invention is realized by completing all three ion implantation processes and two groove etching processes of the active area of the SiC MOSFET device through two times of photoetching and three times of self-alignment processes, wherein the grid groove etching and the P-and N + implantation are realized through one time of photoetching and two times of self-alignment processes; the source trench and the P + implantation are realized by one-time photoetching and one-time self-alignment process, so that the requirement on the capacity of photoetching equipment is low, but the precision is high;
the process implementation method adopted by the invention reduces the original process of five times of photoetching to two times, thereby reducing the manufacturing cost of the device;
the process implementation method adopted by the invention reduces the times of glue coating and photoetching on the surface of the patterned substrate, thereby reducing the process processing difficulty and improving the process reliability;
according to the process implementation method adopted by the invention, the gate trench and the source trench are respectively etched, so that the selection of the trench depth is more selective, and the flexibility is high.
Drawings
FIG. 1 is a diagram illustrating a first implantation mask structure according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a second implantation mask structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a gate trench etching window structure in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a gate trench etching structure in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a source trench etching structure in an embodiment of the present invention;
FIG. 6 is a diagram illustrating a third implantation mask structure according to an embodiment of the present invention;
FIG. 7 is a diagram of the active area cell structure of a DT-MOSFET in an embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will be more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings.
In one embodiment of the invention, the preparation method of the active region of the silicon carbide double-groove MOSFET device comprises the following steps:
firstly, growing a first injection mask on an n-type SiC substrate in a large area, forming an injection window by a photoetching and etching process, and performing ion injection to form a P-injection region as shown in figure 1. Where 11 is a first-time implantation mask, whose material is silicon oxide, 12 is a P-implantation region formed at an implantation window, and 13 is a SiC substrate.
And secondly, growing a large-area second injection mask on the basis of the first injection mask, wherein the second injection mask is made of polycrystalline silicon, directly forming a new injection window through dry etching, and performing ion injection to form an N + injection region. The width of the second implantation mask medium side wall formed on the side wall of the first implantation mask medium can be adjusted by growing the thickness of the second implantation mask medium, so that the width between the P-implantation area and the N + implantation area is adjusted. The dry etching time is to remove the first implantation mask and the newly grown second implantation mask on the exposed SiC substrate, and due to the anisotropic characteristic of the dry etching, the second grown implantation mask may remain on the sidewall of the first implantation mask to form a sidewall, and the sidewall and the first implantation mask together form a window of the second implantation mask as shown in fig. 2. Wherein 21 is a newly grown implantation mask sidewall and 22 is an N + implantation region.
And thirdly, oxidizing all the residual second implantation mask medium into silicon oxide through high-temperature oxidation. In the process of converting the polysilicon into the silicon oxide, the thickness of the side wall is further increased, and the growth thickness of the silicon oxide layer and the consumption thickness of the polysilicon layer are approximately 100: 45. Therefore, the window of the second implantation mask is further reduced as shown in fig. 3. The size of the gate trench window can be adjusted by the oxidation time of the second implantation of the mask medium, and the longer the oxidation time is, the smaller the gate trench window is. The gate trench window is minimized when the second implant mask dielectric is fully oxidized to silicon oxide. Wherein 31 is the silicon oxide deposited by the first implantation mask, and 32 is the new silicon oxide converted from polysilicon after high temperature oxidation.
And fourthly, etching the substrate to form a gate trench, wherein 41 is the gate trench as shown in figure 4. The gate trench depth is greater than the P-implant junction depth. And then removing the mask medium of the first two times by using a BOE solution wet method, and cleaning.
And fifthly, growing a third injection mask, forming a new etching window through photoetching, etching and other processes, and etching the SiC substrate to form a source groove as shown in FIG. 5. Where 51 is the newly grown third implantation mask, which is silicon oxide. And 52, forming a window through photoetching and etching, and etching a source groove formed in the SiC substrate.
And sixthly, performing large-area wet etching on the third implantation mask to reduce the thickness of the implantation mask and widen the etching window, wherein the window of the third implantation mask can be controlled by adjusting the etching time of the third implantation mask medium, and at this time, performing ion implantation to form a P + implantation region as shown in FIG. 6. Where 61 is the widened implantation window and 62 is the P + implantation region.
And seventhly, removing the third implantation mask by a wet method to finish the preparation of the active region of the double-groove MOSFET, as shown in FIG. 7. Wherein 71 is a gate trench, 72 is a source trench, 73 is a P + contact region in an active region of a MOSFET device, 74 is an N + contact region in the active region of the MOSFET device, 75 is a P-well region in the active region of the MOSFET device, and 76 is a channel of the MOSFET device.
According to the embodiment of the invention, the method can realize two times of etching of the gate trench and the source trench and three times of ion implantation of the P-, P + and N + active regions only by two times of photoetching. Wherein, the etching of the grid groove and the injection of P-and N + are realized by one-time photoetching and two-time self-alignment process; the source trench and the P + implant are implemented by one photolithography and one self-aligned process. Therefore, the method has the advantages of high manufacturing precision, low process cost and the like.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A preparation method of an active region of a silicon carbide double-groove MOSFET device is characterized by comprising the following steps:
depositing a first injection mask medium on the SiC substrate, forming a first ion injection window, and performing first ion injection;
growing a second implantation mask medium on the first implantation mask medium, forming a second implantation mask medium side wall on the side wall of the first implantation mask medium through etching, and performing second ion implantation;
oxidizing the second injection mask medium side wall completely to form a gate groove etching window through high-temperature oxidation;
etching the SiC substrate at the gate groove etching window to form a gate groove, and removing all mask media;
growing a third injection mask medium and forming a source groove window, and etching the SiC substrate at the source groove window to form a source groove;
etching the third implantation mask medium to widen the source groove window to form a third ion implantation window, and performing third ion implantation;
and removing the third implantation mask medium.
2. The method according to claim 1, wherein the first ion implantation is a P-implantation, the second ion implantation is an N + implantation, and the third ion implantation is a P + implantation.
3. The method according to claim 1, wherein the first implantation mask dielectric is made of silicon oxide, the second implantation mask dielectric is made of polysilicon, and the third implantation mask dielectric is made of silicon oxide.
4. The method according to claim 2, wherein the width of the second implantation mask dielectric sidewall formed on the sidewall of the first implantation mask dielectric is adjusted by growing the thickness of the second implantation mask dielectric, thereby adjusting the width between the P-implantation region and the N + implantation region.
5. The method according to claim 3, wherein the size of the gate trench window is adjusted by the time of the second implantation mask dielectric oxidation, and the longer the oxidation time, the smaller the gate trench window.
6. The method of claim 1, wherein the window of the third implantation mask is controlled by adjusting an etching time of the third implantation mask dielectric.
7. The method of claim 1, wherein the second ion implantation is performed to a depth less than the depth of the first ion implantation.
8. The method of claim 1, wherein the depth of the gate trench is greater than the depth of the first ion implantation.
9. The method of claim 1, wherein the third ion implantation is performed at the sidewalls, top and bottom of the source trench, and the third ion implantation partially overlaps the first ion implantation.
10. The method according to claim 1, wherein the first ion implantation window and the source trench window are formed by photolithography and etching, the second implantation mask dielectric sidewall, the gate trench, and the source trench are formed by dry etching, and the source trench window is widened by wet etching.
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CN111573616B (en) * 2020-04-24 2024-02-13 中国电子科技集团公司第十三研究所 Composite high aspect ratio groove standard template and preparation method thereof
CN113284954B (en) * 2021-07-22 2021-09-24 成都蓉矽半导体有限公司 Silicon carbide MOSFET with high channel density and preparation method thereof
CN114361242B (en) * 2022-03-14 2022-06-14 芯众享(成都)微电子有限公司 Planar silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of adjusting threshold voltage and preparation method thereof

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