CN109545855A - A kind of preparation method of the double groove MOSFET device active areas of silicon carbide - Google Patents
A kind of preparation method of the double groove MOSFET device active areas of silicon carbide Download PDFInfo
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- CN109545855A CN109545855A CN201811381503.2A CN201811381503A CN109545855A CN 109545855 A CN109545855 A CN 109545855A CN 201811381503 A CN201811381503 A CN 201811381503A CN 109545855 A CN109545855 A CN 109545855A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 238000002347 injection Methods 0.000 claims abstract description 83
- 239000007924 injection Substances 0.000 claims abstract description 83
- 150000002500 ions Chemical class 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000001259 photo etching Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000012010 growth Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims 1
- 230000007797 corrosion Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 31
- 238000001459 lithography Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000000243 solution Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000034655 secondary growth Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a kind of preparation methods of the double groove MOSFET device active areas of silicon carbide.The ion implanting three times of gate groove, the twice etching of source groove and P-, P+ and N+ active area need to only can be realized in this method by Twi-lithography.Wherein, self-registered technology is realized by a photoetching and twice for gate groove etching and P-, N+ injection；Source groove and P+ injection are realized by a photoetching and a self-registered technology.This method has the characteristics that make precision height and process costs are low.
Description
Technical field
The invention belongs to technical field of semiconductors, are related to a kind of preparation for processing of semiconductor devices, and in particular to one
The preparation method of the double groove MOSFET device active areas of kind silicon carbide.
Background technique
As the representative in third generation semiconductor material with wide forbidden band, silicon carbide (SiC) is with its excellent physicochemical characteristics
And electrology characteristic becomes one of manufacture high temperature, high frequency, important materials of large power semiconductor device.Meanwhile SiC or nature
Hardness is only second to the semiconductor material of diamond in boundary, does not almost chemically react with all substances under room temperature.From material system
Standby technological angle sets out, and the manufacture craft of SiC is again with tradition and mature silicon (Si) semiconductor technology highly compatible and can be with
Silica (SiO is directly formed by high temperature oxidation process2) passivation layer, this is that other compound semiconductor materials are incomparable
's.
Silicone carbide metal oxide field effect transistor (SiC MOSFET) is voltage control device, gate driving circuit pair
Channel region control is simple, is more subconductivity devices, switch time is short, and power density is a kind of typical power semiconductor device greatly
Part is widely used among various power electronic systems.With traditional vertical structure MOS memory
(VDMOSFET) it compares, carries out grooving in source region and grid region, form the metal oxide field effect crystal with double groove structures
Managing (DT-MOSFET) has smaller cellular size, smaller power consumption penalty, bigger gully density.Meanwhile it can also keep away
Exempt from parasitic JFET effect, therefore becomes current research hotspot and developing direction.
Due to the difference on traditional SiC VDMOSFET device architecture, DT-MOSFET device prepared in active area
Need additionally to increase the etching technics of gate groove and source groove in journey.And when the projected depth difference of gate groove and source groove,
It also needs to etch completion in two times.Along with the ion implantation technology three times of P-, N+, P+ active area, so that completing entire active
The preparation process in area at least needs 5 photoetching to realize, technique is relatively cumbersome.In addition, in this figure with groove structure
Photoetching process is carried out on shape substrate, the homogeneity relative to the substrate of planar structure its whirl coating pattern during gluing is more difficult
Control, it is bigger that this brings the characteristic size of fine lines to control difficulty.
For the process of preparing of the double trench MOSFET active areas of conventional silicon carbide, the present invention
Under the premise of guaranteeing craft precision, a kind of preparation process implementation method is proposed, it can greatly simplify process flow, reduce
Processing cost.
Summary of the invention
(1) technical problems to be solved
For the shortcoming in the manufacturing process of the device active region above-mentioned SiC DT-MOSFET, the invention proposes one kind
The preparation method of the device active region SiC DT-MOSFET.
(2) technical solution
To solve the above-mentioned problems, this invention takes the following technical solutions:
A kind of preparation method of the double groove MOSFET device active areas of silicon carbide, comprising:
Deposition injects exposure mask medium for the first time on sic substrates, and forms first time ion implantation window, and carries out first
Secondary ion injection；
The secondary injection exposure mask medium of growth regulation on first time injection exposure mask medium, by etching in the first time
It injects on the side wall of exposure mask medium and forms second of injection exposure mask medium side wall, and carry out second of ion implanting；
By high-temperature oxydation, by second of injection exposure mask medium side wall, all oxidation forms the groove etched window of grid；
The SiC substrate described in the groove etched opening etch of the grid forms gate groove, and removes all exposure mask media；
Growth third time injection exposure mask medium simultaneously forms source trench openings, etches the SiC lining in the source trench openings
Bottom forms source groove；
Etching the third time injection exposure mask medium broadens the source trench openings, forms third time ion implanting window
Mouthful, and carry out third time ion implanting；
The third time injection exposure mask medium is removed, the preparation of active area is completed.
In some embodiments, the first time ion implanting is P- injection, and second of ion implanting is N+ injection,
The third time ion implanting is P+ injection.
In some embodiments, the material of injection exposure mask medium is silica for the first time, injects exposure mask medium for the second time
Material is polysilicon, and the material that third time injects exposure mask medium is silica.
In some embodiments, exposure mask is injected in first time to adjust by the thickness of the secondary injection exposure mask medium of growth regulation
The width of second of the injection exposure mask medium side wall formed on the side wall of medium, and then adjust between the injection region P- and the injection region N+
Width.
In some embodiments, the size of the medium oxidizing time adjustment gate groove window of exposure mask is injected by second,
Oxidization time is longer, and gate groove window is smaller.
In some embodiments, it is covered by adjusting the etching time of third time injection exposure mask medium to control third time injection
The window of film.
In some embodiments, the depth of second of ion implanting is less than the depth of first time ion implanting.
In some embodiments, the depth of the gate groove is greater than the depth of first time ion implanting.
In some embodiments, the injection region of third time ion implanting is located at side wall, top and the bottom of the source groove,
The region of third time ion implanting and the region part of first time ion implanting are overlapping.
In some embodiments, the first time ion implantation window and the source trench openings pass through photoetching, etching shape
At second of injection exposure mask medium side wall, the gate groove and the source groove are formed by dry etching, the source ditch
Slot window is broadened by wet etching.
(3) beneficial effect
In conjunction with the above-mentioned explanation about technical solution of the present invention, it can be seen that process implementation method of the invention is used, it can
To bring following beneficial improvement:
Process implementation method of the present invention is in the three secondary ions note for completing SiC MOSFET element active area whole
Enter and trench etch process is by Twi-lithography and self-registered technology realization three times twice, wherein gate groove etching and P-, N+
By a photoetching and twice, self-registered technology is realized for injection；Source groove and P+ injection pass through a photoetching and an autoregistration work
Skill is realized, therefore but precision low to lithographic equipment Capability Requirement is high；
The former technique for needing five photoetching is reduced to twice by process implementation method of the present invention, therefore can be reduced
Element manufacturing cost；
Process implementation method of the present invention reduces the gluing photoetching number on patterned substrate surface, therefore
Technique difficulty of processing is reduced, reliability of technology is improved；
Process implementation method of the present invention, grid, source groove are etching realizations, therefore the selection to groove depth respectively
More selective, flexibility ratio is high.
Detailed description of the invention
Fig. 1 is to inject mask structure schematic diagram for the first time in the embodiment of the present invention；
Fig. 2 is second of injection mask structure schematic diagram in the embodiment of the present invention；
Fig. 3 is gate groove etching window structural schematic diagram in the embodiment of the present invention；
Fig. 4 is gate groove etching structure schematic diagram in the embodiment of the present invention；
Fig. 5 is source etching groove structural schematic diagram in the embodiment of the present invention；
Fig. 6 is to inject mask structure schematic diagram for the third time in the embodiment of the present invention；
Fig. 7 is DT-MOSFET active area single cell structure schematic diagram in the embodiment of the present invention.
Specific embodiment
Understand to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and joins
According to attached drawing, the present invention is described in more detail.
In one embodiment of the invention, the preparation method of the double groove MOSFET device active areas of silicon carbide includes following
Step:
The first step, large area deposition injects exposure mask for the first time in N-shaped SiC substrate, passes through photoetching, the process of etching
Injection window is formed, and carries out ion implanting, it is as shown in Figure 1 to form the injection region P-.Wherein 11 be injection exposure mask for the first time, material
Material is silica, and 12 injection region P- to be formed at injection window, 13 be SiC substrate.
Second step, the secondary injection exposure mask of growing large-area growth regulation on the basis of first time injecting exposure mask, second of note
Entering exposure mask medium is polysilicon, new injection window is directly formed by dry etching, and carry out ion implanting, forms N+ injection
Area.It can be formed on the side wall of first time injection exposure mask medium by the thickness of the secondary injection exposure mask medium of growth regulation to adjust
Second of injection exposure mask medium side wall width, and then adjust the width between the injection region P- and the injection region N+.Wherein dry method
Etch period is second of the injection exposure mask newly grown got rid of on injection exposure mask and exposed SiC substrate for the first time, due to
The anisotropy feature of dry etching, the side wall that the injection exposure mask of the second secondary growth can remain in injection exposure mask for the first time form side
Wall, and for the first time injection exposure mask collectively form second of injection exposure mask window it is as shown in Figure 2.Wherein 21 be the note newly grown
Enter exposure mask side wall, 22 be the injection region N+.
Remaining second of injection exposure mask medium is all oxidized to silica by high-temperature oxydation by third step.In polycrystalline
During silicon is converted to silica, the thickness of side wall be will be further increased, and silica layer growth thickness and polysilicon layer consume
Thickness substantially 100: 45.So the window of second of injection exposure mask will further reduce as shown in Figure 3.Second can be passed through
The oxidization time of secondary injection exposure mask medium adjusts the size of gate groove window, and oxidization time is longer, and gate groove window is smaller.Second
Gate groove window is minimum when secondary injection exposure mask medium is all oxidized to silica.Wherein 31 oxygen to inject mask deposition for the first time
SiClx, 32 be the new silica being converted to after high-temperature oxydation by polysilicon.
4th step etches above-mentioned substrate, forms gate groove as shown in figure 4,41 be gate groove.Gate groove depth is greater than P-
Injection junction depth.Then the exposure mask medium before being removed using BOE solution wet process twice, and clean.
5th step, growth third time injection exposure mask, forms new etching window, etching SiC by techniques such as photoetching, etchings
It is as shown in Figure 5 that substrate forms source groove.Wherein 51 be the third time injection exposure mask newly grown, is silica.52 for through photoetching,
Etch the window formed, and the source groove that etching SiC substrate is formed.
6th step, large area wet etching third time injection exposure mask, declines injection mask thicknesses, and etching window exhibition
Width, can by adjust third time injection exposure mask medium etching time come control third time inject exposure mask window, at this time into
It is as shown in Figure 6 that row ion implanting forms the injection region P+.Wherein 61 be the injection window broadened, and 62 be the injection region P+.
7th step, wet process removal third time injection exposure mask, completes double groove MOSFET active area preparations, as shown in Figure 7.Its
In 71 be gate groove, 72 be source groove, and 73 be the contact zone P+ in MOSFET element active area, and 74 is in MOSFET element active areas
The contact zone N+, 75 be MOSFET element active area P-well area, and 76 be the channel of MOSFET element.
Embodiment through the invention it is found that the method for the invention need to only be can be realized by Twi-lithography gate groove,
The twice etching of source groove and the ion implanting three times of P-, P+ and N+ active area.Wherein, gate groove etching and P-, N+ injection
Pass through a photoetching and self-registered technology realization twice；Source groove and P+ injection pass through a photoetching and a self-registered technology reality
It is existing.Therefore, this method has the advantages that make precision is high and process costs are low etc..
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (10)
1. a kind of preparation method of the double groove MOSFET device active areas of silicon carbide, which comprises the following steps:
Deposition injection exposure mask medium for the first time on sic substrates, and forms first time ion implantation window, and carry out for the first time from
Son injection；
The secondary injection exposure mask medium of growth regulation on first time injection exposure mask medium is injected by etching in the first time
Second of injection exposure mask medium side wall is formed on the side wall of exposure mask medium, and carries out second of ion implanting；
By high-temperature oxydation, by second of injection exposure mask medium side wall, all oxidation forms the groove etched window of grid；
The SiC substrate described in the groove etched opening etch of the grid forms gate groove, and removes all exposure mask media；
Growth third time injection exposure mask medium simultaneously forms source trench openings, etches the SiC substrate shape in the source trench openings
At source groove；
Etching the third time injection exposure mask medium broadens the source trench openings, forms third time ion implantation window, and
Carry out third time ion implanting；
Remove the third time injection exposure mask medium.
2. preparation method according to claim 1, which is characterized in that the first time ion implanting is P- injection, described
Second of ion implanting is N+ injection, and the third time ion implanting is P+ injection.
3. preparation method according to claim 1, which is characterized in that the material of injection exposure mask medium is oxidation for the first time
Silicon, second of material for injecting exposure mask medium is polysilicon, and the material that third time injects exposure mask medium is silica.
4. preparation method according to claim 2, which is characterized in that pass through the thickness of the secondary injection exposure mask medium of growth regulation
To adjust the width of second of the injection exposure mask medium side wall formed on the side wall of first time injection exposure mask medium, and then adjusting
Width between the injection region P- and the injection region N+.
5. preparation method according to claim 3, which is characterized in that pass through second of injection exposure mask medium oxidizing time
The size of gate groove window is adjusted, oxidization time is longer, and gate groove window is smaller.
6. preparation method according to claim 1, which is characterized in that inject the corrosion of exposure mask medium by adjusting third time
Time controls the window that third time injects exposure mask.
7. preparation method according to claim 1, which is characterized in that the depth of second of ion implanting be less than for the first time from
The depth of son injection.
8. preparation method according to claim 1, which is characterized in that the depth of the gate groove is infused greater than the first secondary ion
The depth entered.
9. preparation method according to claim 1, which is characterized in that the injection region of third time ion implanting is located at the source
Side wall, top and the bottom of groove, the region of third time ion implanting and the region part of first time ion implanting are overlapping.
10. preparation method according to claim 1, which is characterized in that the first time ion implantation window and the source
Trench openings are formed by photoetching, etching, and second of injection exposure mask medium side wall, the gate groove and the source groove are logical
It crosses dry etching to be formed, the source trench openings are broadened by wet etching.
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| CN111573616A (en) * | 2020-04-24 | 2020-08-25 | 中国电子科技集团公司第十三研究所 | Composite type high depth-to-width ratio groove standard sample plate and preparation method |
| CN113284954A (en) * | 2021-07-22 | 2021-08-20 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
| CN114361242A (en) * | 2022-03-14 | 2022-04-15 | 芯众享(成都)微电子有限公司 | Planar silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of adjusting threshold voltage and preparation method thereof |
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| CN111573616A (en) * | 2020-04-24 | 2020-08-25 | 中国电子科技集团公司第十三研究所 | Composite type high depth-to-width ratio groove standard sample plate and preparation method |
| CN111573616B (en) * | 2020-04-24 | 2024-02-13 | 中国电子科技集团公司第十三研究所 | Composite high aspect ratio groove standard template and preparation method thereof |
| CN113284954A (en) * | 2021-07-22 | 2021-08-20 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
| CN113284954B (en) * | 2021-07-22 | 2021-09-24 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with high channel density and preparation method thereof |
| CN114361242A (en) * | 2022-03-14 | 2022-04-15 | 芯众享(成都)微电子有限公司 | Planar silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of adjusting threshold voltage and preparation method thereof |
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